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wdenk2262cfe2002-11-18 00:14:45 +00001/*
Graeme Russdbf71152011-04-13 19:43:26 +10002 * (C) Copyright 2008-2011
3 * Graeme Russ, <graeme.russ@gmail.com>
Graeme Russ564a9982009-11-24 20:04:18 +11004 *
wdenk2262cfe2002-11-18 00:14:45 +00005 * (C) Copyright 2002
Albert ARIBAUDfa82f872011-08-04 18:45:45 +02006 * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
wdenk2262cfe2002-11-18 00:14:45 +00007 *
Graeme Russ433ff2b2010-04-24 00:05:38 +10008 * Portions of this file are derived from the Linux kernel source
9 * Copyright (C) 1991, 1992 Linus Torvalds
10 *
wdenk2262cfe2002-11-18 00:14:45 +000011 * See file CREDITS for list of people who contributed to this
12 * project.
13 *
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 * MA 02111-1307 USA
28 */
29
30#include <common.h>
Graeme Russ9933d602008-12-07 10:29:01 +110031#include <asm/interrupt.h>
Graeme Russca56a4c2011-02-12 15:11:28 +110032#include <asm/io.h>
Graeme Russ0c24c9c2011-02-12 15:11:32 +110033#include <asm/processor-flags.h>
Graeme Russ717979f2011-11-08 02:33:13 +000034#include <linux/compiler.h>
wdenk2262cfe2002-11-18 00:14:45 +000035
Graeme Russ564a9982009-11-24 20:04:18 +110036#define DECLARE_INTERRUPT(x) \
37 ".globl irq_"#x"\n" \
Graeme Russ0fc1b492009-11-24 20:04:19 +110038 ".hidden irq_"#x"\n" \
39 ".type irq_"#x", @function\n" \
Graeme Russ564a9982009-11-24 20:04:18 +110040 "irq_"#x":\n" \
Graeme Russ564a9982009-11-24 20:04:18 +110041 "pushl $"#x"\n" \
42 "jmp irq_common_entry\n"
wdenk2262cfe2002-11-18 00:14:45 +000043
Graeme Russ433ff2b2010-04-24 00:05:38 +100044/*
45 * Volatile isn't enough to prevent the compiler from reordering the
46 * read/write functions for the control registers and messing everything up.
47 * A memory clobber would solve the problem, but would prevent reordering of
48 * all loads stores around it, which can hurt performance. Solution is to
Graeme Russdbf71152011-04-13 19:43:26 +100049 * use a variable and mimic reads and writes to it to enforce serialisation
Graeme Russ433ff2b2010-04-24 00:05:38 +100050 */
51static unsigned long __force_order;
52
53static inline unsigned long read_cr0(void)
54{
55 unsigned long val;
56 asm volatile("mov %%cr0,%0\n\t" : "=r" (val), "=m" (__force_order));
57 return val;
58}
59
60static inline unsigned long read_cr2(void)
61{
62 unsigned long val;
63 asm volatile("mov %%cr2,%0\n\t" : "=r" (val), "=m" (__force_order));
64 return val;
65}
66
67static inline unsigned long read_cr3(void)
68{
69 unsigned long val;
70 asm volatile("mov %%cr3,%0\n\t" : "=r" (val), "=m" (__force_order));
71 return val;
72}
73
74static inline unsigned long read_cr4(void)
75{
76 unsigned long val;
77 asm volatile("mov %%cr4,%0\n\t" : "=r" (val), "=m" (__force_order));
78 return val;
79}
80
81static inline unsigned long get_debugreg(int regno)
82{
83 unsigned long val = 0; /* Damn you, gcc! */
84
85 switch (regno) {
86 case 0:
Graeme Russ717979f2011-11-08 02:33:13 +000087 asm("mov %%db0, %0" : "=r" (val));
Graeme Russ433ff2b2010-04-24 00:05:38 +100088 break;
89 case 1:
Graeme Russ717979f2011-11-08 02:33:13 +000090 asm("mov %%db1, %0" : "=r" (val));
Graeme Russ433ff2b2010-04-24 00:05:38 +100091 break;
92 case 2:
Graeme Russ717979f2011-11-08 02:33:13 +000093 asm("mov %%db2, %0" : "=r" (val));
Graeme Russ433ff2b2010-04-24 00:05:38 +100094 break;
95 case 3:
Graeme Russ717979f2011-11-08 02:33:13 +000096 asm("mov %%db3, %0" : "=r" (val));
Graeme Russ433ff2b2010-04-24 00:05:38 +100097 break;
98 case 6:
Graeme Russ717979f2011-11-08 02:33:13 +000099 asm("mov %%db6, %0" : "=r" (val));
Graeme Russ433ff2b2010-04-24 00:05:38 +1000100 break;
101 case 7:
Graeme Russ717979f2011-11-08 02:33:13 +0000102 asm("mov %%db7, %0" : "=r" (val));
Graeme Russ433ff2b2010-04-24 00:05:38 +1000103 break;
104 default:
105 val = 0;
106 }
107 return val;
108}
109
Graeme Russ7228efa2010-10-07 20:03:23 +1100110void dump_regs(struct irq_regs *regs)
Graeme Russ433ff2b2010-04-24 00:05:38 +1000111{
112 unsigned long cr0 = 0L, cr2 = 0L, cr3 = 0L, cr4 = 0L;
113 unsigned long d0, d1, d2, d3, d6, d7;
Graeme Russca56a4c2011-02-12 15:11:28 +1100114 unsigned long sp;
Graeme Russ433ff2b2010-04-24 00:05:38 +1000115
116 printf("EIP: %04x:[<%08lx>] EFLAGS: %08lx\n",
117 (u16)regs->xcs, regs->eip, regs->eflags);
118
119 printf("EAX: %08lx EBX: %08lx ECX: %08lx EDX: %08lx\n",
120 regs->eax, regs->ebx, regs->ecx, regs->edx);
121 printf("ESI: %08lx EDI: %08lx EBP: %08lx ESP: %08lx\n",
122 regs->esi, regs->edi, regs->ebp, regs->esp);
123 printf(" DS: %04x ES: %04x FS: %04x GS: %04x SS: %04x\n",
Graeme Russ717979f2011-11-08 02:33:13 +0000124 (u16)regs->xds, (u16)regs->xes, (u16)regs->xfs,
125 (u16)regs->xgs, (u16)regs->xss);
Graeme Russ433ff2b2010-04-24 00:05:38 +1000126
127 cr0 = read_cr0();
128 cr2 = read_cr2();
129 cr3 = read_cr3();
130 cr4 = read_cr4();
131
132 printf("CR0: %08lx CR2: %08lx CR3: %08lx CR4: %08lx\n",
133 cr0, cr2, cr3, cr4);
134
135 d0 = get_debugreg(0);
136 d1 = get_debugreg(1);
137 d2 = get_debugreg(2);
138 d3 = get_debugreg(3);
139
140 printf("DR0: %08lx DR1: %08lx DR2: %08lx DR3: %08lx\n",
141 d0, d1, d2, d3);
142
143 d6 = get_debugreg(6);
144 d7 = get_debugreg(7);
145 printf("DR6: %08lx DR7: %08lx\n",
146 d6, d7);
Graeme Russca56a4c2011-02-12 15:11:28 +1100147
148 printf("Stack:\n");
149 sp = regs->esp;
150
151 sp += 64;
152
153 while (sp > (regs->esp - 16)) {
154 if (sp == regs->esp)
155 printf("--->");
156 else
157 printf(" ");
158 printf("0x%8.8lx : 0x%8.8lx\n", sp, (ulong)readl(sp));
159 sp -= 4;
160 }
Graeme Russ433ff2b2010-04-24 00:05:38 +1000161}
162
wdenk2262cfe2002-11-18 00:14:45 +0000163struct idt_entry {
164 u16 base_low;
165 u16 selector;
166 u8 res;
167 u8 access;
168 u16 base_high;
Graeme Russ717979f2011-11-08 02:33:13 +0000169} __packed;
wdenk2262cfe2002-11-18 00:14:45 +0000170
Graeme Russ564a9982009-11-24 20:04:18 +1100171struct desc_ptr {
172 unsigned short size;
173 unsigned long address;
174 unsigned short segment;
Graeme Russ717979f2011-11-08 02:33:13 +0000175} __packed;
wdenk2262cfe2002-11-18 00:14:45 +0000176
Graeme Russ58c7a672011-12-19 14:26:18 +1100177struct idt_entry idt[256] __aligned(16);
wdenk2262cfe2002-11-18 00:14:45 +0000178
Graeme Russ564a9982009-11-24 20:04:18 +1100179struct desc_ptr idt_ptr;
wdenk2262cfe2002-11-18 00:14:45 +0000180
Graeme Russ564a9982009-11-24 20:04:18 +1100181static inline void load_idt(const struct desc_ptr *dtr)
182{
Graeme Russ717979f2011-11-08 02:33:13 +0000183 asm volatile("cs lidt %0" : : "m" (*dtr));
Graeme Russ564a9982009-11-24 20:04:18 +1100184}
wdenk2262cfe2002-11-18 00:14:45 +0000185
Graeme Russabf0cd32009-02-24 21:13:40 +1100186void set_vector(u8 intnum, void *routine)
wdenk2262cfe2002-11-18 00:14:45 +0000187{
Graeme Russ1c409bc2009-11-24 20:04:21 +1100188 idt[intnum].base_high = (u16)((u32)(routine) >> 16);
189 idt[intnum].base_low = (u16)((u32)(routine) & 0xffff);
wdenk2262cfe2002-11-18 00:14:45 +0000190}
191
Graeme Russ717979f2011-11-08 02:33:13 +0000192/*
193 * Ideally these would be defined static to avoid a checkpatch warning, but
194 * the compiler cannot see them in the inline asm and complains that they
195 * aren't defined
196 */
Graeme Russ564a9982009-11-24 20:04:18 +1100197void irq_0(void);
198void irq_1(void);
wdenk2262cfe2002-11-18 00:14:45 +0000199
Graeme Russabf0cd32009-02-24 21:13:40 +1100200int cpu_init_interrupts(void)
wdenk2262cfe2002-11-18 00:14:45 +0000201{
202 int i;
wdenk8bde7f72003-06-27 21:31:46 +0000203
Graeme Russ564a9982009-11-24 20:04:18 +1100204 int irq_entry_size = irq_1 - irq_0;
205 void *irq_entry = (void *)irq_0;
206
wdenk2262cfe2002-11-18 00:14:45 +0000207 /* Just in case... */
208 disable_interrupts();
wdenk8bde7f72003-06-27 21:31:46 +0000209
wdenk2262cfe2002-11-18 00:14:45 +0000210 /* Setup the IDT */
Graeme Russ717979f2011-11-08 02:33:13 +0000211 for (i = 0; i < 256; i++) {
wdenk2262cfe2002-11-18 00:14:45 +0000212 idt[i].access = 0x8e;
wdenk8bde7f72003-06-27 21:31:46 +0000213 idt[i].res = 0;
214 idt[i].selector = 0x10;
Graeme Russ564a9982009-11-24 20:04:18 +1100215 set_vector(i, irq_entry);
216 irq_entry += irq_entry_size;
wdenk8bde7f72003-06-27 21:31:46 +0000217 }
218
Graeme Russ564a9982009-11-24 20:04:18 +1100219 idt_ptr.size = 256 * 8;
220 idt_ptr.address = (unsigned long) idt;
221 idt_ptr.segment = 0x18;
222
223 load_idt(&idt_ptr);
wdenk8bde7f72003-06-27 21:31:46 +0000224
wdenk2262cfe2002-11-18 00:14:45 +0000225 /* It is now safe to enable interrupts */
wdenk8bde7f72003-06-27 21:31:46 +0000226 enable_interrupts();
227
wdenk2262cfe2002-11-18 00:14:45 +0000228 return 0;
229}
230
Graeme Russ564a9982009-11-24 20:04:18 +1100231void __do_irq(int irq)
232{
233 printf("Unhandled IRQ : %d\n", irq);
234}
235void do_irq(int irq) __attribute__((weak, alias("__do_irq")));
236
wdenk2262cfe2002-11-18 00:14:45 +0000237void enable_interrupts(void)
238{
239 asm("sti\n");
240}
241
242int disable_interrupts(void)
243{
244 long flags;
wdenk8bde7f72003-06-27 21:31:46 +0000245
wdenk2262cfe2002-11-18 00:14:45 +0000246 asm volatile ("pushfl ; popl %0 ; cli\n" : "=g" (flags) : );
wdenk8bde7f72003-06-27 21:31:46 +0000247
Graeme Russ717979f2011-11-08 02:33:13 +0000248 return flags & X86_EFLAGS_IF;
wdenk2262cfe2002-11-18 00:14:45 +0000249}
Graeme Russ564a9982009-11-24 20:04:18 +1100250
251/* IRQ Low-Level Service Routine */
Graeme Russ7228efa2010-10-07 20:03:23 +1100252void irq_llsr(struct irq_regs *regs)
Graeme Russ564a9982009-11-24 20:04:18 +1100253{
254 /*
255 * For detailed description of each exception, refer to:
Albert ARIBAUDfa82f872011-08-04 18:45:45 +0200256 * Intel® 64 and IA-32 Architectures Software Developer's Manual
Graeme Russ564a9982009-11-24 20:04:18 +1100257 * Volume 1: Basic Architecture
258 * Order Number: 253665-029US, November 2008
259 * Table 6-1. Exceptions and Interrupts
260 */
Graeme Russ7228efa2010-10-07 20:03:23 +1100261 switch (regs->irq_id) {
Graeme Russ564a9982009-11-24 20:04:18 +1100262 case 0x00:
Graeme Russ433ff2b2010-04-24 00:05:38 +1000263 printf("Divide Error (Division by zero)\n");
264 dump_regs(regs);
Graeme Russ6d7404c2011-11-08 02:33:12 +0000265 hang();
Graeme Russ564a9982009-11-24 20:04:18 +1100266 break;
267 case 0x01:
Graeme Russ433ff2b2010-04-24 00:05:38 +1000268 printf("Debug Interrupt (Single step)\n");
269 dump_regs(regs);
Graeme Russ564a9982009-11-24 20:04:18 +1100270 break;
271 case 0x02:
Graeme Russ433ff2b2010-04-24 00:05:38 +1000272 printf("NMI Interrupt\n");
273 dump_regs(regs);
Graeme Russ564a9982009-11-24 20:04:18 +1100274 break;
275 case 0x03:
Graeme Russ433ff2b2010-04-24 00:05:38 +1000276 printf("Breakpoint\n");
277 dump_regs(regs);
Graeme Russ564a9982009-11-24 20:04:18 +1100278 break;
279 case 0x04:
Graeme Russ433ff2b2010-04-24 00:05:38 +1000280 printf("Overflow\n");
281 dump_regs(regs);
Graeme Russ6d7404c2011-11-08 02:33:12 +0000282 hang();
Graeme Russ564a9982009-11-24 20:04:18 +1100283 break;
284 case 0x05:
Graeme Russ433ff2b2010-04-24 00:05:38 +1000285 printf("BOUND Range Exceeded\n");
286 dump_regs(regs);
Graeme Russ6d7404c2011-11-08 02:33:12 +0000287 hang();
Graeme Russ564a9982009-11-24 20:04:18 +1100288 break;
289 case 0x06:
Graeme Russ433ff2b2010-04-24 00:05:38 +1000290 printf("Invalid Opcode (UnDefined Opcode)\n");
291 dump_regs(regs);
Graeme Russ6d7404c2011-11-08 02:33:12 +0000292 hang();
Graeme Russ564a9982009-11-24 20:04:18 +1100293 break;
294 case 0x07:
Graeme Russ433ff2b2010-04-24 00:05:38 +1000295 printf("Device Not Available (No Math Coprocessor)\n");
296 dump_regs(regs);
Graeme Russ6d7404c2011-11-08 02:33:12 +0000297 hang();
Graeme Russ564a9982009-11-24 20:04:18 +1100298 break;
299 case 0x08:
Graeme Russ433ff2b2010-04-24 00:05:38 +1000300 printf("Double fault\n");
301 dump_regs(regs);
Graeme Russ6d7404c2011-11-08 02:33:12 +0000302 hang();
Graeme Russ564a9982009-11-24 20:04:18 +1100303 break;
304 case 0x09:
Graeme Russ433ff2b2010-04-24 00:05:38 +1000305 printf("Co-processor segment overrun\n");
306 dump_regs(regs);
Graeme Russ6d7404c2011-11-08 02:33:12 +0000307 hang();
Graeme Russ564a9982009-11-24 20:04:18 +1100308 break;
309 case 0x0a:
Graeme Russ433ff2b2010-04-24 00:05:38 +1000310 printf("Invalid TSS\n");
311 dump_regs(regs);
Graeme Russ564a9982009-11-24 20:04:18 +1100312 break;
313 case 0x0b:
Graeme Russ433ff2b2010-04-24 00:05:38 +1000314 printf("Segment Not Present\n");
315 dump_regs(regs);
Graeme Russ6d7404c2011-11-08 02:33:12 +0000316 hang();
Graeme Russ564a9982009-11-24 20:04:18 +1100317 break;
318 case 0x0c:
Graeme Russ433ff2b2010-04-24 00:05:38 +1000319 printf("Stack Segment Fault\n");
320 dump_regs(regs);
Graeme Russ6d7404c2011-11-08 02:33:12 +0000321 hang();
Graeme Russ564a9982009-11-24 20:04:18 +1100322 break;
323 case 0x0d:
Graeme Russ433ff2b2010-04-24 00:05:38 +1000324 printf("General Protection\n");
325 dump_regs(regs);
Graeme Russ564a9982009-11-24 20:04:18 +1100326 break;
327 case 0x0e:
Graeme Russ433ff2b2010-04-24 00:05:38 +1000328 printf("Page fault\n");
329 dump_regs(regs);
Graeme Russ6d7404c2011-11-08 02:33:12 +0000330 hang();
Graeme Russ564a9982009-11-24 20:04:18 +1100331 break;
332 case 0x0f:
Graeme Russ433ff2b2010-04-24 00:05:38 +1000333 printf("Floating-Point Error (Math Fault)\n");
334 dump_regs(regs);
Graeme Russ564a9982009-11-24 20:04:18 +1100335 break;
336 case 0x10:
Graeme Russ433ff2b2010-04-24 00:05:38 +1000337 printf("Alignment check\n");
338 dump_regs(regs);
Graeme Russ564a9982009-11-24 20:04:18 +1100339 break;
340 case 0x11:
Graeme Russ433ff2b2010-04-24 00:05:38 +1000341 printf("Machine Check\n");
342 dump_regs(regs);
Graeme Russ564a9982009-11-24 20:04:18 +1100343 break;
344 case 0x12:
Graeme Russ433ff2b2010-04-24 00:05:38 +1000345 printf("SIMD Floating-Point Exception\n");
346 dump_regs(regs);
Graeme Russ564a9982009-11-24 20:04:18 +1100347 break;
348 case 0x13:
349 case 0x14:
350 case 0x15:
351 case 0x16:
352 case 0x17:
353 case 0x18:
354 case 0x19:
355 case 0x1a:
356 case 0x1b:
357 case 0x1c:
358 case 0x1d:
359 case 0x1e:
360 case 0x1f:
Graeme Russ433ff2b2010-04-24 00:05:38 +1000361 printf("Reserved Exception\n");
362 dump_regs(regs);
Graeme Russ564a9982009-11-24 20:04:18 +1100363 break;
364
365 default:
366 /* Hardware or User IRQ */
Graeme Russ7228efa2010-10-07 20:03:23 +1100367 do_irq(regs->irq_id);
Graeme Russ564a9982009-11-24 20:04:18 +1100368 }
369}
370
371/*
372 * OK - This looks really horrible, but it serves a purpose - It helps create
373 * fully relocatable code.
374 * - The call to irq_llsr will be a relative jump
375 * - The IRQ entries will be guaranteed to be in order
Graeme Russ433ff2b2010-04-24 00:05:38 +1000376 * Interrupt entries are now very small (a push and a jump) but they are
377 * now slower (all registers pushed on stack which provides complete
378 * crash dumps in the low level handlers
Graeme Russ7228efa2010-10-07 20:03:23 +1100379 *
380 * Interrupt Entry Point:
381 * - Interrupt has caused eflags, CS and EIP to be pushed
382 * - Interrupt Vector Handler has pushed orig_eax
383 * - pt_regs.esp needs to be adjusted by 40 bytes:
384 * 12 bytes pushed by CPU (EFLAGSF, CS, EIP)
385 * 4 bytes pushed by vector handler (irq_id)
386 * 24 bytes pushed before SP (SS, GS, FS, ES, DS, EAX)
387 * NOTE: Only longs are pushed on/popped off the stack!
Graeme Russ564a9982009-11-24 20:04:18 +1100388 */
389asm(".globl irq_common_entry\n" \
Graeme Russ0fc1b492009-11-24 20:04:19 +1100390 ".hidden irq_common_entry\n" \
391 ".type irq_common_entry, @function\n" \
Graeme Russ564a9982009-11-24 20:04:18 +1100392 "irq_common_entry:\n" \
Graeme Russ433ff2b2010-04-24 00:05:38 +1000393 "cld\n" \
Graeme Russ7228efa2010-10-07 20:03:23 +1100394 "pushl %ss\n" \
Graeme Russ433ff2b2010-04-24 00:05:38 +1000395 "pushl %gs\n" \
396 "pushl %fs\n" \
397 "pushl %es\n" \
398 "pushl %ds\n" \
399 "pushl %eax\n" \
Graeme Russ7228efa2010-10-07 20:03:23 +1100400 "movl %esp, %eax\n" \
401 "addl $40, %eax\n" \
402 "pushl %eax\n" \
Graeme Russ433ff2b2010-04-24 00:05:38 +1000403 "pushl %ebp\n" \
404 "pushl %edi\n" \
405 "pushl %esi\n" \
406 "pushl %edx\n" \
407 "pushl %ecx\n" \
408 "pushl %ebx\n" \
409 "mov %esp, %eax\n" \
Graeme Russ564a9982009-11-24 20:04:18 +1100410 "call irq_llsr\n" \
Graeme Russ433ff2b2010-04-24 00:05:38 +1000411 "popl %ebx\n" \
412 "popl %ecx\n" \
413 "popl %edx\n" \
414 "popl %esi\n" \
415 "popl %edi\n" \
416 "popl %ebp\n" \
417 "popl %eax\n" \
Graeme Russ7228efa2010-10-07 20:03:23 +1100418 "popl %eax\n" \
Graeme Russ433ff2b2010-04-24 00:05:38 +1000419 "popl %ds\n" \
420 "popl %es\n" \
421 "popl %fs\n" \
422 "popl %gs\n" \
Graeme Russ7228efa2010-10-07 20:03:23 +1100423 "popl %ss\n" \
Graeme Russ433ff2b2010-04-24 00:05:38 +1000424 "add $4, %esp\n" \
Graeme Russ564a9982009-11-24 20:04:18 +1100425 "iret\n" \
426 DECLARE_INTERRUPT(0) \
427 DECLARE_INTERRUPT(1) \
428 DECLARE_INTERRUPT(2) \
429 DECLARE_INTERRUPT(3) \
430 DECLARE_INTERRUPT(4) \
431 DECLARE_INTERRUPT(5) \
432 DECLARE_INTERRUPT(6) \
433 DECLARE_INTERRUPT(7) \
434 DECLARE_INTERRUPT(8) \
435 DECLARE_INTERRUPT(9) \
436 DECLARE_INTERRUPT(10) \
437 DECLARE_INTERRUPT(11) \
438 DECLARE_INTERRUPT(12) \
439 DECLARE_INTERRUPT(13) \
440 DECLARE_INTERRUPT(14) \
441 DECLARE_INTERRUPT(15) \
442 DECLARE_INTERRUPT(16) \
443 DECLARE_INTERRUPT(17) \
444 DECLARE_INTERRUPT(18) \
445 DECLARE_INTERRUPT(19) \
446 DECLARE_INTERRUPT(20) \
447 DECLARE_INTERRUPT(21) \
448 DECLARE_INTERRUPT(22) \
449 DECLARE_INTERRUPT(23) \
450 DECLARE_INTERRUPT(24) \
451 DECLARE_INTERRUPT(25) \
452 DECLARE_INTERRUPT(26) \
453 DECLARE_INTERRUPT(27) \
454 DECLARE_INTERRUPT(28) \
455 DECLARE_INTERRUPT(29) \
456 DECLARE_INTERRUPT(30) \
457 DECLARE_INTERRUPT(31) \
458 DECLARE_INTERRUPT(32) \
459 DECLARE_INTERRUPT(33) \
460 DECLARE_INTERRUPT(34) \
461 DECLARE_INTERRUPT(35) \
462 DECLARE_INTERRUPT(36) \
463 DECLARE_INTERRUPT(37) \
464 DECLARE_INTERRUPT(38) \
465 DECLARE_INTERRUPT(39) \
466 DECLARE_INTERRUPT(40) \
467 DECLARE_INTERRUPT(41) \
468 DECLARE_INTERRUPT(42) \
469 DECLARE_INTERRUPT(43) \
470 DECLARE_INTERRUPT(44) \
471 DECLARE_INTERRUPT(45) \
472 DECLARE_INTERRUPT(46) \
473 DECLARE_INTERRUPT(47) \
474 DECLARE_INTERRUPT(48) \
475 DECLARE_INTERRUPT(49) \
476 DECLARE_INTERRUPT(50) \
477 DECLARE_INTERRUPT(51) \
478 DECLARE_INTERRUPT(52) \
479 DECLARE_INTERRUPT(53) \
480 DECLARE_INTERRUPT(54) \
481 DECLARE_INTERRUPT(55) \
482 DECLARE_INTERRUPT(56) \
483 DECLARE_INTERRUPT(57) \
484 DECLARE_INTERRUPT(58) \
485 DECLARE_INTERRUPT(59) \
486 DECLARE_INTERRUPT(60) \
487 DECLARE_INTERRUPT(61) \
488 DECLARE_INTERRUPT(62) \
489 DECLARE_INTERRUPT(63) \
490 DECLARE_INTERRUPT(64) \
491 DECLARE_INTERRUPT(65) \
492 DECLARE_INTERRUPT(66) \
493 DECLARE_INTERRUPT(67) \
494 DECLARE_INTERRUPT(68) \
495 DECLARE_INTERRUPT(69) \
496 DECLARE_INTERRUPT(70) \
497 DECLARE_INTERRUPT(71) \
498 DECLARE_INTERRUPT(72) \
499 DECLARE_INTERRUPT(73) \
500 DECLARE_INTERRUPT(74) \
501 DECLARE_INTERRUPT(75) \
502 DECLARE_INTERRUPT(76) \
503 DECLARE_INTERRUPT(77) \
504 DECLARE_INTERRUPT(78) \
505 DECLARE_INTERRUPT(79) \
506 DECLARE_INTERRUPT(80) \
507 DECLARE_INTERRUPT(81) \
508 DECLARE_INTERRUPT(82) \
509 DECLARE_INTERRUPT(83) \
510 DECLARE_INTERRUPT(84) \
511 DECLARE_INTERRUPT(85) \
512 DECLARE_INTERRUPT(86) \
513 DECLARE_INTERRUPT(87) \
514 DECLARE_INTERRUPT(88) \
515 DECLARE_INTERRUPT(89) \
516 DECLARE_INTERRUPT(90) \
517 DECLARE_INTERRUPT(91) \
518 DECLARE_INTERRUPT(92) \
519 DECLARE_INTERRUPT(93) \
520 DECLARE_INTERRUPT(94) \
521 DECLARE_INTERRUPT(95) \
522 DECLARE_INTERRUPT(97) \
523 DECLARE_INTERRUPT(96) \
524 DECLARE_INTERRUPT(98) \
525 DECLARE_INTERRUPT(99) \
526 DECLARE_INTERRUPT(100) \
527 DECLARE_INTERRUPT(101) \
528 DECLARE_INTERRUPT(102) \
529 DECLARE_INTERRUPT(103) \
530 DECLARE_INTERRUPT(104) \
531 DECLARE_INTERRUPT(105) \
532 DECLARE_INTERRUPT(106) \
533 DECLARE_INTERRUPT(107) \
534 DECLARE_INTERRUPT(108) \
535 DECLARE_INTERRUPT(109) \
536 DECLARE_INTERRUPT(110) \
537 DECLARE_INTERRUPT(111) \
538 DECLARE_INTERRUPT(112) \
539 DECLARE_INTERRUPT(113) \
540 DECLARE_INTERRUPT(114) \
541 DECLARE_INTERRUPT(115) \
542 DECLARE_INTERRUPT(116) \
543 DECLARE_INTERRUPT(117) \
544 DECLARE_INTERRUPT(118) \
545 DECLARE_INTERRUPT(119) \
546 DECLARE_INTERRUPT(120) \
547 DECLARE_INTERRUPT(121) \
548 DECLARE_INTERRUPT(122) \
549 DECLARE_INTERRUPT(123) \
550 DECLARE_INTERRUPT(124) \
551 DECLARE_INTERRUPT(125) \
552 DECLARE_INTERRUPT(126) \
553 DECLARE_INTERRUPT(127) \
554 DECLARE_INTERRUPT(128) \
555 DECLARE_INTERRUPT(129) \
556 DECLARE_INTERRUPT(130) \
557 DECLARE_INTERRUPT(131) \
558 DECLARE_INTERRUPT(132) \
559 DECLARE_INTERRUPT(133) \
560 DECLARE_INTERRUPT(134) \
561 DECLARE_INTERRUPT(135) \
562 DECLARE_INTERRUPT(136) \
563 DECLARE_INTERRUPT(137) \
564 DECLARE_INTERRUPT(138) \
565 DECLARE_INTERRUPT(139) \
566 DECLARE_INTERRUPT(140) \
567 DECLARE_INTERRUPT(141) \
568 DECLARE_INTERRUPT(142) \
569 DECLARE_INTERRUPT(143) \
570 DECLARE_INTERRUPT(144) \
571 DECLARE_INTERRUPT(145) \
572 DECLARE_INTERRUPT(146) \
573 DECLARE_INTERRUPT(147) \
574 DECLARE_INTERRUPT(148) \
575 DECLARE_INTERRUPT(149) \
576 DECLARE_INTERRUPT(150) \
577 DECLARE_INTERRUPT(151) \
578 DECLARE_INTERRUPT(152) \
579 DECLARE_INTERRUPT(153) \
580 DECLARE_INTERRUPT(154) \
581 DECLARE_INTERRUPT(155) \
582 DECLARE_INTERRUPT(156) \
583 DECLARE_INTERRUPT(157) \
584 DECLARE_INTERRUPT(158) \
585 DECLARE_INTERRUPT(159) \
586 DECLARE_INTERRUPT(160) \
587 DECLARE_INTERRUPT(161) \
588 DECLARE_INTERRUPT(162) \
589 DECLARE_INTERRUPT(163) \
590 DECLARE_INTERRUPT(164) \
591 DECLARE_INTERRUPT(165) \
592 DECLARE_INTERRUPT(166) \
593 DECLARE_INTERRUPT(167) \
594 DECLARE_INTERRUPT(168) \
595 DECLARE_INTERRUPT(169) \
596 DECLARE_INTERRUPT(170) \
597 DECLARE_INTERRUPT(171) \
598 DECLARE_INTERRUPT(172) \
599 DECLARE_INTERRUPT(173) \
600 DECLARE_INTERRUPT(174) \
601 DECLARE_INTERRUPT(175) \
602 DECLARE_INTERRUPT(176) \
603 DECLARE_INTERRUPT(177) \
604 DECLARE_INTERRUPT(178) \
605 DECLARE_INTERRUPT(179) \
606 DECLARE_INTERRUPT(180) \
607 DECLARE_INTERRUPT(181) \
608 DECLARE_INTERRUPT(182) \
609 DECLARE_INTERRUPT(183) \
610 DECLARE_INTERRUPT(184) \
611 DECLARE_INTERRUPT(185) \
612 DECLARE_INTERRUPT(186) \
613 DECLARE_INTERRUPT(187) \
614 DECLARE_INTERRUPT(188) \
615 DECLARE_INTERRUPT(189) \
616 DECLARE_INTERRUPT(190) \
617 DECLARE_INTERRUPT(191) \
618 DECLARE_INTERRUPT(192) \
619 DECLARE_INTERRUPT(193) \
620 DECLARE_INTERRUPT(194) \
621 DECLARE_INTERRUPT(195) \
622 DECLARE_INTERRUPT(196) \
623 DECLARE_INTERRUPT(197) \
624 DECLARE_INTERRUPT(198) \
625 DECLARE_INTERRUPT(199) \
626 DECLARE_INTERRUPT(200) \
627 DECLARE_INTERRUPT(201) \
628 DECLARE_INTERRUPT(202) \
629 DECLARE_INTERRUPT(203) \
630 DECLARE_INTERRUPT(204) \
631 DECLARE_INTERRUPT(205) \
632 DECLARE_INTERRUPT(206) \
633 DECLARE_INTERRUPT(207) \
634 DECLARE_INTERRUPT(208) \
635 DECLARE_INTERRUPT(209) \
636 DECLARE_INTERRUPT(210) \
637 DECLARE_INTERRUPT(211) \
638 DECLARE_INTERRUPT(212) \
639 DECLARE_INTERRUPT(213) \
640 DECLARE_INTERRUPT(214) \
641 DECLARE_INTERRUPT(215) \
642 DECLARE_INTERRUPT(216) \
643 DECLARE_INTERRUPT(217) \
644 DECLARE_INTERRUPT(218) \
645 DECLARE_INTERRUPT(219) \
646 DECLARE_INTERRUPT(220) \
647 DECLARE_INTERRUPT(221) \
648 DECLARE_INTERRUPT(222) \
649 DECLARE_INTERRUPT(223) \
650 DECLARE_INTERRUPT(224) \
651 DECLARE_INTERRUPT(225) \
652 DECLARE_INTERRUPT(226) \
653 DECLARE_INTERRUPT(227) \
654 DECLARE_INTERRUPT(228) \
655 DECLARE_INTERRUPT(229) \
656 DECLARE_INTERRUPT(230) \
657 DECLARE_INTERRUPT(231) \
658 DECLARE_INTERRUPT(232) \
659 DECLARE_INTERRUPT(233) \
660 DECLARE_INTERRUPT(234) \
661 DECLARE_INTERRUPT(235) \
662 DECLARE_INTERRUPT(236) \
663 DECLARE_INTERRUPT(237) \
664 DECLARE_INTERRUPT(238) \
665 DECLARE_INTERRUPT(239) \
666 DECLARE_INTERRUPT(240) \
667 DECLARE_INTERRUPT(241) \
668 DECLARE_INTERRUPT(242) \
669 DECLARE_INTERRUPT(243) \
670 DECLARE_INTERRUPT(244) \
671 DECLARE_INTERRUPT(245) \
672 DECLARE_INTERRUPT(246) \
673 DECLARE_INTERRUPT(247) \
674 DECLARE_INTERRUPT(248) \
675 DECLARE_INTERRUPT(249) \
676 DECLARE_INTERRUPT(250) \
677 DECLARE_INTERRUPT(251) \
678 DECLARE_INTERRUPT(252) \
679 DECLARE_INTERRUPT(253) \
680 DECLARE_INTERRUPT(254) \
681 DECLARE_INTERRUPT(255));