blob: c4feef8196ec3c979cbd62a4449a1ccf68b5e811 [file] [log] [blame]
Heiko Schocher4e43b2e2010-07-07 12:26:34 +02001/*
2 * Copyright (C) Freescale Semiconductor, Inc. 2006-2007
3 *
4 * Author: Scott Wood <scottwood@freescale.com>
5 *
6 * (C) Copyright 2010
7 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
8 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02009 * SPDX-License-Identifier: GPL-2.0+
Heiko Schocher4e43b2e2010-07-07 12:26:34 +020010 */
11
12#include <common.h>
13#include <libfdt.h>
14#include <pci.h>
15#include <mpc83xx.h>
16#include <ns16550.h>
17#include <nand.h>
18
19#include <asm/bitops.h>
20#include <asm/io.h>
21
22DECLARE_GLOBAL_DATA_PTR;
23
24extern void disable_addr_trans (void);
25extern void enable_addr_trans (void);
26
27int checkboard(void)
28{
29 puts("Board: ve8313\n");
30 return 0;
31}
32
33static long fixed_sdram(void)
34{
35 u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
36
37#ifndef CONFIG_SYS_RAMBOOT
38 volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
39 u32 msize_log2 = __ilog2(msize);
40
41 out_be32(&im->sysconf.ddrlaw[0].bar,
42 (CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000));
43 out_be32(&im->sysconf.ddrlaw[0].ar, (LBLAWAR_EN | (msize_log2 - 1)));
44 out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE);
45
46 /*
47 * Erratum DDR3 requires a 50ms delay after clearing DDRCDR[DDR_cfg],
48 * or the DDR2 controller may fail to initialize correctly.
49 */
50 __udelay(50000);
51
Joe Hershberger2e651b22011-10-11 23:57:31 -050052#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0)
53#warning Chip select bounds is only configurable in 16MB increments
54#endif
55 out_be32(&im->ddr.csbnds[0].csbnds,
56 ((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
57 (((CONFIG_SYS_DDR_SDRAM_BASE + msize - 1) >> CSBNDS_EA_SHIFT) &
58 CSBNDS_EA));
59 out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG);
Heiko Schocher4e43b2e2010-07-07 12:26:34 +020060
61 /* Currently we use only one CS, so disable the other bank. */
62 out_be32(&im->ddr.cs_config[1], 0);
63
64 out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CNTL);
65 out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
66 out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
67 out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
68 out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
69
70 out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_SDRAM_CFG);
71
72 out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_SDRAM_CFG2);
73 out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE);
74 out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE_2);
75
76 out_be32(&im->ddr.sdram_interval, CONFIG_SYS_DDR_INTERVAL);
77 sync();
78
79 /* enable DDR controller */
80 setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
81
82 /* now check the real size */
83 disable_addr_trans ();
84 msize = get_ram_size (CONFIG_SYS_DDR_BASE, msize);
85 enable_addr_trans ();
86#endif
87
88 return msize;
89}
90
91phys_size_t initdram(int board_type)
92{
93 volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
Kumar Galaa2243b82010-08-19 01:48:14 -050094 volatile fsl_lbc_t *lbc = &im->im_lbc;
Heiko Schocher4e43b2e2010-07-07 12:26:34 +020095 u32 msize;
96
97 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
98 return -1;
99
100 /* DDR SDRAM - Main SODIMM */
101 msize = fixed_sdram();
102
103 /* Local Bus setup lbcr and mrtpr */
104 out_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR);
105 out_be32(&lbc->mrtpr, CONFIG_SYS_LBC_MRTPR);
106 sync();
107
108 /* return total bus SDRAM size(bytes) -- DDR */
109 return msize;
110}
111
112#define VE8313_WDT_EN 0x00020000
113#define VE8313_WDT_TRIG 0x00040000
114
115int board_early_init_f (void)
116{
117 volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
118 volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)im->gpio;
119
120#if defined(CONFIG_HW_WATCHDOG)
121 /* enable WDT */
122 clrbits_be32(&gpio->dat, VE8313_WDT_EN | VE8313_WDT_TRIG);
123#else
124 /* disable WDT */
125 setbits_be32(&gpio->dat, VE8313_WDT_EN | VE8313_WDT_TRIG);
126#endif
127 /* set WDT pins as output */
128 setbits_be32(&gpio->dir, VE8313_WDT_EN | VE8313_WDT_TRIG);
129
130 return 0;
131}
132
133#if defined(CONFIG_HW_WATCHDOG)
134void hw_watchdog_reset(void)
135{
136 volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
137 volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)im->gpio;
138 unsigned long reg;
139
140 reg = in_be32(&gpio->dat);
141 if (reg & VE8313_WDT_TRIG)
142 clrbits_be32(&gpio->dat, VE8313_WDT_TRIG);
143 else
144 setbits_be32(&gpio->dat, VE8313_WDT_TRIG);
145}
146#endif
147
148
149#if defined(CONFIG_PCI)
150static struct pci_region pci_regions[] = {
151 {
152 bus_start: CONFIG_SYS_PCI1_MEM_BASE,
153 phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
154 size: CONFIG_SYS_PCI1_MEM_SIZE,
155 flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
156 },
157 {
158 bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
159 phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
160 size: CONFIG_SYS_PCI1_MMIO_SIZE,
161 flags: PCI_REGION_MEM
162 },
163 {
164 bus_start: CONFIG_SYS_PCI1_IO_BASE,
165 phys_start: CONFIG_SYS_PCI1_IO_PHYS,
166 size: CONFIG_SYS_PCI1_IO_SIZE,
167 flags: PCI_REGION_IO
168 }
169};
170
171void pci_init_board(void)
172{
173 volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
174 volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
175 volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
176 struct pci_region *reg[] = { pci_regions };
Heiko Schocher4e43b2e2010-07-07 12:26:34 +0200177
178 /* Enable all 3 PCI_CLK_OUTPUTs. */
179 setbits_be32(&clk->occr, 0xe0000000);
180
181 /*
182 * Configure PCI Local Access Windows
183 */
184 out_be32(&pci_law[0].bar, CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR);
185 out_be32(&pci_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
186
187 out_be32(&pci_law[1].bar, CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR);
188 out_be32(&pci_law[1].ar, LBLAWAR_EN | LBLAWAR_1MB);
189
Peter Tyser6aa3d3b2010-09-14 19:13:50 -0500190 mpc83xx_pci_init(1, reg);
Heiko Schocher4e43b2e2010-07-07 12:26:34 +0200191}
192#endif
193
194#if defined(CONFIG_OF_BOARD_SETUP)
195void ft_board_setup(void *blob, bd_t *bd)
196{
197 ft_cpu_setup(blob, bd);
198#ifdef CONFIG_PCI
199 ft_pci_setup(blob, bd);
200#endif
201}
202#endif