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Jagannadha Sutradharudu Tekif77f4692014-01-12 21:40:11 +05301SPI/QSPI Dual flash connection modes:
2=====================================
3
4This describes how SPI/QSPI flash memories are connected to a given
5controller in a single chip select line.
6
7Current spi_flash framework supports, single flash memory connected
8to a given controller with single chip select line, but there are some
9hw logics(ex: xilinx zynq qspi) that describes two/dual memories are
10connected with a single chip select line from a controller.
11
12"dual_flash" from include/spi.h describes these types of connection mode
13
14Possible connections:
15--------------------
16SF_SINGLE_FLASH:
17 - single spi flash memory connected with single chip select line.
18
19 +------------+ CS +---------------+
20 | |----------------------->| |
21 | Controller | I0[3:0] | Flash memory |
22 | SPI/QSPI |<======================>| (SPI/QSPI) |
23 | | CLK | |
24 | |----------------------->| |
25 +------------+ +---------------+
26
27SF_DUAL_STACKED_FLASH:
28 - dual spi/qspi flash memories are connected with a single chipselect
29 line and these two memories are operating stacked fasion with shared buses.
30 - xilinx zynq qspi controller has implemented this feature [1]
31
32 +------------+ CS +---------------+
33 | |---------------------->| |
34 | | I0[3:0] | Upper Flash |
35 | | +=========>| memory |
36 | | | CLK | (SPI/QSPI) |
37 | | | +---->| |
38 | Controller | CS | | +---------------+
39 | SPI/QSPI |------------|----|---->| |
40 | | I0[3:0] | | | Lower Flash |
41 | |<===========+====|====>| memory |
42 | | CLK | | (SPI/QSPI) |
43 | |-----------------+---->| |
44 +------------+ +---------------+
45
46 - two memory flash devices should has same hw part attributes (like size,
47 vendor..etc)
48 - Configurations:
49 on LQSPI_CFG register, Enable TWO_MEM[BIT:30] on LQSPI_CFG
50 Enable U_PAGE[BIT:28] if U_PAGE flag set - upper memory
51 Disable U_PAGE[BIT:28] if U_PAGE flag unset - lower memory
52 - Operation:
53 accessing memories serially like one after another.
54 by default, if U_PAGE is unset lower memory should accessible,
55 once user wants to access upper memory need to set U_PAGE.
56
Jagannadha Sutradharudu Teki056fbc72014-01-07 00:11:35 +053057SPI_FLASH_CONN_DUALPARALLEL:
58 - dual spi/qspi flash memories are connected with a single chipselect
59 line and these two memories are operating parallel with separate buses.
60 - xilinx zynq qspi controller has implemented this feature [1]
61
62 +-------------+ CS +---------------+
63 | |---------------------->| |
64 | | I0[3:0] | Upper Flash |
65 | |<=====================>| memory |
66 | | CLK | (SPI/QSPI) |
67 | |---------------------->| |
68 | Controller | CS +---------------+
69 | SPI/QSPI |---------------------->| |
70 | | I0[3:0] | Lower Flash |
71 | |<=====================>| memory |
72 | | CLK | (SPI/QSPI) |
73 | |---------------------->| |
74 +-------------+ +---------------+
75
76 - two memory flash devices should has same hw part attributes (like size,
77 vendor..etc)
78 - Configurations:
79 Need to enable SEP_BUS[BIT:29],TWO_MEM[BIT:30] on LQSPI_CFG register.
80 - Operation:
81 Even bits, i.e. bit 0, 2, 4 ., of a data word is located in the lower memory
82 and odd bits, i.e. bit 1, 3, 5, ., of a data word is located in the upper memory.
83
Jagannadha Sutradharudu Tekif77f4692014-01-12 21:40:11 +053084Note: Technically there is only one CS line from the controller, but
85zynq qspi controller has an internal hw logic to enable additional CS
86when controller is configured for dual memories.
87
88[1] http://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf
89
90--
91Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
9205-01-2014.