blob: 95b7d8246ee480505f638b4fc6af9c2ea8d37c29 [file] [log] [blame]
Wolfgang Denk265817c2005-09-25 00:53:22 +02001/*
2 * (C) Copyright 2003
3 * Thomas.Lange@corelatus.se
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <common.h>
25#include <command.h>
26#include <asm/au1x00.h>
27#include <asm/mipsregs.h>
Jean-Christophe PLAGNIOL-VILLARD5c150102007-11-13 09:11:05 +010028#include <asm/io.h>
Wolfgang Denk265817c2005-09-25 00:53:22 +020029
30long int initdram(int board_type)
31{
32 /* Sdram is setup by assembler code */
33 /* If memory could be changed, we should return the true value here */
34 return 64*1024*1024;
35}
36
37#define BCSR_PCMCIA_PC0DRVEN 0x0010
38#define BCSR_PCMCIA_PC0RST 0x0080
39
40/* In cpu/mips/cpu.c */
41void write_one_tlb( int index, u32 pagemask, u32 hi, u32 low0, u32 low1 );
42
43int checkboard (void)
44{
45 u16 status;
46 /* volatile u32 *pcmcia_bcsr = (u32*)(DB1000_BCSR_ADDR+0x10); */
47 volatile u32 *sys_counter = (volatile u32*)SYS_COUNTER_CNTRL;
48 u32 proc_id;
49
50 *sys_counter = 0x100; /* Enable 32 kHz oscillator for RTC/TOY */
51
52 proc_id = read_32bit_cp0_register(CP0_PRID);
53
54 switch (proc_id >> 24) {
55 case 0:
56 puts ("Board: Pb1000\n");
57 printf ("CPU: Au1000 396 MHz, id: 0x%02x, rev: 0x%02x\n",
58 (proc_id >> 8) & 0xFF, proc_id & 0xFF);
59 break;
60 case 1:
61 puts ("Board: Pb1500\n");
62 printf ("CPU: Au1500, id: 0x%02x, rev: 0x%02x\n",
63 (proc_id >> 8) & 0xFF, proc_id & 0xFF);
64 break;
65 case 2:
66 puts ("Board: Pb1100\n");
67 printf ("CPU: Au1100, id: 0x%02x, rev: 0x%02x\n",
68 (proc_id >> 8) & 0xFF, proc_id & 0xFF);
69 break;
70 default:
71 printf ("Unsupported cpu %d, proc_id=0x%x\n", proc_id >> 24, proc_id);
72 }
Jean-Christophe PLAGNIOL-VILLARD5c150102007-11-13 09:11:05 +010073
74 set_io_port_base(0);
75
Wolfgang Denk265817c2005-09-25 00:53:22 +020076#if defined(CONFIG_IDE_PCMCIA) && 0
77 /* Enable 3.3 V on slot 0 ( VCC )
78 No 5V */
79 status = 4;
80 *pcmcia_bcsr = status;
81
82 status |= BCSR_PCMCIA_PC0DRVEN;
83 *pcmcia_bcsr = status;
84 au_sync();
85
86 udelay(300*1000);
87
88 status |= BCSR_PCMCIA_PC0RST;
89 *pcmcia_bcsr = status;
90 au_sync();
91
92 udelay(100*1000);
93
94 /* PCMCIA is on a 36 bit physical address.
95 We need to map it into a 32 bit addresses */
96
97#if 0
98 /* We dont need theese unless we run whole pcmcia package */
99 write_one_tlb(20, /* index */
100 0x01ffe000, /* Pagemask, 16 MB pages */
101 CFG_PCMCIA_IO_BASE, /* Hi */
102 0x3C000017, /* Lo0 */
103 0x3C200017); /* Lo1 */
104
105 write_one_tlb(21, /* index */
106 0x01ffe000, /* Pagemask, 16 MB pages */
107 CFG_PCMCIA_ATTR_BASE, /* Hi */
108 0x3D000017, /* Lo0 */
109 0x3D200017); /* Lo1 */
110#endif /* 0 */
111 write_one_tlb(22, /* index */
112 0x01ffe000, /* Pagemask, 16 MB pages */
113 CFG_PCMCIA_MEM_ADDR, /* Hi */
114 0x3E000017, /* Lo0 */
115 0x3E200017); /* Lo1 */
116#endif /* CONFIG_IDE_PCMCIA */
117
118 return 0;
119}