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Albert Aribaud0c61e6f2010-06-17 19:36:07 +05301/*
Albert ARIBAUD57b4bce2011-04-22 19:41:02 +02002 * Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net>
Albert Aribaud0c61e6f2010-06-17 19:36:07 +05303 *
4 * Based on original Kirkwood support which is
5 * (C) Copyright 2009
6 * Marvell Semiconductor <www.marvell.com>
7 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
8 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02009 * SPDX-License-Identifier: GPL-2.0+
Albert Aribaud0c61e6f2010-06-17 19:36:07 +053010 */
11
12#include <common.h>
13#include <config.h>
Lei Wen5ff8b352011-10-24 16:27:32 +000014#include <asm/arch/cpu.h>
Albert Aribaud0c61e6f2010-06-17 19:36:07 +053015
16DECLARE_GLOBAL_DATA_PTR;
17
18/*
19 * orion5x_sdram_bar - reads SDRAM Base Address Register
20 */
21u32 orion5x_sdram_bar(enum memory_bank bank)
22{
23 struct orion5x_ddr_addr_decode_registers *winregs =
24 (struct orion5x_ddr_addr_decode_registers *)
Rogan Dawes286a5b22011-04-13 23:54:53 +053025 ORION5X_DRAM_BASE;
Albert Aribaud0c61e6f2010-06-17 19:36:07 +053026
27 u32 result = 0;
28 u32 enable = 0x01 & winregs[bank].size;
29
30 if ((!enable) || (bank > BANK3))
31 return 0;
32
33 result = winregs[bank].base;
34 return result;
35}
Heiko Schocherab86f722010-09-17 13:10:42 +020036int dram_init (void)
37{
38 /* dram_init must store complete ramsize in gd->ram_size */
39 gd->ram_size = get_ram_size(
Albert ARIBAUDa55d23c2011-07-03 05:55:33 +000040 (long *) orion5x_sdram_bar(0),
Heiko Schocherab86f722010-09-17 13:10:42 +020041 CONFIG_MAX_RAM_BANK_SIZE);
42 return 0;
43}
44
45void dram_init_banksize (void)
46{
47 int i;
48
49 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
50 gd->bd->bi_dram[i].start = orion5x_sdram_bar(i);
51 gd->bd->bi_dram[i].size = get_ram_size(
Albert ARIBAUDa55d23c2011-07-03 05:55:33 +000052 (long *) (gd->bd->bi_dram[i].start),
Heiko Schocherab86f722010-09-17 13:10:42 +020053 CONFIG_MAX_RAM_BANK_SIZE);
54 }
55}