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Tom Rini4549e782018-05-06 18:27:01 -04001// SPDX-License-Identifier: GPL-2.0+ OR X11
Haikun Wangd941f712015-06-26 19:48:36 +08002/*
Prabhakar Kushwaha44937212015-11-09 16:42:07 +05303 * Freescale ls2080a SOC common device tree source
Haikun Wangd941f712015-06-26 19:48:36 +08004 *
5 * Copyright 2013-2015 Freescale Semiconductor, Inc.
Haikun Wangd941f712015-06-26 19:48:36 +08006 */
7
8/ {
Prabhakar Kushwaha44937212015-11-09 16:42:07 +05309 compatible = "fsl,ls2080a";
Haikun Wangd941f712015-06-26 19:48:36 +080010 interrupt-parent = <&gic>;
11 #address-cells = <2>;
12 #size-cells = <2>;
13
Haikun Wangd941f712015-06-26 19:48:36 +080014 memory@80000000 {
15 device_type = "memory";
16 reg = <0x00000000 0x80000000 0 0x80000000>;
17 /* DRAM space - 1, size : 2 GB DRAM */
18 };
19
20 gic: interrupt-controller@6000000 {
21 compatible = "arm,gic-v3";
22 reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
23 <0x0 0x06100000 0 0x100000>; /* GICR (RD_base + SGI_base) */
24 #interrupt-cells = <3>;
25 interrupt-controller;
26 interrupts = <1 9 0x4>;
27 };
28
29 timer {
30 compatible = "arm,armv8-timer";
31 interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */
32 <1 14 0x8>, /* Physical Non-Secure PPI, active-low */
33 <1 11 0x8>, /* Virtual PPI, active-low */
34 <1 10 0x8>; /* Hypervisor PPI, active-low */
35 };
36
37 serial0: serial@21c0500 {
38 device_type = "serial";
39 compatible = "fsl,ns16550", "ns16550a";
40 reg = <0x0 0x21c0500 0x0 0x100>;
41 clock-frequency = <0>; /* Updated by bootloader */
42 interrupts = <0 32 0x1>; /* edge triggered */
43 };
44
45 serial1: serial@21c0600 {
46 device_type = "serial";
47 compatible = "fsl,ns16550", "ns16550a";
48 reg = <0x0 0x21c0600 0x0 0x100>;
49 clock-frequency = <0>; /* Updated by bootloader */
50 interrupts = <0 32 0x1>; /* edge triggered */
51 };
52
53 fsl_mc: fsl-mc@80c000000 {
54 compatible = "fsl,qoriq-mc";
55 reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */
56 <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
57 };
Haikun Wangfe69a0e2015-06-26 19:48:45 +080058
chuanhua han407916f2019-07-22 16:36:45 +080059 i2c0: i2c@2000000 {
60 status = "disabled";
61 compatible = "fsl,vf610-i2c";
62 #address-cells = <1>;
63 #size-cells = <0>;
64 reg = <0x0 0x2000000 0x0 0x10000>;
65 interrupts = <0 34 0x4>; /* Level high type */
66 };
67
68 i2c1: i2c@2010000 {
69 status = "disabled";
70 compatible = "fsl,vf610-i2c";
71 #address-cells = <1>;
72 #size-cells = <0>;
73 reg = <0x0 0x2010000 0x0 0x10000>;
74 interrupts = <0 34 0x4>; /* Level high type */
75 };
76
77 i2c2: i2c@2020000 {
78 status = "disabled";
79 compatible = "fsl,vf610-i2c";
80 #address-cells = <1>;
81 #size-cells = <0>;
82 reg = <0x0 0x2020000 0x0 0x10000>;
83 interrupts = <0 35 0x4>; /* Level high type */
84 };
85
86 i2c3: i2c@2030000 {
87 status = "disabled";
88 compatible = "fsl,vf610-i2c";
89 #address-cells = <1>;
90 #size-cells = <0>;
91 reg = <0x0 0x2030000 0x0 0x10000>;
92 interrupts = <0 35 0x4>; /* Level high type */
93 };
94
Haikun Wangfe69a0e2015-06-26 19:48:45 +080095 dspi: dspi@2100000 {
96 compatible = "fsl,vf610-dspi";
97 #address-cells = <1>;
98 #size-cells = <0>;
99 reg = <0x0 0x2100000 0x0 0x10000>;
100 interrupts = <0 26 0x4>; /* Level high type */
101 num-cs = <6>;
102 };
Yuan Yao95ab8512016-06-08 18:24:56 +0800103
104 qspi: quadspi@1550000 {
105 compatible = "fsl,vf610-qspi";
106 #address-cells = <1>;
107 #size-cells = <0>;
108 reg = <0x0 0x20c0000 0x0 0x10000>,
109 <0x0 0x20000000 0x0 0x10000000>;
110 reg-names = "QuadSPI", "QuadSPI-memory";
111 num-cs = <4>;
112 };
Sriram Dash68ec3882016-10-07 14:07:36 +0530113
Yinbo Zhu99e00712018-09-25 14:47:08 +0800114 esdhc: esdhc@0 {
115 compatible = "fsl,esdhc";
116 reg = <0x0 0x2140000 0x0 0x10000>;
117 interrupts = <0 28 0x4>; /* Level high type */
118 little-endian;
119 bus-width = <4>;
120 };
121
Sriram Dash68ec3882016-10-07 14:07:36 +0530122 usb0: usb3@3100000 {
123 compatible = "fsl,layerscape-dwc3";
124 reg = <0x0 0x3100000 0x0 0x10000>;
125 interrupts = <0 80 0x4>; /* Level high type */
126 dr_mode = "host";
127 };
128
129 usb1: usb3@3110000 {
130 compatible = "fsl,layerscape-dwc3";
131 reg = <0x0 0x3110000 0x0 0x10000>;
132 interrupts = <0 81 0x4>; /* Level high type */
133 dr_mode = "host";
134 };
Minghuan Lian33f61e02016-12-13 14:54:15 +0800135
136 pcie@3400000 {
137 compatible = "fsl,ls-pcie", "snps,dw-pcie";
138 reg = <0x00 0x03400000 0x0 0x80000 /* dbi registers */
139 0x00 0x03480000 0x0 0x80000 /* lut registers */
140 0x10 0x00000000 0x0 0x20000>; /* configuration space */
141 reg-names = "dbi", "lut", "config";
142 #address-cells = <3>;
143 #size-cells = <2>;
144 device_type = "pci";
145 num-lanes = <4>;
146 bus-range = <0x0 0xff>;
147 ranges = <0x81000000 0x0 0x00000000 0x10 0x00020000 0x0 0x00010000 /* downstream I/O */
148 0x82000000 0x0 0x40000000 0x10 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
149 };
150
151 pcie@3500000 {
152 compatible = "fsl,ls-pcie", "snps,dw-pcie";
153 reg = <0x00 0x03500000 0x0 0x80000 /* dbi registers */
154 0x00 0x03580000 0x0 0x80000 /* lut registers */
155 0x12 0x00000000 0x0 0x20000>; /* configuration space */
156 reg-names = "dbi", "lut", "config";
157 #address-cells = <3>;
158 #size-cells = <2>;
159 device_type = "pci";
160 num-lanes = <4>;
161 bus-range = <0x0 0xff>;
162 ranges = <0x81000000 0x0 0x00000000 0x12 0x00020000 0x0 0x00010000 /* downstream I/O */
163 0x82000000 0x0 0x40000000 0x12 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
164 };
165
166 pcie@3600000 {
167 compatible = "fsl,ls-pcie", "snps,dw-pcie";
168 reg = <0x00 0x03600000 0x0 0x80000 /* dbi registers */
169 0x00 0x03680000 0x0 0x80000 /* lut registers */
170 0x14 0x00000000 0x0 0x20000>; /* configuration space */
171 reg-names = "dbi", "lut", "config";
172 #address-cells = <3>;
173 #size-cells = <2>;
174 device_type = "pci";
175 num-lanes = <8>;
176 bus-range = <0x0 0xff>;
177 ranges = <0x81000000 0x0 0x00000000 0x14 0x00020000 0x0 0x00010000 /* downstream I/O */
178 0x82000000 0x0 0x40000000 0x14 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
179 };
180
181 pcie@3700000 {
182 compatible = "fsl,ls-pcie", "snps,dw-pcie";
183 reg = <0x00 0x03700000 0x0 0x80000 /* dbi registers */
184 0x00 0x03780000 0x0 0x80000 /* lut registers */
185 0x16 0x00000000 0x0 0x20000>; /* configuration space */
186 reg-names = "dbi", "lut", "config";
187 #address-cells = <3>;
188 #size-cells = <2>;
189 device_type = "pci";
190 num-lanes = <4>;
191 bus-range = <0x0 0xff>;
192 ranges = <0x81000000 0x0 0x00000000 0x16 0x00020000 0x0 0x00010000 /* downstream I/O */
193 0x82000000 0x0 0x40000000 0x16 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
194 };
Peng Ma8ec42852018-10-22 10:43:21 +0800195
196 sata: sata@3200000 {
197 compatible = "fsl,ls2080a-ahci";
198 reg = <0x0 0x3200000 0x0 0x10000>;
199 interrupts = <0 133 0x4>; /* Level high type */
200 status = "disabled";
201 };
202
Haikun Wangd941f712015-06-26 19:48:36 +0800203};