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wdenk935ecca2002-08-06 20:46:37 +00001#ifndef _440_i2c_h_
2#define _440_i2c_h_
3
Stefan Roese846b0dd2005-08-08 12:42:22 +02004#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
Stefan Roesec157d8e2005-08-01 16:41:48 +02005#define I2C_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x00000700)
6#else
wdenk935ecca2002-08-06 20:46:37 +00007#define I2C_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x00000400)
Stefan Roese846b0dd2005-08-08 12:42:22 +02008#endif /*CONFIG_440EP CONFIG_440GR*/
wdenk935ecca2002-08-06 20:46:37 +00009
10#define I2C_REGISTERS_BASE_ADDRESS I2C_BASE_ADDR
11#define IIC_MDBUF (I2C_REGISTERS_BASE_ADDRESS+IICMDBUF)
12#define IIC_SDBUF (I2C_REGISTERS_BASE_ADDRESS+IICSDBUF)
13#define IIC_LMADR (I2C_REGISTERS_BASE_ADDRESS+IICLMADR)
14#define IIC_HMADR (I2C_REGISTERS_BASE_ADDRESS+IICHMADR)
15#define IIC_CNTL (I2C_REGISTERS_BASE_ADDRESS+IICCNTL)
16#define IIC_MDCNTL (I2C_REGISTERS_BASE_ADDRESS+IICMDCNTL)
17#define IIC_STS (I2C_REGISTERS_BASE_ADDRESS+IICSTS)
18#define IIC_EXTSTS (I2C_REGISTERS_BASE_ADDRESS+IICEXTSTS)
19#define IIC_LSADR (I2C_REGISTERS_BASE_ADDRESS+IICLSADR)
20#define IIC_HSADR (I2C_REGISTERS_BASE_ADDRESS+IICHSADR)
21#define IIC_CLKDIV (I2C_REGISTERS_BASE_ADDRESS+IICCLKDIV)
22#define IIC_INTRMSK (I2C_REGISTERS_BASE_ADDRESS+IICINTRMSK)
23#define IIC_XFRCNT (I2C_REGISTERS_BASE_ADDRESS+IICXFRCNT)
24#define IIC_XTCNTLSS (I2C_REGISTERS_BASE_ADDRESS+IICXTCNTLSS)
25#define IIC_DIRECTCNTL (I2C_REGISTERS_BASE_ADDRESS+IICDIRECTCNTL)
26
27/* MDCNTL Register Bit definition */
28#define IIC_MDCNTL_HSCL 0x01
29#define IIC_MDCNTL_EUBS 0x02
30#define IIC_MDCNTL_EINT 0x04
31#define IIC_MDCNTL_ESM 0x08
32#define IIC_MDCNTL_FSM 0x10
33#define IIC_MDCNTL_EGC 0x20
34#define IIC_MDCNTL_FMDB 0x40
35#define IIC_MDCNTL_FSDB 0x80
36
37/* CNTL Register Bit definition */
38#define IIC_CNTL_PT 0x01
39#define IIC_CNTL_READ 0x02
40#define IIC_CNTL_CHT 0x04
41#define IIC_CNTL_RPST 0x08
42/* bit 2/3 for Transfer count*/
43#define IIC_CNTL_AMD 0x40
44#define IIC_CNTL_HMT 0x80
45
46/* STS Register Bit definition */
47#define IIC_STS_PT 0X01
48#define IIC_STS_IRQA 0x02
49#define IIC_STS_ERR 0X04
50#define IIC_STS_SCMP 0x08
51#define IIC_STS_MDBF 0x10
52#define IIC_STS_MDBS 0X20
53#define IIC_STS_SLPR 0x40
54#define IIC_STS_SSS 0x80
55
56/* EXTSTS Register Bit definition */
57#define IIC_EXTSTS_XFRA 0X01
58#define IIC_EXTSTS_ICT 0X02
59#define IIC_EXTSTS_LA 0X04
60
61/* XTCNTLSS Register Bit definition */
62#define IIC_XTCNTLSS_SRST 0x01
63#define IIC_XTCNTLSS_EPI 0x02
64#define IIC_XTCNTLSS_SDBF 0x04
65#define IIC_XTCNTLSS_SBDD 0x08
66#define IIC_XTCNTLSS_SWS 0x10
67#define IIC_XTCNTLSS_SWC 0x20
68#define IIC_XTCNTLSS_SRS 0x40
69#define IIC_XTCNTLSS_SRC 0x80
70#endif