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Tom Rini83d290c2018-05-06 17:58:06 -04001# SPDX-License-Identifier: GPL-2.0+
Walter Schweizera0a868b2016-10-06 23:29:56 +02002#
3# (C) Copyright 2011
4# Jason Cooper <u-boot@lakedaemon.net>
5#
6# Based on work by:
7# Marvell Semiconductor <www.marvell.com>
8# Written-by: Siddarth Gore <gores@marvell.com>
Walter Schweizera0a868b2016-10-06 23:29:56 +02009# Refer doc/README.kwbimage for more details about how-to configure
10# and create kirkwood boot image
11#
12
13# Boot Media configurations
14BOOT_FROM spi
15
16# SOC registers configuration using bootrom header extension
17# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
18
19# Configure RGMII-0/1 interface pad voltage to 1.8V
Walter Schweizer9c658d82016-10-06 23:29:58 +020020DATA 0xFFD100e0 0x1b1b1b9b
21
22DATA 0xFFD20134 0xbbbbbbbb
23DATA 0xFFD20138 0x00bbbbbb
Walter Schweizera0a868b2016-10-06 23:29:56 +020024
25#Dram initalization for SINGLE x16 CL=5 @ 400MHz
26DATA 0xFFD01400 0x43000c30 # DDR Configuration register
27# bit13-0: 0xc30 (3120 DDR2 clks refresh rate)
28# bit23-14: zero
29# bit24: 1= enable exit self refresh mode on DDR access
30# bit25: 1 required
31# bit29-26: zero
32# bit31-30: 01
33
Walter Schweizer9c658d82016-10-06 23:29:58 +020034DATA 0xFFD01404 0x39543000 # DDR Controller Control Low
Walter Schweizera0a868b2016-10-06 23:29:56 +020035# bit 4: 0=addr/cmd in smame cycle
36# bit 5: 0=clk is driven during self refresh, we don't care for APX
37# bit 6: 0=use recommended falling edge of clk for addr/cmd
38# bit14: 0=input buffer always powered up
39# bit18: 1=cpu lock transaction enabled
40# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
41# bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
42# bit30-28: 3 required
43# bit31: 0=no additional STARTBURST delay
44
45DATA 0xFFD01408 0x22125451 # DDR Timing (Low) (active cycles value +1)
46# bit3-0: TRAS lsbs
47# bit7-4: TRCD
48# bit11- 8: TRP
49# bit15-12: TWR
50# bit19-16: TWTR
51# bit20: TRAS msb
52# bit23-21: 0x0
53# bit27-24: TRRD
54# bit31-28: TRTP
55
Walter Schweizer9c658d82016-10-06 23:29:58 +020056DATA 0xFFD0140C 0x00000833 # DDR Timing (High)
Walter Schweizera0a868b2016-10-06 23:29:56 +020057# bit6-0: TRFC
58# bit8-7: TR2R
59# bit10-9: TR2W
60# bit12-11: TW2W
61# bit31-13: zero required
62
Walter Schweizer9c658d82016-10-06 23:29:58 +020063DATA 0xFFD01410 0x0000000d # DDR Address Control
Walter Schweizera0a868b2016-10-06 23:29:56 +020064# bit1-0: 01, Cs0width=x8
65# bit3-2: 10, Cs0size=1Gb
66# bit5-4: 01, Cs1width=x8
67# bit7-6: 10, Cs1size=1Gb
68# bit9-8: 00, Cs2width=nonexistent
69# bit11-10: 00, Cs2size =nonexistent
70# bit13-12: 00, Cs3width=nonexistent
71# bit15-14: 00, Cs3size =nonexistent
72# bit16: 0, Cs0AddrSel
73# bit17: 0, Cs1AddrSel
74# bit18: 0, Cs2AddrSel
75# bit19: 0, Cs3AddrSel
76# bit31-20: 0 required
77
78DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
79# bit0: 0, OpenPage enabled
80# bit31-1: 0 required
81
82DATA 0xFFD01418 0x00000000 # DDR Operation
83# bit3-0: 0x0, DDR cmd
84# bit31-4: 0 required
85
86DATA 0xFFD0141C 0x00000C52 # DDR Mode
87# bit2-0: 2, BurstLen=2 required
88# bit3: 0, BurstType=0 required
89# bit6-4: 4, CL=5
90# bit7: 0, TestMode=0 normal
91# bit8: 0, DLL reset=0 normal
92# bit11-9: 6, auto-precharge write recovery ????????????
93# bit12: 0, PD must be zero
94# bit31-13: 0 required
95
Walter Schweizer9c658d82016-10-06 23:29:58 +020096DATA 0xFFD01420 0x00000042 # DDR Extended Mode
Walter Schweizera0a868b2016-10-06 23:29:56 +020097# bit0: 0, DDR DLL enabled
98# bit1: 0, DDR drive strenght normal
99# bit2: 0, DDR ODT control lsd (disabled)
100# bit5-3: 000, required
101# bit6: 1, DDR ODT control msb, (disabled)
102# bit9-7: 000, required
103# bit10: 0, differential DQS enabled
104# bit11: 0, required
105# bit12: 0, DDR output buffer enabled
106# bit31-13: 0 required
107
Walter Schweizer9c658d82016-10-06 23:29:58 +0200108DATA 0xFFD01424 0x0000F1FF # DDR Controller Control High
Walter Schweizera0a868b2016-10-06 23:29:56 +0200109# bit2-0: 111, required
110# bit3 : 1 , MBUS Burst Chop disabled
111# bit6-4: 111, required
112# bit7 : 0
113# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz
114# bit9 : 0 , no half clock cycle addition to dataout
115# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
116# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
117# bit15-12: 1111 required
118# bit31-16: 0 required
119
120DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values)
121DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values)
122
123DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0
Walter Schweizer9c658d82016-10-06 23:29:58 +0200124DATA 0xFFD01504 0x07FFFFF1 # CS[0]n Size
Walter Schweizera0a868b2016-10-06 23:29:56 +0200125# bit0: 1, Window enabled
126# bit1: 0, Write Protect disabled
127# bit3-2: 00, CS0 hit selected
128# bit23-4: ones, required
Walter Schweizer9c658d82016-10-06 23:29:58 +0200129# bit31-24: 0x07, Size (i.e. 128MB)
Walter Schweizera0a868b2016-10-06 23:29:56 +0200130
131DATA 0xFFD01508 0x10000000 # CS[1]n Base address to 256Mb
Walter Schweizer9c658d82016-10-06 23:29:58 +0200132DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled
Walter Schweizera0a868b2016-10-06 23:29:56 +0200133
Walter Schweizer9c658d82016-10-06 23:29:58 +0200134DATA 0xFFD01510 0x20000000 # CS[2]n Base address to 256Mb
Walter Schweizera0a868b2016-10-06 23:29:56 +0200135DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
Walter Schweizer9c658d82016-10-06 23:29:58 +0200136DATA 0xFFD01518 0x30000000 # CS[3]n Base address to 256Mb
Walter Schweizera0a868b2016-10-06 23:29:56 +0200137DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
138
Walter Schweizer9c658d82016-10-06 23:29:58 +0200139DATA 0xFFD01494 0x003C0000 # DDR ODT Control (Low)
Walter Schweizera0a868b2016-10-06 23:29:56 +0200140DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
141# bit1-0: 00, ODT0 controlled by ODT Control (low) register above
142# bit3-2: 01, ODT1 active NEVER!
143# bit31-4: zero, required
144
Walter Schweizer9c658d82016-10-06 23:29:58 +0200145DATA 0xFFD0149C 0x0000F80F # CPU ODT Control
Walter Schweizera0a868b2016-10-06 23:29:56 +0200146DATA 0xFFD01480 0x00000001 # DDR Initialization Control
147#bit0=1, enable DDR init upon this register write
148
149# End of Header extension
150DATA 0x0 0x0