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Dave Liu8bd522c2008-01-11 18:48:24 +08001/*
Scott Woode8d3ca82010-08-30 18:04:52 -05002 * Copyright (C) 2007-2010 Freescale Semiconductor, Inc.
Dave Liu8bd522c2008-01-11 18:48:24 +08003 *
4 * Dave Liu <daveliu@freescale.com>
5 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02006 * SPDX-License-Identifier: GPL-2.0+
Dave Liu8bd522c2008-01-11 18:48:24 +08007 */
8
9#ifndef __CONFIG_H
10#define __CONFIG_H
11
Scott Woodf1c574d2010-11-24 13:28:40 +000012#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10)
13#define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000
14#define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
15#define CONFIG_SYS_NAND_U_BOOT_OFFS 16384
16#define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
17
Wolfgang Denk2ae18242010-10-06 09:05:45 +020018#ifndef CONFIG_SYS_TEXT_BASE
19#define CONFIG_SYS_TEXT_BASE 0xFE000000
Anton Vorontsov2e950042009-11-24 20:12:12 +030020#endif
21
Scott Woodf1c574d2010-11-24 13:28:40 +000022#ifndef CONFIG_SYS_MONITOR_BASE
23#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
24#endif
25
Dave Liu8bd522c2008-01-11 18:48:24 +080026/*
27 * High Level Configuration Options
28 */
29#define CONFIG_E300 1 /* E300 family */
Peter Tyser2c7920a2009-05-22 17:23:25 -050030#define CONFIG_MPC831x 1 /* MPC831x CPU family */
Dave Liu8bd522c2008-01-11 18:48:24 +080031#define CONFIG_MPC8315 1 /* MPC8315 CPU specific */
32#define CONFIG_MPC8315ERDB 1 /* MPC8315ERDB board specific */
33
34/*
35 * System Clock Setup
36 */
37#define CONFIG_83XX_CLKIN 66666667 /* in Hz */
38#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
39
40/*
41 * Hardware Reset Configuration Word
42 * if CLKIN is 66.66MHz, then
43 * CSB = 133MHz, CORE = 400MHz, DDRC = 266MHz, LBC = 133MHz
44 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020045#define CONFIG_SYS_HRCW_LOW (\
Dave Liu8bd522c2008-01-11 18:48:24 +080046 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
47 HRCWL_DDR_TO_SCB_CLK_2X1 |\
48 HRCWL_SVCOD_DIV_2 |\
49 HRCWL_CSB_TO_CLKIN_2X1 |\
50 HRCWL_CORE_TO_CSB_3X1)
Anton Vorontsov2e950042009-11-24 20:12:12 +030051#define CONFIG_SYS_HRCW_HIGH_BASE (\
Dave Liu8bd522c2008-01-11 18:48:24 +080052 HRCWH_PCI_HOST |\
53 HRCWH_PCI1_ARBITER_ENABLE |\
54 HRCWH_CORE_ENABLE |\
Dave Liu8bd522c2008-01-11 18:48:24 +080055 HRCWH_BOOTSEQ_DISABLE |\
56 HRCWH_SW_WATCHDOG_DISABLE |\
Dave Liu8bd522c2008-01-11 18:48:24 +080057 HRCWH_TSEC1M_IN_RGMII |\
58 HRCWH_TSEC2M_IN_RGMII |\
59 HRCWH_BIG_ENDIAN |\
60 HRCWH_LALE_NORMAL)
61
Anton Vorontsov2e950042009-11-24 20:12:12 +030062#ifdef CONFIG_NAND_SPL
63#define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\
64 HRCWH_FROM_0XFFF00100 |\
65 HRCWH_ROM_LOC_NAND_SP_8BIT |\
66 HRCWH_RL_EXT_NAND)
67#else
68#define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\
69 HRCWH_FROM_0X00000100 |\
70 HRCWH_ROM_LOC_LOCAL_16BIT |\
71 HRCWH_RL_EXT_LEGACY)
72#endif
73
Dave Liu8bd522c2008-01-11 18:48:24 +080074/*
75 * System IO Config
76 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020077#define CONFIG_SYS_SICRH 0x00000000
78#define CONFIG_SYS_SICRL 0x00000000 /* 3.3V, no delay */
Dave Liu8bd522c2008-01-11 18:48:24 +080079
Anton Vorontsovb8b71ff2009-06-10 00:25:36 +040080#define CONFIG_HWCONFIG
Dave Liu8bd522c2008-01-11 18:48:24 +080081
82/*
83 * IMMR new address
84 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020085#define CONFIG_SYS_IMMR 0xE0000000
Dave Liu8bd522c2008-01-11 18:48:24 +080086
87/*
88 * Arbiter Setup
89 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020090#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */
Joe Hershberger6f681b72011-10-11 23:57:11 -050091#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */
92#define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */
Dave Liu8bd522c2008-01-11 18:48:24 +080093
94/*
95 * DDR Setup
96 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020097#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
98#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
99#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
100#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
Joe Hershberger6f681b72011-10-11 23:57:11 -0500101#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
Dave Liu8bd522c2008-01-11 18:48:24 +0800102 | DDRCDR_PZ_LOZ \
103 | DDRCDR_NZ_LOZ \
104 | DDRCDR_ODT \
Joe Hershberger6f681b72011-10-11 23:57:11 -0500105 | DDRCDR_Q_DRN)
Dave Liu8bd522c2008-01-11 18:48:24 +0800106 /* 0x7b880001 */
107/*
108 * Manually set up DDR parameters
109 * consist of two chips HY5PS12621BFP-C4 from HYNIX
110 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200111#define CONFIG_SYS_DDR_SIZE 128 /* MB */
112#define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
Joe Hershberger6f681b72011-10-11 23:57:11 -0500113#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
Joe Hershberger2fef4022011-10-11 23:57:29 -0500114 | CSCONFIG_ODT_RD_NEVER \
115 | CSCONFIG_ODT_WR_ONLY_CURRENT \
Joe Hershberger6f681b72011-10-11 23:57:11 -0500116 | CSCONFIG_ROW_BIT_13 \
117 | CSCONFIG_COL_BIT_10)
Dave Liu8bd522c2008-01-11 18:48:24 +0800118 /* 0x80010102 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200119#define CONFIG_SYS_DDR_TIMING_3 0x00000000
Joe Hershberger6f681b72011-10-11 23:57:11 -0500120#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
121 | (0 << TIMING_CFG0_WRT_SHIFT) \
122 | (0 << TIMING_CFG0_RRT_SHIFT) \
123 | (0 << TIMING_CFG0_WWT_SHIFT) \
124 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
125 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
126 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
127 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
Dave Liu8bd522c2008-01-11 18:48:24 +0800128 /* 0x00220802 */
Joe Hershberger6f681b72011-10-11 23:57:11 -0500129#define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
130 | (7 << TIMING_CFG1_ACTTOPRE_SHIFT) \
131 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
132 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
133 | (6 << TIMING_CFG1_REFREC_SHIFT) \
134 | (2 << TIMING_CFG1_WRREC_SHIFT) \
135 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
136 | (2 << TIMING_CFG1_WRTORD_SHIFT))
Howard Gregory2f2a5c32008-11-04 14:55:33 +0800137 /* 0x27256222 */
Joe Hershberger6f681b72011-10-11 23:57:11 -0500138#define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
139 | (4 << TIMING_CFG2_CPO_SHIFT) \
140 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
141 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
142 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
143 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
144 | (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
Howard Gregory2f2a5c32008-11-04 14:55:33 +0800145 /* 0x121048c5 */
Joe Hershberger6f681b72011-10-11 23:57:11 -0500146#define CONFIG_SYS_DDR_INTERVAL ((0x0360 << SDRAM_INTERVAL_REFINT_SHIFT) \
147 | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
Dave Liu8bd522c2008-01-11 18:48:24 +0800148 /* 0x03600100 */
Joe Hershberger6f681b72011-10-11 23:57:11 -0500149#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
Dave Liu8bd522c2008-01-11 18:48:24 +0800150 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
Joe Hershberger2fef4022011-10-11 23:57:29 -0500151 | SDRAM_CFG_DBW_32)
Dave Liu8bd522c2008-01-11 18:48:24 +0800152 /* 0x43080000 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200153#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */
Joe Hershberger6f681b72011-10-11 23:57:11 -0500154#define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) \
155 | (0x0232 << SDRAM_MODE_SD_SHIFT))
Dave Liu8bd522c2008-01-11 18:48:24 +0800156 /* ODT 150ohm CL=3, AL=1 on SDRAM */
Joe Hershberger6f681b72011-10-11 23:57:11 -0500157#define CONFIG_SYS_DDR_MODE2 0x00000000
Dave Liu8bd522c2008-01-11 18:48:24 +0800158
159/*
160 * Memory test
161 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200162#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
163#define CONFIG_SYS_MEMTEST_START 0x00040000 /* memtest region */
164#define CONFIG_SYS_MEMTEST_END 0x00140000
Dave Liu8bd522c2008-01-11 18:48:24 +0800165
166/*
167 * The reserved memory
168 */
Kevin Hao16c8c172016-07-08 11:25:14 +0800169#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
Joe Hershberger6f681b72011-10-11 23:57:11 -0500170#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
Dave Liu8bd522c2008-01-11 18:48:24 +0800171
172/*
173 * Initial RAM Base Address Setup
174 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200175#define CONFIG_SYS_INIT_RAM_LOCK 1
176#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200177#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
Joe Hershberger6f681b72011-10-11 23:57:11 -0500178#define CONFIG_SYS_GBL_DATA_OFFSET \
179 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Dave Liu8bd522c2008-01-11 18:48:24 +0800180
181/*
182 * Local Bus Configuration & Clock Setup
183 */
Kim Phillipsc7190f02009-09-25 18:19:44 -0500184#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
185#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200186#define CONFIG_SYS_LBC_LBCR 0x00040000
Becky Bruce0914f482010-06-17 11:37:18 -0500187#define CONFIG_FSL_ELBC 1
Dave Liu8bd522c2008-01-11 18:48:24 +0800188
189/*
190 * FLASH on the Local Bus
191 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200192#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200193#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200194#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
Dave Liu8bd522c2008-01-11 18:48:24 +0800195
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200196#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
Joe Hershberger6f681b72011-10-11 23:57:11 -0500197#define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is 8M */
198#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
Dave Liu8bd522c2008-01-11 18:48:24 +0800199
Joe Hershberger6f681b72011-10-11 23:57:11 -0500200 /* Window base at flash base */
201#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500202#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB)
Dave Liu8bd522c2008-01-11 18:48:24 +0800203
Anton Vorontsov2e950042009-11-24 20:12:12 +0300204#define CONFIG_SYS_NOR_BR_PRELIM (CONFIG_SYS_FLASH_BASE \
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500205 | BR_PS_16 /* 16 bit port */ \
206 | BR_MS_GPCM /* MSEL = GPCM */ \
207 | BR_V) /* valid */
208#define CONFIG_SYS_NOR_OR_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
209 | OR_UPM_XAM \
210 | OR_GPCM_CSNT \
211 | OR_GPCM_ACS_DIV2 \
212 | OR_GPCM_XACS \
213 | OR_GPCM_SCY_15 \
214 | OR_GPCM_TRLX_SET \
215 | OR_GPCM_EHTR_SET \
216 | OR_GPCM_EAD)
Dave Liu8bd522c2008-01-11 18:48:24 +0800217
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200218#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
Joe Hershberger6f681b72011-10-11 23:57:11 -0500219/* 127 64KB sectors and 8 8KB top sectors per device */
220#define CONFIG_SYS_MAX_FLASH_SECT 135
Dave Liu8bd522c2008-01-11 18:48:24 +0800221
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200222#undef CONFIG_SYS_FLASH_CHECKSUM
223#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
224#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
Dave Liu8bd522c2008-01-11 18:48:24 +0800225
226/*
227 * NAND Flash on the Local Bus
228 */
Anton Vorontsov2e950042009-11-24 20:12:12 +0300229
230#ifdef CONFIG_NAND_SPL
231#define CONFIG_SYS_NAND_BASE 0xFFF00000
232#else
233#define CONFIG_SYS_NAND_BASE 0xE0600000
234#endif
235
Scott Woode8d3ca82010-08-30 18:04:52 -0500236#define CONFIG_MTD_DEVICE
237#define CONFIG_MTD_PARTITION
238#define CONFIG_CMD_MTDPARTS
239#define MTDIDS_DEFAULT "nand0=e0600000.flash"
Joe Hershberger6f681b72011-10-11 23:57:11 -0500240#define MTDPARTS_DEFAULT \
Kevin Hao63865272016-07-08 11:25:15 +0800241 "mtdparts=e0600000.flash:512k(uboot),128k(env),6m@1m(kernel),-(fs)"
Scott Woode8d3ca82010-08-30 18:04:52 -0500242
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200243#define CONFIG_SYS_MAX_NAND_DEVICE 1
Dave Liu1ac57442008-11-04 14:55:06 +0800244#define CONFIG_CMD_NAND 1
245#define CONFIG_NAND_FSL_ELBC 1
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500246#define CONFIG_SYS_NAND_BLOCK_SIZE 16384
247#define CONFIG_SYS_NAND_WINDOW_SIZE (32 * 1024) /* 0x00008000 */
Dave Liu8bd522c2008-01-11 18:48:24 +0800248
Anton Vorontsov2e950042009-11-24 20:12:12 +0300249#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10)
250#define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000
251#define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
252#define CONFIG_SYS_NAND_U_BOOT_OFFS 16384
253#define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
254
255#define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE \
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500256 | BR_DECC_CHK_GEN /* Use HW ECC */ \
Joe Hershberger6f681b72011-10-11 23:57:11 -0500257 | BR_PS_8 /* 8 bit port */ \
Dave Liu8bd522c2008-01-11 18:48:24 +0800258 | BR_MS_FCM /* MSEL = FCM */ \
Joe Hershberger6f681b72011-10-11 23:57:11 -0500259 | BR_V) /* valid */
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500260#define CONFIG_SYS_NAND_OR_PRELIM \
261 (P2SZ_TO_AM(CONFIG_SYS_NAND_WINDOW_SIZE) \
Dave Liu8bd522c2008-01-11 18:48:24 +0800262 | OR_FCM_CSCT \
263 | OR_FCM_CST \
264 | OR_FCM_CHT \
265 | OR_FCM_SCY_1 \
266 | OR_FCM_TRLX \
Joe Hershberger6f681b72011-10-11 23:57:11 -0500267 | OR_FCM_EHTR)
Dave Liu8bd522c2008-01-11 18:48:24 +0800268 /* 0xFFFF8396 */
269
Anton Vorontsov2e950042009-11-24 20:12:12 +0300270#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM
271#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM
272#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM
273#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM
Anton Vorontsov2e950042009-11-24 20:12:12 +0300274
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200275#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500276#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
Dave Liu8bd522c2008-01-11 18:48:24 +0800277
Anton Vorontsov2e950042009-11-24 20:12:12 +0300278#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM
279#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM
280
281#if CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE && \
282 !defined(CONFIG_NAND_SPL)
283#define CONFIG_SYS_RAMBOOT
284#else
285#undef CONFIG_SYS_RAMBOOT
286#endif
287
Dave Liu8bd522c2008-01-11 18:48:24 +0800288/*
289 * Serial Port
290 */
291#define CONFIG_CONS_INDEX 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200292#define CONFIG_SYS_NS16550_SERIAL
293#define CONFIG_SYS_NS16550_REG_SIZE 1
Anton Vorontsov2e950042009-11-24 20:12:12 +0300294#define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 2)
Dave Liu8bd522c2008-01-11 18:48:24 +0800295
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200296#define CONFIG_SYS_BAUDRATE_TABLE \
Joe Hershberger6f681b72011-10-11 23:57:11 -0500297 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
Dave Liu8bd522c2008-01-11 18:48:24 +0800298
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200299#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
300#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
Dave Liu8bd522c2008-01-11 18:48:24 +0800301
Dave Liu8bd522c2008-01-11 18:48:24 +0800302/* I2C */
Heiko Schocher00f792e2012-10-24 13:48:22 +0200303#define CONFIG_SYS_I2C
304#define CONFIG_SYS_I2C_FSL
305#define CONFIG_SYS_FSL_I2C_SPEED 400000
306#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
307#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
308#define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} }
Dave Liu8bd522c2008-01-11 18:48:24 +0800309
310/*
311 * Board info - revision and where boot from
312 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200313#define CONFIG_SYS_I2C_PCF8574A_ADDR 0x39
Dave Liu8bd522c2008-01-11 18:48:24 +0800314
315/*
316 * Config on-board RTC
317 */
318#define CONFIG_RTC_DS1337 /* ds1339 on board, use ds1337 rtc via i2c */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200319#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
Dave Liu8bd522c2008-01-11 18:48:24 +0800320
321/*
322 * General PCI
323 * Addresses are mapped 1-1.
324 */
Joe Hershberger6f681b72011-10-11 23:57:11 -0500325#define CONFIG_SYS_PCI_MEM_BASE 0x80000000
326#define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE
327#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200328#define CONFIG_SYS_PCI_MMIO_BASE 0x90000000
329#define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE
330#define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */
331#define CONFIG_SYS_PCI_IO_BASE 0x00000000
332#define CONFIG_SYS_PCI_IO_PHYS 0xE0300000
333#define CONFIG_SYS_PCI_IO_SIZE 0x100000 /* 1M */
Dave Liu8bd522c2008-01-11 18:48:24 +0800334
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200335#define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE
336#define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000
337#define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000
Dave Liu8bd522c2008-01-11 18:48:24 +0800338
Anton Vorontsov8f11e342009-01-08 04:26:17 +0300339#define CONFIG_SYS_PCIE1_BASE 0xA0000000
340#define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000
341#define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000
342#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
343#define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000
344#define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000
345#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
346#define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000
347#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000
348
349#define CONFIG_SYS_PCIE2_BASE 0xC0000000
350#define CONFIG_SYS_PCIE2_MEM_BASE 0xC0000000
351#define CONFIG_SYS_PCIE2_MEM_PHYS 0xC0000000
352#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000
353#define CONFIG_SYS_PCIE2_CFG_BASE 0xD0000000
354#define CONFIG_SYS_PCIE2_CFG_SIZE 0x01000000
355#define CONFIG_SYS_PCIE2_IO_BASE 0x00000000
356#define CONFIG_SYS_PCIE2_IO_PHYS 0xD1000000
357#define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000
358
Gabor Juhos842033e2013-05-30 07:06:12 +0000359#define CONFIG_PCI_INDIRECT_BRIDGE
Kim Phillipsbe9b56d2009-07-23 14:09:38 -0500360#define CONFIG_PCIE
Dave Liu8bd522c2008-01-11 18:48:24 +0800361
Dave Liu8bd522c2008-01-11 18:48:24 +0800362#define CONFIG_EEPRO100
363#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200364#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
Dave Liu8bd522c2008-01-11 18:48:24 +0800365
Anton Vorontsov25f5f0d2008-07-08 21:00:04 +0400366#define CONFIG_HAS_FSL_DR_USB
Vivek Mahajan6823e9b2009-05-25 17:23:17 +0530367#define CONFIG_SYS_SCCR_USBDRCM 3
368
Vivek Mahajan6823e9b2009-05-25 17:23:17 +0530369#define CONFIG_USB_EHCI
370#define CONFIG_USB_EHCI_FSL
Joe Hershberger6f681b72011-10-11 23:57:11 -0500371#define CONFIG_USB_PHY_TYPE "utmi"
Vivek Mahajan6823e9b2009-05-25 17:23:17 +0530372#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
Anton Vorontsov25f5f0d2008-07-08 21:00:04 +0400373
Dave Liu8bd522c2008-01-11 18:48:24 +0800374/*
375 * TSEC
376 */
377#define CONFIG_TSEC_ENET /* TSEC ethernet support */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200378#define CONFIG_SYS_TSEC1_OFFSET 0x24000
Joe Hershberger6f681b72011-10-11 23:57:11 -0500379#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200380#define CONFIG_SYS_TSEC2_OFFSET 0x25000
Joe Hershberger6f681b72011-10-11 23:57:11 -0500381#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
Dave Liu8bd522c2008-01-11 18:48:24 +0800382
383/*
384 * TSEC ethernet configuration
385 */
386#define CONFIG_MII 1 /* MII PHY management */
387#define CONFIG_TSEC1 1
388#define CONFIG_TSEC1_NAME "eTSEC0"
389#define CONFIG_TSEC2 1
390#define CONFIG_TSEC2_NAME "eTSEC1"
391#define TSEC1_PHY_ADDR 0
392#define TSEC2_PHY_ADDR 1
393#define TSEC1_PHYIDX 0
394#define TSEC2_PHYIDX 0
395#define TSEC1_FLAGS TSEC_GIGABIT
396#define TSEC2_FLAGS TSEC_GIGABIT
397
398/* Options are: eTSEC[0-1] */
399#define CONFIG_ETHPRIME "eTSEC1"
400
401/*
Kim Phillips730e7922008-03-28 14:31:23 -0500402 * SATA
403 */
404#define CONFIG_LIBATA
405#define CONFIG_FSL_SATA
406
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200407#define CONFIG_SYS_SATA_MAX_DEVICE 2
Kim Phillips730e7922008-03-28 14:31:23 -0500408#define CONFIG_SATA1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200409#define CONFIG_SYS_SATA1_OFFSET 0x18000
Joe Hershberger6f681b72011-10-11 23:57:11 -0500410#define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET)
411#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
Kim Phillips730e7922008-03-28 14:31:23 -0500412#define CONFIG_SATA2
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200413#define CONFIG_SYS_SATA2_OFFSET 0x19000
Joe Hershberger6f681b72011-10-11 23:57:11 -0500414#define CONFIG_SYS_SATA2 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET)
415#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
Kim Phillips730e7922008-03-28 14:31:23 -0500416
417#ifdef CONFIG_FSL_SATA
418#define CONFIG_LBA48
419#define CONFIG_CMD_SATA
Kim Phillips730e7922008-03-28 14:31:23 -0500420#endif
421
422/*
Dave Liu8bd522c2008-01-11 18:48:24 +0800423 * Environment
424 */
Masahiro Yamadad0fb0fc2014-06-04 10:26:51 +0900425#if !defined(CONFIG_SYS_RAMBOOT)
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200426 #define CONFIG_ENV_IS_IN_FLASH 1
Joe Hershberger6f681b72011-10-11 23:57:11 -0500427 #define CONFIG_ENV_ADDR \
428 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200429 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */
430 #define CONFIG_ENV_SIZE 0x2000
Dave Liu8bd522c2008-01-11 18:48:24 +0800431#else
Jean-Christophe PLAGNIOL-VILLARD93f6d722008-09-10 22:48:00 +0200432 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200433 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200434 #define CONFIG_ENV_SIZE 0x2000
Dave Liu8bd522c2008-01-11 18:48:24 +0800435#endif
436
437#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200438#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
Dave Liu8bd522c2008-01-11 18:48:24 +0800439
440/*
441 * BOOTP options
442 */
443#define CONFIG_BOOTP_BOOTFILESIZE
444#define CONFIG_BOOTP_BOOTPATH
445#define CONFIG_BOOTP_GATEWAY
446#define CONFIG_BOOTP_HOSTNAME
447
448/*
449 * Command line configuration.
450 */
Dave Liu8bd522c2008-01-11 18:48:24 +0800451#define CONFIG_CMD_PCI
452
Dave Liu8bd522c2008-01-11 18:48:24 +0800453#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
Joe Hershberger6f681b72011-10-11 23:57:11 -0500454#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
Dave Liu8bd522c2008-01-11 18:48:24 +0800455
456#undef CONFIG_WATCHDOG /* watchdog disabled */
457
458/*
459 * Miscellaneous configurable options
460 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200461#define CONFIG_SYS_LONGHELP /* undef to save memory */
462#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Dave Liu8bd522c2008-01-11 18:48:24 +0800463
464#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200465 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Dave Liu8bd522c2008-01-11 18:48:24 +0800466#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200467 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Dave Liu8bd522c2008-01-11 18:48:24 +0800468#endif
469
Joe Hershberger6f681b72011-10-11 23:57:11 -0500470 /* Print Buffer Size */
471#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
472#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
473 /* Boot Argument Buffer Size */
474#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
Dave Liu8bd522c2008-01-11 18:48:24 +0800475
476/*
477 * For booting Linux, the board info and command line data
Ira W. Snyder9f530d52010-09-10 15:42:32 -0700478 * have to be in the first 256 MB of memory, since this is
Dave Liu8bd522c2008-01-11 18:48:24 +0800479 * the maximum mapped by the Linux kernel during initialization.
480 */
Joe Hershberger6f681b72011-10-11 23:57:11 -0500481#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
Kevin Hao63865272016-07-08 11:25:15 +0800482#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
Dave Liu8bd522c2008-01-11 18:48:24 +0800483
484/*
485 * Core HID Setup
486 */
Kim Phillips1a2e2032010-04-20 19:37:54 -0500487#define CONFIG_SYS_HID0_INIT 0x000000000
488#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
489 HID0_ENABLE_INSTRUCTION_CACHE | \
Dave Liu8bd522c2008-01-11 18:48:24 +0800490 HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200491#define CONFIG_SYS_HID2 HID2_HBE
Dave Liu8bd522c2008-01-11 18:48:24 +0800492
493/*
494 * MMU Setup
495 */
Becky Bruce31d82672008-05-08 19:02:12 -0500496#define CONFIG_HIGH_BATS 1 /* High BATs supported */
Dave Liu8bd522c2008-01-11 18:48:24 +0800497
498/* DDR: cache cacheable */
Joe Hershberger6f681b72011-10-11 23:57:11 -0500499#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500500 | BATL_PP_RW \
Joe Hershberger6f681b72011-10-11 23:57:11 -0500501 | BATL_MEMCOHERENCE)
502#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
503 | BATU_BL_128M \
504 | BATU_VS \
505 | BATU_VP)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200506#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
507#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
Dave Liu8bd522c2008-01-11 18:48:24 +0800508
509/* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
Joe Hershberger6f681b72011-10-11 23:57:11 -0500510#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500511 | BATL_PP_RW \
Joe Hershberger6f681b72011-10-11 23:57:11 -0500512 | BATL_CACHEINHIBIT \
513 | BATL_GUARDEDSTORAGE)
514#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR \
515 | BATU_BL_8M \
516 | BATU_VS \
517 | BATU_VP)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200518#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
519#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
Dave Liu8bd522c2008-01-11 18:48:24 +0800520
521/* FLASH: icache cacheable, but dcache-inhibit and guarded */
Joe Hershberger6f681b72011-10-11 23:57:11 -0500522#define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500523 | BATL_PP_RW \
Joe Hershberger6f681b72011-10-11 23:57:11 -0500524 | BATL_MEMCOHERENCE)
525#define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE \
526 | BATU_BL_32M \
527 | BATU_VS \
528 | BATU_VP)
529#define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500530 | BATL_PP_RW \
Joe Hershberger6f681b72011-10-11 23:57:11 -0500531 | BATL_CACHEINHIBIT \
532 | BATL_GUARDEDSTORAGE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200533#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
Dave Liu8bd522c2008-01-11 18:48:24 +0800534
535/* Stack in dcache: cacheable, no memory coherence */
Joe Hershberger72cd4082011-10-11 23:57:28 -0500536#define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
Joe Hershberger6f681b72011-10-11 23:57:11 -0500537#define CONFIG_SYS_IBAT3U (CONFIG_SYS_INIT_RAM_ADDR \
538 | BATU_BL_128K \
539 | BATU_VS \
540 | BATU_VP)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200541#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
542#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
Dave Liu8bd522c2008-01-11 18:48:24 +0800543
544/* PCI MEM space: cacheable */
Joe Hershberger6f681b72011-10-11 23:57:11 -0500545#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI_MEM_PHYS \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500546 | BATL_PP_RW \
Joe Hershberger6f681b72011-10-11 23:57:11 -0500547 | BATL_MEMCOHERENCE)
548#define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI_MEM_PHYS \
549 | BATU_BL_256M \
550 | BATU_VS \
551 | BATU_VP)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200552#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
553#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
Dave Liu8bd522c2008-01-11 18:48:24 +0800554
555/* PCI MMIO space: cache-inhibit and guarded */
Joe Hershberger6f681b72011-10-11 23:57:11 -0500556#define CONFIG_SYS_IBAT5L (CONFIG_SYS_PCI_MMIO_PHYS \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500557 | BATL_PP_RW \
Joe Hershberger6f681b72011-10-11 23:57:11 -0500558 | BATL_CACHEINHIBIT \
559 | BATL_GUARDEDSTORAGE)
560#define CONFIG_SYS_IBAT5U (CONFIG_SYS_PCI_MMIO_PHYS \
561 | BATU_BL_256M \
562 | BATU_VS \
563 | BATU_VP)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200564#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
565#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
Dave Liu8bd522c2008-01-11 18:48:24 +0800566
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200567#define CONFIG_SYS_IBAT6L 0
568#define CONFIG_SYS_IBAT6U 0
569#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
570#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
Dave Liu8bd522c2008-01-11 18:48:24 +0800571
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200572#define CONFIG_SYS_IBAT7L 0
573#define CONFIG_SYS_IBAT7U 0
574#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
575#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
Dave Liu8bd522c2008-01-11 18:48:24 +0800576
Dave Liu8bd522c2008-01-11 18:48:24 +0800577#if defined(CONFIG_CMD_KGDB)
578#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
Dave Liu8bd522c2008-01-11 18:48:24 +0800579#endif
580
581/*
582 * Environment Configuration
583 */
584
585#define CONFIG_ENV_OVERWRITE
586
587#if defined(CONFIG_TSEC_ENET)
588#define CONFIG_HAS_ETH0
Dave Liu8bd522c2008-01-11 18:48:24 +0800589#define CONFIG_HAS_ETH1
Dave Liu8bd522c2008-01-11 18:48:24 +0800590#endif
591
Kim Phillips79f516b2009-08-21 16:34:38 -0500592#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
Dave Liu8bd522c2008-01-11 18:48:24 +0800593
Dave Liu8bd522c2008-01-11 18:48:24 +0800594#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
595
596#define CONFIG_EXTRA_ENV_SETTINGS \
Joe Hershberger6f681b72011-10-11 23:57:11 -0500597 "netdev=eth0\0" \
598 "consoledev=ttyS0\0" \
599 "ramdiskaddr=1000000\0" \
600 "ramdiskfile=ramfs.83xx\0" \
601 "fdtaddr=780000\0" \
602 "fdtfile=mpc8315erdb.dtb\0" \
603 "usb_phy_type=utmi\0" \
604 ""
Dave Liu8bd522c2008-01-11 18:48:24 +0800605
606#define CONFIG_NFSBOOTCOMMAND \
Joe Hershberger6f681b72011-10-11 23:57:11 -0500607 "setenv bootargs root=/dev/nfs rw " \
608 "nfsroot=$serverip:$rootpath " \
609 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
610 "$netdev:off " \
611 "console=$consoledev,$baudrate $othbootargs;" \
612 "tftp $loadaddr $bootfile;" \
613 "tftp $fdtaddr $fdtfile;" \
614 "bootm $loadaddr - $fdtaddr"
Dave Liu8bd522c2008-01-11 18:48:24 +0800615
616#define CONFIG_RAMBOOTCOMMAND \
Joe Hershberger6f681b72011-10-11 23:57:11 -0500617 "setenv bootargs root=/dev/ram rw " \
618 "console=$consoledev,$baudrate $othbootargs;" \
619 "tftp $ramdiskaddr $ramdiskfile;" \
620 "tftp $loadaddr $bootfile;" \
621 "tftp $fdtaddr $fdtfile;" \
622 "bootm $loadaddr $ramdiskaddr $fdtaddr"
Dave Liu8bd522c2008-01-11 18:48:24 +0800623
Dave Liu8bd522c2008-01-11 18:48:24 +0800624#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
625
626#endif /* __CONFIG_H */