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Prabhakar Kushwahaafa6b552012-04-29 23:56:13 +00001External Debug Support
2----------------------
3
4Freescale's e500v1 and e500v2 cores (used in mpc85xx chips) have some
5restrictions on external debugging (JTAG). In particular, for the debugger to
6be able to receive control after a single step or breakpoint:
7 - MSR[DE] must be set
8 - A valid opcode must be fetchable, through the MMU, from the debug
9 exception vector (IVPR + IVOR15).
10
11To maximize the time during which this requirement is met, U-Boot sets MSR[DE]
12immediately on entry and keeps it set. It also uses a temporary TLB to keep a
13mapping to a valid opcode at the debug exception vector, even if we normally
14don't support exception vectors being used that early, and that's not the area
15where U-Boot currently executes from.
16
17Note that there may still be some small windows where debugging will not work,
18such as in between updating IVPR and IVOR15.
19
20Config Switches:
21----------------
22
23Please refer README section "MPC85xx External Debug Support"
24
25Major Config Switches during various boot Modes
26----------------------------------------------
27
28NOR boot
Scott Woodc97cd1b2012-09-20 19:02:18 -050029 !defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SPL)
Prabhakar Kushwahaafa6b552012-04-29 23:56:13 +000030NOR boot Secure
Udit Agarwalbef18452019-11-07 16:11:39 +000031 !defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_NXP_ESBC)
Prabhakar Kushwahaafa6b552012-04-29 23:56:13 +000032RAMBOOT(SD, SPI & NAND boot)
Wolfgang Denk00c60f92012-07-22 21:58:26 +020033 defined(CONFIG_SYS_RAMBOOT)
Prabhakar Kushwahaafa6b552012-04-29 23:56:13 +000034RAMBOOT Secure (SD, SPI & NAND)
Udit Agarwalbef18452019-11-07 16:11:39 +000035 defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_NXP_ESBC)
Prabhakar Kushwahaafa6b552012-04-29 23:56:13 +000036NAND SPL BOOT
Wolfgang Denk00c60f92012-07-22 21:58:26 +020037 defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_NAND_SPL)
Prabhakar Kushwahaafa6b552012-04-29 23:56:13 +000038
39
40TLB Entries during u-boot execution
41-----------------------------------
42
43Note: Sequence number is in order of execution
44
45A) defined(CONFIG_SYS_RAMBOOT) i.e. SD, SPI, NAND RAMBOOT & NAND_SPL boot
46
47 1) TLB entry to overcome e500 v1/v2 debug restriction
Pali Rohárde14a5a2022-04-03 00:05:09 +020048 Location : Label "_start"
Prabhakar Kushwahaafa6b552012-04-29 23:56:13 +000049 TLB Entry : CONFIG_SYS_PPC_E500_DEBUG_TLB
50 EPN -->RPN : CONFIG_SYS_MONITOR_BASE --> CONFIG_SYS_MONITOR_BASE
51 Properties : 256K, AS0, I, IPROT
52
53 2) TLB entry for working in AS1
Wolfgang Denk00c60f92012-07-22 21:58:26 +020054 Location : Label "create_init_ram_area"
Prabhakar Kushwahaafa6b552012-04-29 23:56:13 +000055 TLB Entry : 15
56 EPN -->RPN : CONFIG_SYS_MONITOR_BASE --> CONFIG_SYS_MONITOR_BASE
57 Properties : 1M, AS1, I, G, IPROT
58
59 3) TLB entry for the stack during AS1
Wolfgang Denk00c60f92012-07-22 21:58:26 +020060 Location : Lable "create_init_ram_area"
Prabhakar Kushwahaafa6b552012-04-29 23:56:13 +000061 TLB Entry : 14
Tom Rini65cc0e22022-11-16 13:10:41 -050062 EPN -->RPN : CFG_SYS_INIT_RAM_ADDR --> CFG_SYS_INIT_RAM_ADDR
Prabhakar Kushwahaafa6b552012-04-29 23:56:13 +000063 Properties : 16K, AS1, IPROT
64
65 4) TLB entry for CCSRBAR during AS1 execution
Wolfgang Denk00c60f92012-07-22 21:58:26 +020066 Location : cpu_init_early_f
Prabhakar Kushwahaafa6b552012-04-29 23:56:13 +000067 TLB Entry : 13
Tom Rini65cc0e22022-11-16 13:10:41 -050068 EPN -->RPN : CFG_SYS_CCSRBAR --> CFG_SYS_CCSRBAR
Prabhakar Kushwahaafa6b552012-04-29 23:56:13 +000069 Properties : 1M, AS1, I, G
70
71 5) Invalidate unproctected TLB Entries
Wolfgang Denk00c60f92012-07-22 21:58:26 +020072 Location : cpu_init_early_f
Prabhakar Kushwahaafa6b552012-04-29 23:56:13 +000073 Invalidated: 13
74
75 6) Create TLB entries as per boards/freescale/<board>/tlb.c
Wolfgang Denk00c60f92012-07-22 21:58:26 +020076 Location : cpu_init_early_f --> init_tlbs()
Prabhakar Kushwahaafa6b552012-04-29 23:56:13 +000077 Properties : ..., AS0, ...
78 Please note It can overwrites previous TLB Entries.
79
80 7) Disable TLB Entries of AS1
Wolfgang Denk00c60f92012-07-22 21:58:26 +020081 Location : cpu_init_f --> disable_tlb()
82 Disable : 15, 14
Prabhakar Kushwahaafa6b552012-04-29 23:56:13 +000083
84 8) Update Flash's TLB entry
Wolfgang Denk00c60f92012-07-22 21:58:26 +020085 Location : Board_init_r
Prabhakar Kushwahaafa6b552012-04-29 23:56:13 +000086 TLB entry : Search from TLB entries
Tom Rini65cc0e22022-11-16 13:10:41 -050087 EPN -->RPN : CFG_SYS_FLASH_BASE --> CFG_SYS_FLASH_BASE_PHYS
Prabhakar Kushwahaafa6b552012-04-29 23:56:13 +000088 Properties : Board specific size, AS0, I, G, IPROT
89
90
91B) !defined(CONFIG_SYS_RAMBOOT) i.e. NOR boot
92
93 1) TLB entry to overcome e500 v1/v2 debug restriction
Pali Rohárde14a5a2022-04-03 00:05:09 +020094 Location : Label "_start"
Prabhakar Kushwahaafa6b552012-04-29 23:56:13 +000095 TLB Entry : CONFIG_SYS_PPC_E500_DEBUG_TLB
Udit Agarwalbef18452019-11-07 16:11:39 +000096#if defined(CONFIG_NXP_ESBC)
Tom Rini65cc0e22022-11-16 13:10:41 -050097 EPN -->RPN : CONFIG_SYS_MONITOR_BASE --> CFG_SYS_PBI_FLASH_WINDOW
Prabhakar Kushwahaafa6b552012-04-29 23:56:13 +000098 Properties : 1M, AS1, I, G, IPROT
99#else
100 EPN -->RPN : CONFIG_SYS_MONITOR_BASE & 0xffc00000 --> 0xffc00000
101 Properties : 4M, AS0, I, G, IPROT
102#endif
103
104 2) TLB entry for working in AS1
Wolfgang Denk00c60f92012-07-22 21:58:26 +0200105 Location : Label "create_init_ram_area"
Prabhakar Kushwahaafa6b552012-04-29 23:56:13 +0000106 TLB Entry : 15
Udit Agarwalbef18452019-11-07 16:11:39 +0000107#if defined(CONFIG_NXP_ESBC)
Tom Rini65cc0e22022-11-16 13:10:41 -0500108 EPN -->RPN : CONFIG_SYS_MONITOR_BASE --> CFG_SYS_PBI_FLASH_WINDOW
Prabhakar Kushwahaafa6b552012-04-29 23:56:13 +0000109 Properties : 1M, AS1, I, G, IPROT
110#else
111 EPN -->RPN : CONFIG_SYS_MONITOR_BASE & 0xffc00000 --> 0xffc00000
112 Properties : 4M, AS1, I, G, IPROT
113#endif
114
115 3) TLB entry for the stack during AS1
Wolfgang Denk00c60f92012-07-22 21:58:26 +0200116 Location : Lable "create_init_ram_area"
Prabhakar Kushwahaafa6b552012-04-29 23:56:13 +0000117 TLB Entry : 14
Tom Rini65cc0e22022-11-16 13:10:41 -0500118 EPN -->RPN : CFG_SYS_INIT_RAM_ADDR --> CFG_SYS_INIT_RAM_ADDR
Prabhakar Kushwahaafa6b552012-04-29 23:56:13 +0000119 Properties : 16K, AS1, IPROT
120
121 4) TLB entry for CCSRBAR during AS1 execution
Wolfgang Denk00c60f92012-07-22 21:58:26 +0200122 Location : cpu_init_early_f
Prabhakar Kushwahaafa6b552012-04-29 23:56:13 +0000123 TLB Entry : 13
Tom Rini65cc0e22022-11-16 13:10:41 -0500124 EPN -->RPN : CFG_SYS_CCSRBAR --> CFG_SYS_CCSRBAR
Prabhakar Kushwahaafa6b552012-04-29 23:56:13 +0000125 Properties : 1M, AS1, I, G
126
127 5) TLB entry for Errata workaround CONFIG_SYS_FSL_ERRATUM_IFC_A003399
Wolfgang Denk00c60f92012-07-22 21:58:26 +0200128 Location : cpu_init_early_f
Prabhakar Kushwahaafa6b552012-04-29 23:56:13 +0000129 TLB Entry : 9
130 EPN -->RPN : SRAM_BASE_ADDR --> SRAM_BASE_ADDR
131 Properties : 1M, AS1, I
132
133 6) CONFIG_SYS_FSL_ERRATUM_IFC_A003399 Adjust flash's phys addr
Wolfgang Denk00c60f92012-07-22 21:58:26 +0200134 Location : cpu_init_early_f --> setup_ifc
Prabhakar Kushwahaafa6b552012-04-29 23:56:13 +0000135 TLB Entry : Get Flash TLB
136 EPN -->RPN : Adjusted flash_phys --> Adjusted flash_phys
137 Properties : 4M, AS1, I, G, IPROT
138
139 7) CONFIG_SYS_FSL_ERRATUM_IFC_A003399: E500 v1,v2 debug restriction
Wolfgang Denk00c60f92012-07-22 21:58:26 +0200140 Location : cpu_init_early_f --> setup_ifc
Prabhakar Kushwahaafa6b552012-04-29 23:56:13 +0000141 TLB Entry : CONFIG_SYS_PPC_E500_DEBUG_TLB
142 EPN -->RPN : Adjusted flash_phys --> Adjusted flash_phys
143 Properties : 4M, AS0, I, G, IPROT
144
145 8) Invalidate unproctected TLB Entries
Wolfgang Denk00c60f92012-07-22 21:58:26 +0200146 Location : cpu_init_early_f
Prabhakar Kushwahaafa6b552012-04-29 23:56:13 +0000147 Invalidated: 13, 9
148
149 9) Create TLB entries as per boards/freescale/<board>/tlb.c
Wolfgang Denk00c60f92012-07-22 21:58:26 +0200150 Location : cpu_init_early_f --> init_tlbs()
Prabhakar Kushwahaafa6b552012-04-29 23:56:13 +0000151 Properties : ..., AS0, ...
152 Note: It can overwrites previous TLB Entries
153
154 10) Disable TLB Entries of AS1
Wolfgang Denk00c60f92012-07-22 21:58:26 +0200155 Location : cpu_init_f --> disable_tlb()
156 Disable : 15, 14
Prabhakar Kushwahaafa6b552012-04-29 23:56:13 +0000157
158 11) Create DDR's TLB entriy
Simon Glassf1683aa2017-04-06 12:47:05 -0600159 Location : Board_init_f -> dram_init
Prabhakar Kushwahaafa6b552012-04-29 23:56:13 +0000160 TLB entry : Search free TLB entry
161
162 12) Update Flash's TLB entry
Wolfgang Denk00c60f92012-07-22 21:58:26 +0200163 Location : Board_init_r
Prabhakar Kushwahaafa6b552012-04-29 23:56:13 +0000164 TLB entry : Search from TLB entries
Tom Rini65cc0e22022-11-16 13:10:41 -0500165 EPN -->RPN : CFG_SYS_FLASH_BASE --> CFG_SYS_FLASH_BASE_PHYS
Prabhakar Kushwahaafa6b552012-04-29 23:56:13 +0000166 Properties : Board specific size, AS0, I, G, IPROT