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wdenk0e6d7982004-03-14 00:07:33 +00001/*
2 * (C) Copyright 2004 Paul Reynolds <PaulReynolds@lhsolutions.com>
3 *
Stefan Roese8a316c92005-08-01 16:49:12 +02004 * (C) Copyright 2005
5 * Stefan Roese, DENX Software Engineering, sr@denx.de.
6 *
wdenk0e6d7982004-03-14 00:07:33 +00007 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26/************************************************************************
wdenk42dfe7a2004-03-14 22:25:36 +000027 * 1 March 2004 Travis B. Sawyer <tsawyer@sandburst.com>
wdenk0e6d7982004-03-14 00:07:33 +000028 * Adapted to current Das U-Boot source
29 ***********************************************************************/
30
31
32/************************************************************************
Wolfgang Denk0c8721a2005-09-23 11:05:55 +020033 * OCOTEA.h - configuration for AMCC 440GX Ref (Ocotea)
wdenk0e6d7982004-03-14 00:07:33 +000034 ***********************************************************************/
35
36#ifndef __CONFIG_H
37#define __CONFIG_H
38
39/*-----------------------------------------------------------------------
40 * High Level Configuration Options
41 *----------------------------------------------------------------------*/
42#define CONFIG_OCOTEA 1 /* Board is ebony */
Stefan Roese846b0dd2005-08-08 12:42:22 +020043#define CONFIG_440GX 1 /* Specifc GX support */
wdenk0e6d7982004-03-14 00:07:33 +000044#define CONFIG_4xx 1 /* ... PPC4xx family */
45#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
46#undef CFG_DRAM_TEST /* Disable-takes long time! */
47#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
48
49/*-----------------------------------------------------------------------
50 * Base addresses -- Note these are effective addresses where the
51 * actual resources get mapped (not physical addresses)
52 *----------------------------------------------------------------------*/
53#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
54#define CFG_FLASH_BASE 0xff800000 /* start of FLASH */
stroese7ec25502005-04-07 05:35:12 +000055#define CFG_MONITOR_BASE 0xfffc0000 /* start of monitor */
wdenk0e6d7982004-03-14 00:07:33 +000056#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */
57#define CFG_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */
58#define CFG_ISRAM_BASE 0xc0000000 /* internal SRAM */
59#define CFG_PCI_BASE 0xd0000000 /* internal PCI regs */
60
61#define CFG_FPGA_BASE (CFG_PERIPHERAL_BASE + 0x08300000)
62#define CFG_NVRAM_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x08000000)
63
64/*-----------------------------------------------------------------------
65 * Initial RAM & stack pointer (placed in internal SRAM)
66 *----------------------------------------------------------------------*/
67#define CFG_TEMP_STACK_OCM 1
68#define CFG_OCM_DATA_ADDR CFG_ISRAM_BASE
69#define CFG_INIT_RAM_ADDR CFG_ISRAM_BASE /* Initial RAM address */
70#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */
71#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
72
73#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
wdenk42dfe7a2004-03-14 22:25:36 +000074#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4)
75#define CFG_INIT_SP_OFFSET CFG_POST_WORD_ADDR
wdenk0e6d7982004-03-14 00:07:33 +000076
77#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
78#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc*/
79
80/*-----------------------------------------------------------------------
81 * Serial Port
82 *----------------------------------------------------------------------*/
83#undef CONFIG_SERIAL_SOFTWARE_FIFO
84#define CFG_EXT_SERIAL_CLOCK (1843200 * 6) /* Ext clk @ 11.059 MHz */
85#define CONFIG_BAUDRATE 115200
86
87#define CFG_BAUDRATE_TABLE \
88 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
89
90/*-----------------------------------------------------------------------
Stefan Roese8a316c92005-08-01 16:49:12 +020091 * Environment
92 *----------------------------------------------------------------------*/
93/*
94 * Define here the location of the environment variables (FLASH or NVRAM).
95 * Note: DENX encourages to use redundant environment in FLASH. NVRAM is only
96 * supported for backward compatibility.
97 */
98#if 1
99#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
100#else
101#define CFG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */
102#endif
103
104
105/*-----------------------------------------------------------------------
wdenk0e6d7982004-03-14 00:07:33 +0000106 * NVRAM/RTC
107 *
108 * NOTE: Upper 8 bytes of NVRAM is where the RTC registers are located.
109 * The DS1743 code assumes this condition (i.e. -- it assumes the base
110 * address for the RTC registers is:
111 *
112 * CFG_NVRAM_BASE_ADDR + CFG_NVRAM_SIZE
113 *
114 *----------------------------------------------------------------------*/
115#define CFG_NVRAM_SIZE (0x2000 - 8) /* NVRAM size(8k)- RTC regs */
116#define CONFIG_RTC_DS174x 1 /* DS1743 RTC */
117
Stefan Roese8a316c92005-08-01 16:49:12 +0200118#ifdef CFG_ENV_IS_IN_NVRAM
119#define CFG_ENV_SIZE 0x1000 /* Size of Environment vars */
120#define CFG_ENV_ADDR \
121 (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE)
122#endif /* CFG_ENV_IS_IN_NVRAM */
123
wdenk0e6d7982004-03-14 00:07:33 +0000124/*-----------------------------------------------------------------------
125 * FLASH related
126 *----------------------------------------------------------------------*/
127#define CFG_MAX_FLASH_BANKS 3 /* number of banks */
128#define CFG_MAX_FLASH_SECT 64 /* sectors per device */
129
130#undef CFG_FLASH_CHECKSUM
131#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
132#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
133
Stefan Roese8a316c92005-08-01 16:49:12 +0200134#define CFG_FLASH_ADDR0 0x5555
135#define CFG_FLASH_ADDR1 0x2aaa
136#define CFG_FLASH_WORD_SIZE unsigned char
137
138#ifdef CFG_ENV_IS_IN_FLASH
139#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
140#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
141#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
142
143/* Address and size of Redundant Environment Sector */
144#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
145#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
146#endif /* CFG_ENV_IS_IN_FLASH */
147
wdenk0e6d7982004-03-14 00:07:33 +0000148/*-----------------------------------------------------------------------
149 * DDR SDRAM
150 *----------------------------------------------------------------------*/
wdenk42dfe7a2004-03-14 22:25:36 +0000151#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup */
152#define SPD_EEPROM_ADDRESS {0x53,0x52} /* SPD i2c spd addresses */
wdenk0e6d7982004-03-14 00:07:33 +0000153
154/*-----------------------------------------------------------------------
155 * I2C
156 *----------------------------------------------------------------------*/
157#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
158#undef CONFIG_SOFT_I2C /* I2C bit-banged */
159#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
160#define CFG_I2C_SLAVE 0x7F
Stefan Roese4f92ed52006-08-07 14:33:32 +0200161
162#define CFG_I2C_MULTI_EEPROMS
163#define CFG_I2C_EEPROM_ADDR (0xa8>>1)
164#define CFG_I2C_EEPROM_ADDR_LEN 1
165#define CFG_EEPROM_PAGE_WRITE_ENABLE
166#define CFG_EEPROM_PAGE_WRITE_BITS 3
167#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
wdenk0e6d7982004-03-14 00:07:33 +0000168
Stefan Roese8a316c92005-08-01 16:49:12 +0200169#define CONFIG_PREBOOT "echo;" \
170 "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
171 "echo"
wdenk0e6d7982004-03-14 00:07:33 +0000172
Stefan Roese8a316c92005-08-01 16:49:12 +0200173#undef CONFIG_BOOTARGS
wdenk0e6d7982004-03-14 00:07:33 +0000174
Stefan Roese8a316c92005-08-01 16:49:12 +0200175#define CONFIG_EXTRA_ENV_SETTINGS \
176 "netdev=eth0\0" \
177 "hostname=ocotea\0" \
178 "nfsargs=setenv bootargs root=/dev/nfs rw " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100179 "nfsroot=${serverip}:${rootpath}\0" \
Stefan Roese8a316c92005-08-01 16:49:12 +0200180 "ramargs=setenv bootargs root=/dev/ram rw\0" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100181 "addip=setenv bootargs ${bootargs} " \
182 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
183 ":${hostname}:${netdev}:off panic=1\0" \
184 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
Stefan Roese8a316c92005-08-01 16:49:12 +0200185 "flash_nfs=run nfsargs addip addtty;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100186 "bootm ${kernel_addr}\0" \
Stefan Roese8a316c92005-08-01 16:49:12 +0200187 "flash_self=run ramargs addip addtty;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100188 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
189 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
Stefan Roese8a316c92005-08-01 16:49:12 +0200190 "bootm\0" \
191 "rootpath=/opt/eldk/ppc_4xx\0" \
192 "bootfile=/tftpboot/ocotea/uImage\0" \
193 "kernel_addr=fff00000\0" \
194 "ramdisk_addr=fff10000\0" \
Stefan Roese5a753f92007-02-07 16:51:08 +0100195 "initrd_high=30000000\0" \
Stefan Roese8a316c92005-08-01 16:49:12 +0200196 "load=tftp 100000 /tftpboot/ocotea/u-boot.bin\0" \
197 "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \
198 "cp.b 100000 fffc0000 40000;" \
199 "setenv filesize;saveenv\0" \
200 "upd=run load;run update\0" \
201 ""
202#define CONFIG_BOOTCOMMAND "run flash_self"
wdenk0e6d7982004-03-14 00:07:33 +0000203
Stefan Roese8a316c92005-08-01 16:49:12 +0200204#if 0
205#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
206#else
207#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
208#endif
209
wdenk0e6d7982004-03-14 00:07:33 +0000210#define CONFIG_BAUDRATE 115200
211
212#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
213#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
214
215#define CONFIG_MII 1 /* MII PHY management */
216#define CONFIG_NET_MULTI 1
217#define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */
wdenk42dfe7a2004-03-14 22:25:36 +0000218#define CONFIG_PHY1_ADDR 2
219#define CONFIG_PHY2_ADDR 0x10
220#define CONFIG_PHY3_ADDR 0x18
Stefan Roesed6c61aa2005-08-16 18:18:00 +0200221#define CONFIG_HAS_ETH0
222#define CONFIG_HAS_ETH1
223#define CONFIG_HAS_ETH2
224#define CONFIG_HAS_ETH3
wdenk42dfe7a2004-03-14 22:25:36 +0000225#define CONFIG_CIS8201_PHY 1 /* Enable 'special' RGMII mode for Cicada phy */
wdenk6fb6af62004-03-23 23:20:24 +0000226#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
Stefan Roesed6c61aa2005-08-16 18:18:00 +0200227#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
228#define CONFIG_PHY_RESET_DELAY 1000
Stefan Roese4f92ed52006-08-07 14:33:32 +0200229#define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
230
231#define CONFIG_NETCONSOLE /* include NetConsole support */
wdenk0e6d7982004-03-14 00:07:33 +0000232
233#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
Stefan Roese8a316c92005-08-01 16:49:12 +0200234 CFG_CMD_ASKENV | \
wdenk414eec32005-04-02 22:37:54 +0000235 CFG_CMD_DATE | \
236 CFG_CMD_DHCP | \
wdenk42dfe7a2004-03-14 22:25:36 +0000237 CFG_CMD_DIAG | \
wdenk414eec32005-04-02 22:37:54 +0000238 CFG_CMD_ELF | \
Stefan Roese4f92ed52006-08-07 14:33:32 +0200239 CFG_CMD_EEPROM | \
wdenk414eec32005-04-02 22:37:54 +0000240 CFG_CMD_I2C | \
241 CFG_CMD_IRQ | \
wdenk42dfe7a2004-03-14 22:25:36 +0000242 CFG_CMD_MII | \
243 CFG_CMD_NET | \
wdenk414eec32005-04-02 22:37:54 +0000244 CFG_CMD_NFS | \
245 CFG_CMD_PCI | \
246 CFG_CMD_PING | \
Stefan Roese8a316c92005-08-01 16:49:12 +0200247 CFG_CMD_REGINFO | \
248 CFG_CMD_SDRAM | \
wdenk414eec32005-04-02 22:37:54 +0000249 CFG_CMD_SNTP )
wdenk0e6d7982004-03-14 00:07:33 +0000250
251/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
252#include <cmd_confdefs.h>
253
254#undef CONFIG_WATCHDOG /* watchdog disabled */
255
256/*
257 * Miscellaneous configurable options
258 */
259#define CFG_LONGHELP /* undef to save memory */
260#define CFG_PROMPT "=> " /* Monitor Command Prompt */
261#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
262#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
263#else
264#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
265#endif
266#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
267#define CFG_MAXARGS 16 /* max number of command args */
268#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
269
270#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
271#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
272
273#define CFG_LOAD_ADDR 0x100000 /* default load address */
274#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
275
Stefan Roesed6c61aa2005-08-16 18:18:00 +0200276#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenk0e6d7982004-03-14 00:07:33 +0000277
Stefan Roese4f92ed52006-08-07 14:33:32 +0200278#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
Stefan Roese8a316c92005-08-01 16:49:12 +0200279#define CONFIG_LOOPW 1 /* enable loopw command */
Stefan Roese4f92ed52006-08-07 14:33:32 +0200280#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
Stefan Roese8a316c92005-08-01 16:49:12 +0200281#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
282#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
283
wdenk0e6d7982004-03-14 00:07:33 +0000284/*-----------------------------------------------------------------------
285 * PCI stuff
286 *-----------------------------------------------------------------------
287 */
288/* General PCI */
Stefan Roese8a316c92005-08-01 16:49:12 +0200289#define CONFIG_PCI /* include pci support */
290#define CONFIG_PCI_PNP /* do pci plug-and-play */
wdenk42dfe7a2004-03-14 22:25:36 +0000291#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
292#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */
wdenk0e6d7982004-03-14 00:07:33 +0000293
294/* Board-specific PCI */
wdenk42dfe7a2004-03-14 22:25:36 +0000295#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */
Stefan Roese8a316c92005-08-01 16:49:12 +0200296#define CFG_PCI_TARGET_INIT /* let board init pci target */
wdenk0e6d7982004-03-14 00:07:33 +0000297
Stefan Roese8a316c92005-08-01 16:49:12 +0200298#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
wdenk42dfe7a2004-03-14 22:25:36 +0000299#define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
wdenk0e6d7982004-03-14 00:07:33 +0000300
301/*
302 * For booting Linux, the board info and command line data
303 * have to be in the first 8 MB of memory, since this is
304 * the maximum mapped by the Linux kernel during initialization.
305 */
306#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
307/*-----------------------------------------------------------------------
308 * Cache Configuration
309 */
Wolfgang Denk0c8721a2005-09-23 11:05:55 +0200310#define CFG_DCACHE_SIZE 32768 /* For AMCC 440 CPUs */
wdenk0e6d7982004-03-14 00:07:33 +0000311#define CFG_CACHELINE_SIZE 32 /* ... */
312#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
313#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
314#endif
315
316/*
317 * Internal Definitions
318 *
319 * Boot Flags
320 */
321#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
322#define BOOTFLAG_WARM 0x02 /* Software reboot */
323
324#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
325#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
326#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
327#endif
328#endif /* __CONFIG_H */