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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Siva Durga Prasad Paladugu26780592018-01-05 16:16:16 +05302/*
3 * dts file for Xilinx ZynqMP Mini Configuration
4 *
5 * (C) Copyright 2018, Xilinx, Inc.
6 *
7 * Siva Durga Prasad <siva.durga.paladugu@xilinx.com>
Siva Durga Prasad Paladugu26780592018-01-05 16:16:16 +05308 */
9
10/dts-v1/;
11
12/ {
Michal Simekf3289d12018-11-21 15:52:31 +010013 model = "ZynqMP MINI EMMC1";
Siva Durga Prasad Paladugu26780592018-01-05 16:16:16 +053014 compatible = "xlnx,zynqmp";
15 #address-cells = <2>;
16 #size-cells = <2>;
17
18 aliases {
19 serial0 = &dcc;
Siva Durga Prasad Paladugubc0f4ed2018-06-05 15:18:32 +053020 mmc0 = &sdhci1;
Siva Durga Prasad Paladugu26780592018-01-05 16:16:16 +053021 };
22
23 chosen {
24 stdout-path = "serial0:115200n8";
25 };
26
27 memory@0 {
28 device_type = "memory";
29 reg = <0x0 0x0 0x0 0x20000000>;
30 };
31
32 dcc: dcc {
33 compatible = "arm,dcc";
34 status = "disabled";
35 u-boot,dm-pre-reloc;
36 };
37
Siva Durga Prasad Paladugubc0f4ed2018-06-05 15:18:32 +053038 clk_xin: clk_xin {
39 compatible = "fixed-clock";
40 #clock-cells = <0>;
41 clock-frequency = <200000000>;
42 };
43
Siva Durga Prasad Paladugu26780592018-01-05 16:16:16 +053044 amba: amba {
45 compatible = "simple-bus";
46 #address-cells = <2>;
47 #size-cells = <2>;
48 ranges;
49
Siva Durga Prasad Paladugu26780592018-01-05 16:16:16 +053050 sdhci1: sdhci@ff170000 {
51 u-boot,dm-pre-reloc;
52 compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
53 status = "disabled";
54 reg = <0x0 0xff170000 0x0 0x1000>;
Michal Simek92226b52018-07-20 11:34:00 +020055 clock-names = "clk_xin", "clk_ahb";
56 clocks = <&clk_xin &clk_xin>;
Siva Durga Prasad Paladugu26780592018-01-05 16:16:16 +053057 xlnx,device_id = <1>;
58 };
59 };
60};
61
62&dcc {
63 status = "okay";
64};
65
Siva Durga Prasad Paladugu26780592018-01-05 16:16:16 +053066&sdhci1 {
67 status = "okay";
68};