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Jagan Teki0d47bc72018-12-22 21:32:49 +05301// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2018 Amarula Solutions.
4 * Author: Jagan Teki <jagan@amarulasolutions.com>
5 */
6
7#include <common.h>
8#include <clk-uclass.h>
9#include <dm.h>
10#include <errno.h>
Simon Glassf7ae49f2020-05-10 11:40:05 -060011#include <log.h>
Andre Przywara13b08672019-01-29 15:54:08 +000012#include <reset.h>
Jagan Teki0d47bc72018-12-22 21:32:49 +053013#include <asm/io.h>
Samuel Holland21d314a2021-09-12 11:48:43 -050014#include <clk/sunxi.h>
Simon Glasscd93d622020-05-10 11:40:13 -060015#include <linux/bitops.h>
Jagan Teki0d47bc72018-12-22 21:32:49 +053016#include <linux/log2.h>
17
Samuel Holland5af97b62022-05-09 00:29:35 -050018static const struct ccu_clk_gate *plat_to_gate(struct ccu_plat *plat,
Jagan Teki0d47bc72018-12-22 21:32:49 +053019 unsigned long id)
20{
Samuel Holland5af97b62022-05-09 00:29:35 -050021 if (id >= plat->desc->num_gates)
Samuel Holland6827aba2022-05-09 00:29:32 -050022 return NULL;
23
Samuel Holland5af97b62022-05-09 00:29:35 -050024 return &plat->desc->gates[id];
Jagan Teki0d47bc72018-12-22 21:32:49 +053025}
26
27static int sunxi_set_gate(struct clk *clk, bool on)
28{
Samuel Holland5af97b62022-05-09 00:29:35 -050029 struct ccu_plat *plat = dev_get_plat(clk->dev);
30 const struct ccu_clk_gate *gate = plat_to_gate(plat, clk->id);
Jagan Teki0d47bc72018-12-22 21:32:49 +053031 u32 reg;
32
Samuel Holland6827aba2022-05-09 00:29:32 -050033 if (gate && (gate->flags & CCU_CLK_F_DUMMY_GATE))
Andre Przywarad6cb09d2022-05-05 01:25:43 +010034 return 0;
35
Samuel Holland6827aba2022-05-09 00:29:32 -050036 if (!gate || !(gate->flags & CCU_CLK_F_IS_VALID)) {
Jagan Teki0d47bc72018-12-22 21:32:49 +053037 printf("%s: (CLK#%ld) unhandled\n", __func__, clk->id);
38 return 0;
39 }
40
41 debug("%s: (CLK#%ld) off#0x%x, BIT(%d)\n", __func__,
42 clk->id, gate->off, ilog2(gate->bit));
43
Samuel Holland5af97b62022-05-09 00:29:35 -050044 reg = readl(plat->base + gate->off);
Jagan Teki0d47bc72018-12-22 21:32:49 +053045 if (on)
46 reg |= gate->bit;
47 else
48 reg &= ~gate->bit;
49
Samuel Holland5af97b62022-05-09 00:29:35 -050050 writel(reg, plat->base + gate->off);
Jagan Teki0d47bc72018-12-22 21:32:49 +053051
52 return 0;
53}
54
55static int sunxi_clk_enable(struct clk *clk)
56{
57 return sunxi_set_gate(clk, true);
58}
59
60static int sunxi_clk_disable(struct clk *clk)
61{
62 return sunxi_set_gate(clk, false);
63}
64
65struct clk_ops sunxi_clk_ops = {
66 .enable = sunxi_clk_enable,
67 .disable = sunxi_clk_disable,
68};
69
Samuel Holland46fa23f2022-05-09 00:29:34 -050070static int sunxi_clk_bind(struct udevice *dev)
Samuel Hollandd39088a2022-05-09 00:29:33 -050071{
72 return sunxi_reset_bind(dev);
73}
74
Samuel Holland46fa23f2022-05-09 00:29:34 -050075static int sunxi_clk_probe(struct udevice *dev)
Jagan Teki0d47bc72018-12-22 21:32:49 +053076{
Andre Przywara13b08672019-01-29 15:54:08 +000077 struct clk_bulk clk_bulk;
78 struct reset_ctl_bulk rst_bulk;
79 int ret;
Jagan Teki0d47bc72018-12-22 21:32:49 +053080
Andre Przywara13b08672019-01-29 15:54:08 +000081 ret = clk_get_bulk(dev, &clk_bulk);
82 if (!ret)
83 clk_enable_bulk(&clk_bulk);
84
85 ret = reset_get_bulk(dev, &rst_bulk);
86 if (!ret)
87 reset_deassert_bulk(&rst_bulk);
88
Jagan Teki0d47bc72018-12-22 21:32:49 +053089 return 0;
90}
Samuel Holland46fa23f2022-05-09 00:29:34 -050091
Samuel Holland5af97b62022-05-09 00:29:35 -050092static int sunxi_clk_of_to_plat(struct udevice *dev)
93{
94 struct ccu_plat *plat = dev_get_plat(dev);
95
96 plat->base = dev_read_addr_ptr(dev);
97 if (!plat->base)
98 return -ENOMEM;
99
100 plat->desc = (const struct ccu_desc *)dev_get_driver_data(dev);
101 if (!plat->desc)
102 return -EINVAL;
103
104 return 0;
105}
106
Samuel Holland46fa23f2022-05-09 00:29:34 -0500107extern const struct ccu_desc a10_ccu_desc;
108extern const struct ccu_desc a10s_ccu_desc;
109extern const struct ccu_desc a23_ccu_desc;
110extern const struct ccu_desc a31_ccu_desc;
111extern const struct ccu_desc a31_r_ccu_desc;
112extern const struct ccu_desc a64_ccu_desc;
113extern const struct ccu_desc a80_ccu_desc;
114extern const struct ccu_desc a80_mmc_clk_desc;
115extern const struct ccu_desc a83t_ccu_desc;
116extern const struct ccu_desc f1c100s_ccu_desc;
117extern const struct ccu_desc h3_ccu_desc;
118extern const struct ccu_desc h6_ccu_desc;
119extern const struct ccu_desc h616_ccu_desc;
120extern const struct ccu_desc h6_r_ccu_desc;
121extern const struct ccu_desc r40_ccu_desc;
122extern const struct ccu_desc v3s_ccu_desc;
123
124static const struct udevice_id sunxi_clk_ids[] = {
125#ifdef CONFIG_CLK_SUN4I_A10
126 { .compatible = "allwinner,sun4i-a10-ccu",
127 .data = (ulong)&a10_ccu_desc },
128#endif
129#ifdef CONFIG_CLK_SUN5I_A10S
130 { .compatible = "allwinner,sun5i-a10s-ccu",
131 .data = (ulong)&a10s_ccu_desc },
132 { .compatible = "allwinner,sun5i-a13-ccu",
133 .data = (ulong)&a10s_ccu_desc },
134#endif
135#ifdef CONFIG_CLK_SUN6I_A31
136 { .compatible = "allwinner,sun6i-a31-ccu",
137 .data = (ulong)&a31_ccu_desc },
138#endif
139#ifdef CONFIG_CLK_SUN4I_A10
140 { .compatible = "allwinner,sun7i-a20-ccu",
141 .data = (ulong)&a10_ccu_desc },
142#endif
143#ifdef CONFIG_CLK_SUN8I_A23
144 { .compatible = "allwinner,sun8i-a23-ccu",
145 .data = (ulong)&a23_ccu_desc },
146 { .compatible = "allwinner,sun8i-a33-ccu",
147 .data = (ulong)&a23_ccu_desc },
148#endif
149#ifdef CONFIG_CLK_SUN8I_A83T
150 { .compatible = "allwinner,sun8i-a83t-ccu",
151 .data = (ulong)&a83t_ccu_desc },
152#endif
153#ifdef CONFIG_CLK_SUN6I_A31_R
154 { .compatible = "allwinner,sun8i-a83t-r-ccu",
155 .data = (ulong)&a31_r_ccu_desc },
156#endif
157#ifdef CONFIG_CLK_SUN8I_H3
158 { .compatible = "allwinner,sun8i-h3-ccu",
159 .data = (ulong)&h3_ccu_desc },
160#endif
161#ifdef CONFIG_CLK_SUN6I_A31_R
162 { .compatible = "allwinner,sun8i-h3-r-ccu",
163 .data = (ulong)&a31_r_ccu_desc },
164#endif
165#ifdef CONFIG_CLK_SUN8I_R40
166 { .compatible = "allwinner,sun8i-r40-ccu",
167 .data = (ulong)&r40_ccu_desc },
168#endif
169#ifdef CONFIG_CLK_SUN8I_V3S
170 { .compatible = "allwinner,sun8i-v3-ccu",
171 .data = (ulong)&v3s_ccu_desc },
172 { .compatible = "allwinner,sun8i-v3s-ccu",
173 .data = (ulong)&v3s_ccu_desc },
174#endif
175#ifdef CONFIG_CLK_SUN9I_A80
176 { .compatible = "allwinner,sun9i-a80-ccu",
177 .data = (ulong)&a80_ccu_desc },
178 { .compatible = "allwinner,sun9i-a80-mmc-config-clk",
179 .data = (ulong)&a80_mmc_clk_desc },
180#endif
181#ifdef CONFIG_CLK_SUN50I_A64
182 { .compatible = "allwinner,sun50i-a64-ccu",
183 .data = (ulong)&a64_ccu_desc },
184#endif
185#ifdef CONFIG_CLK_SUN6I_A31_R
186 { .compatible = "allwinner,sun50i-a64-r-ccu",
187 .data = (ulong)&a31_r_ccu_desc },
188#endif
189#ifdef CONFIG_CLK_SUN8I_H3
190 { .compatible = "allwinner,sun50i-h5-ccu",
191 .data = (ulong)&h3_ccu_desc },
192#endif
193#ifdef CONFIG_CLK_SUN50I_H6
194 { .compatible = "allwinner,sun50i-h6-ccu",
195 .data = (ulong)&h6_ccu_desc },
196#endif
197#ifdef CONFIG_CLK_SUN50I_H6_R
198 { .compatible = "allwinner,sun50i-h6-r-ccu",
199 .data = (ulong)&h6_r_ccu_desc },
200#endif
201#ifdef CONFIG_CLK_SUN50I_H616
202 { .compatible = "allwinner,sun50i-h616-ccu",
203 .data = (ulong)&h616_ccu_desc },
204#endif
205#ifdef CONFIG_CLK_SUN50I_H6_R
206 { .compatible = "allwinner,sun50i-h616-r-ccu",
207 .data = (ulong)&h6_r_ccu_desc },
208#endif
209#ifdef CONFIG_CLK_SUNIV_F1C100S
210 { .compatible = "allwinner,suniv-f1c100s-ccu",
211 .data = (ulong)&f1c100s_ccu_desc },
212#endif
213 { }
214};
215
216U_BOOT_DRIVER(sunxi_clk) = {
217 .name = "sunxi_clk",
218 .id = UCLASS_CLK,
219 .of_match = sunxi_clk_ids,
220 .bind = sunxi_clk_bind,
221 .probe = sunxi_clk_probe,
Samuel Holland5af97b62022-05-09 00:29:35 -0500222 .of_to_plat = sunxi_clk_of_to_plat,
223 .plat_auto = sizeof(struct ccu_plat),
Samuel Holland46fa23f2022-05-09 00:29:34 -0500224 .ops = &sunxi_clk_ops,
225};