blob: 10fb2b3d60086be65917b3bddef3475b500ac4a7 [file] [log] [blame]
Jon Loeliger8b625112008-03-18 11:12:44 -05001/*
2 * Copyright 2008 Freescale Semiconductor, Inc.
3 *
Tom Rini5b8031c2016-01-14 22:05:13 -05004 * SPDX-License-Identifier: GPL-2.0
Jon Loeliger8b625112008-03-18 11:12:44 -05005 */
6
7#include <common.h>
Jon Loeliger8b625112008-03-18 11:12:44 -05008
York Sun5614e712013-09-30 09:22:09 -07009#include <fsl_ddr_sdram.h>
10#include <fsl_ddr_dimm_params.h>
Jon Loeliger8b625112008-03-18 11:12:44 -050011
Haiying Wangdfb49102008-10-03 12:36:55 -040012void fsl_ddr_board_options(memctl_options_t *popts,
13 dimm_params_t *pdimm,
14 unsigned int ctrl_num)
Jon Loeliger8b625112008-03-18 11:12:44 -050015{
16 /*
17 * Factors to consider for CPO:
18 * - frequency
19 * - ddr1 vs. ddr2
20 */
21 popts->cpo_override = 0;
22
23 /*
24 * Factors to consider for write data delay:
25 * - number of DIMMs
26 *
27 * 1 = 1/4 clock delay
28 * 2 = 1/2 clock delay
29 * 3 = 3/4 clock delay
30 * 4 = 1 clock delay
31 * 5 = 5/4 clock delay
32 * 6 = 3/2 clock delay
33 */
34 popts->write_data_delay = 3;
35
Dave Liub4983e12008-11-21 16:31:43 +080036 /* 2T timing enable */
Priyanka Jain0dd38a32013-09-25 10:41:19 +053037 popts->twot_en = 1;
Dave Liub4983e12008-11-21 16:31:43 +080038
Jon Loeliger8b625112008-03-18 11:12:44 -050039 /*
40 * Factors to consider for half-strength driver enable:
41 * - number of DIMMs installed
42 */
43 popts->half_strength_driver_enable = 0;
44}