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stroesea20b27a2004-12-16 18:05:42 +00001/*
2 * (C) Copyright 2001-2004
3 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
32 * High Level Configuration Options
33 * (easy to change)
34 */
35
36#define CONFIG_405GP 1 /* This is a PPC405 CPU */
37#define CONFIG_4xx 1 /* ...member of PPC4xx family */
38#define CONFIG_APCG405 1 /* ...on a APC405 board */
39
40#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
41#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
42
43#define CONFIG_SYS_CLK_FREQ 33333400 /* external frequency to pll */
44
stroese04e93ec2005-04-13 10:06:07 +000045#define CONFIG_BOARD_TYPES 1 /* support board types */
46
stroesea20b27a2004-12-16 18:05:42 +000047#define CONFIG_BAUDRATE 9600
48#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
49
50#undef CONFIG_BOOTARGS
51#define CONFIG_RAMBOOTCOMMAND \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010052 "setenv bootargs root=/dev/ram rw nfsroot=${serverip}:${rootpath} " \
53 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
stroesea20b27a2004-12-16 18:05:42 +000054 "bootm ffc00000 ffca0000"
55#define CONFIG_NFSBOOTCOMMAND \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010056 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
57 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
stroesea20b27a2004-12-16 18:05:42 +000058 "bootm ffc00000"
59#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
60
61#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
62#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
63
64#define CONFIG_MII 1 /* MII PHY management */
65#define CONFIG_PHY_ADDR 0 /* PHY address */
66#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
67
68#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/
69
Jon Loeliger498ff9a2007-07-05 19:13:52 -050070
71/*
Jon Loeliger11799432007-07-10 09:02:57 -050072 * BOOTP options
73 */
74#define CONFIG_BOOTP_BOOTFILESIZE
75#define CONFIG_BOOTP_BOOTPATH
76#define CONFIG_BOOTP_GATEWAY
77#define CONFIG_BOOTP_HOSTNAME
78
79
80/*
Jon Loeliger498ff9a2007-07-05 19:13:52 -050081 * Command line configuration.
82 */
83#include <config_cmd_default.h>
84
85#define CONFIG_CMD_DHCP
86#define CONFIG_CMD_PCI
87#define CONFIG_CMD_IRQ
88#define CONFIG_CMD_IDE
89#define CONFIG_CMD_FAT
90#define CONFIG_CMD_ELF
91#define CONFIG_CMD_DATE
92#define CONFIG_CMD_I2C
93#define CONFIG_CMD_MII
94#define CONFIG_CMD_PING
Wolfgang Denk5728be32007-08-06 01:01:49 +020095#define CONFIG_CMD_EEPROM
stroesea20b27a2004-12-16 18:05:42 +000096
97#define CONFIG_MAC_PARTITION
98#define CONFIG_DOS_PARTITION
99
100#define CONFIG_SUPPORT_VFAT
101
stroesea20b27a2004-12-16 18:05:42 +0000102#undef CONFIG_WATCHDOG /* watchdog disabled */
103
104#define CONFIG_RTC_MC146818 /* DS1685 is MC146818 compatible*/
105#define CFG_RTC_REG_BASE_ADDR 0xF0000500 /* RTC Base Address */
106
107#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
108
109/*
110 * Miscellaneous configurable options
111 */
112#define CFG_LONGHELP /* undef to save memory */
113#define CFG_PROMPT "=> " /* Monitor Command Prompt */
114
115#undef CFG_HUSH_PARSER /* use "hush" command parser */
116#ifdef CFG_HUSH_PARSER
117#define CFG_PROMPT_HUSH_PS2 "> "
118#endif
119
Jon Loeliger498ff9a2007-07-05 19:13:52 -0500120#if defined(CONFIG_CMD_KGDB)
stroesea20b27a2004-12-16 18:05:42 +0000121#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
122#else
123#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
124#endif
125#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
126#define CFG_MAXARGS 16 /* max number of command args */
127#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
128
129#define CFG_DEVICE_NULLDEV 1 /* include nulldev device */
130
131#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
132
133#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
134#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
135
136#if 1 /* test-only */
137#define CFG_EXT_SERIAL_CLOCK 14745600 /* use external serial clock */
138#else
139#undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */
140#define CFG_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */
141#define CFG_BASE_BAUD 691200
142#endif
143
144/* The following table includes the supported baudrates */
145#define CFG_BAUDRATE_TABLE \
wdenkefe2a4d2004-12-16 21:44:03 +0000146 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
147 57600, 115200, 230400, 460800, 921600 }
stroesea20b27a2004-12-16 18:05:42 +0000148
149#define CFG_LOAD_ADDR 0x100000 /* default load address */
150#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
151
152#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
153
154#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
155
156/* Only interrupt boot if space is pressed */
157/* If a long serial cable is connected but */
158/* other end is dead, garbage will be read */
159#define CONFIG_AUTOBOOT_KEYED 1
160#define CONFIG_AUTOBOOT_PROMPT "Press SPACE to abort autoboot in %d seconds\n"
161#define CONFIG_AUTOBOOT_DELAY_STR "d"
162#define CONFIG_AUTOBOOT_STOP_STR " "
163
164#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
165
166#define CFG_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
167
168/*-----------------------------------------------------------------------
169 * PCI stuff
170 *-----------------------------------------------------------------------
171 */
172#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
173#define PCI_HOST_FORCE 1 /* configure as pci host */
174#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
175
176#define CONFIG_PCI /* include pci support */
177#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
178#define CONFIG_PCI_PNP /* do pci plug-and-play */
wdenkefe2a4d2004-12-16 21:44:03 +0000179 /* resource configuration */
stroesea20b27a2004-12-16 18:05:42 +0000180
181#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
182
183#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
184
185#define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
186#define CFG_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */
187#define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
188#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
189#define CFG_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */
190#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
191#define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */
192#define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
193#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
194
195/*-----------------------------------------------------------------------
196 * IDE/ATA stuff
197 *-----------------------------------------------------------------------
198 */
199#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
200#undef CONFIG_IDE_LED /* no led for ide supported */
201#define CONFIG_IDE_RESET 1 /* reset for ide supported */
202
203#define CFG_IDE_MAXBUS 1 /* max. 1 IDE busses */
204#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
205
206#define CFG_ATA_BASE_ADDR 0xF0100000
207#define CFG_ATA_IDE0_OFFSET 0x0000
208
209#define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
210#define CFG_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */
211#define CFG_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */
212
213/*-----------------------------------------------------------------------
214 * Start addresses for the final memory configuration
215 * (Set up by the startup code)
216 * Please note that CFG_SDRAM_BASE _must_ start at 0
217 */
218#define CFG_SDRAM_BASE 0x00000000
219#define CFG_MONITOR_BASE 0xFFF80000
220#define CFG_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */
221#define CFG_MALLOC_LEN (2*1024*1024) /* Reserve 2MB for malloc() */
222
223/*
224 * For booting Linux, the board info and command line data
225 * have to be in the first 8 MB of memory, since this is
226 * the maximum mapped by the Linux kernel during initialization.
227 */
228#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
229
230/*-----------------------------------------------------------------------
231 * FLASH organization
232 */
233#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
234#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
235#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
236#undef CFG_FLASH_PROTECTION /* don't use hardware protection */
237#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
238#define CFG_FLASH_BASE 0xFE000000 /* test-only...*/
239#define CFG_FLASH_INCREMENT 0x01000000 /* test-only */
240
241#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
242
243#define CFG_JFFS2_FIRST_BANK 0 /* use for JFFS2 */
244#define CFG_JFFS2_NUM_BANKS 1 /* ! second bank contains u-boot */
245
246/*-----------------------------------------------------------------------
247 * Environment Variable setup
248 */
249#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
250#define CFG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */
251#define CFG_ENV_SIZE 0x800 /* 2048 bytes may be used for env vars*/
wdenkefe2a4d2004-12-16 21:44:03 +0000252 /* total size of a CAT24WC16 is 2048 bytes */
stroesea20b27a2004-12-16 18:05:42 +0000253
254#define CFG_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */
255#define CFG_NVRAM_SIZE 242 /* NVRAM size */
256
257/*-----------------------------------------------------------------------
258 * I2C EEPROM (CAT24WC16) for environment
259 */
260#define CONFIG_HARD_I2C /* I2c with hardware support */
261#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
262#define CFG_I2C_SLAVE 0x7F
263
264#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
265#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
266/* mask of address bits that overflow into the "EEPROM chip address" */
267#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07
268#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
269 /* 16 byte page write mode using*/
270 /* last 4 bits of the address */
271#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
272#define CFG_EEPROM_PAGE_WRITE_ENABLE
273
274/*-----------------------------------------------------------------------
275 * Cache Configuration
276 */
Wolfgang Denk0c8721a2005-09-23 11:05:55 +0200277#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
wdenkefe2a4d2004-12-16 21:44:03 +0000278 /* have only 8kB, 16kB is save here */
stroesea20b27a2004-12-16 18:05:42 +0000279#define CFG_CACHELINE_SIZE 32 /* ... */
Jon Loeliger498ff9a2007-07-05 19:13:52 -0500280#if defined(CONFIG_CMD_KGDB)
stroesea20b27a2004-12-16 18:05:42 +0000281#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
282#endif
283
284/*-----------------------------------------------------------------------
285 * External Bus Controller (EBC) Setup
286 */
287#define FLASH0_BA 0xFF000000 /* FLASH 0 Base Address */
288#define FLASH1_BA 0xFE000000 /* FLASH 1 Base Address */
289#define CAN_BA 0xF0000000 /* CAN Base Address */
290#define DUART0_BA 0xF0000400 /* DUART Base Address */
291#define DUART1_BA 0xF0000408 /* DUART Base Address */
292#define RTC_BA 0xF0000500 /* RTC Base Address */
293#define PS2_BA 0xF0000600 /* PS/2 Base Address */
294#define CF_BA 0xF0100000 /* CompactFlash Base Address */
295#define FPGA_BA 0xF0100100 /* FPGA internal Base Address */
296#define FUJI_BA 0xF0100200 /* Fuji internal Base Address */
297#define PCMCIA1_BA 0x20000000 /* PCMCIA Slot 1 Base Address */
298#define PCMCIA2_BA 0x28000000 /* PCMCIA Slot 2 Base Address */
299#define VGA_BA 0xF1000000 /* Epson VGA Base Address */
300
301#define CFG_FPGA_BASE_ADDR FPGA_BA /* FPGA internal Base Address */
302
303/* Memory Bank 0 (Flash Bank 0) initialization */
304#define CFG_EBC_PB0AP 0x92015480
305#define CFG_EBC_PB0CR FLASH0_BA | 0x9A000 /* BAS=0xFF0,BS=16MB,BU=R/W,BW=16bit*/
306
307/* Memory Bank 1 (Flash Bank 1) initialization */
308#define CFG_EBC_PB1AP 0x92015480
309#define CFG_EBC_PB1CR FLASH1_BA | 0x9A000 /* BAS=0xFE0,BS=16MB,BU=R/W,BW=16bit*/
310
311/* Memory Bank 2 (CAN0, 1, RTC, Duart) initialization */
312#define CFG_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
313#define CFG_EBC_PB2CR CAN_BA | 0x18000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
314
315/* Memory Bank 3 (CompactFlash IDE, FPGA internal) initialization */
316#define CFG_EBC_PB3AP 0x010059C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
317#define CFG_EBC_PB3CR CF_BA | 0x1A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
318
319/* Memory Bank 4 (PCMCIA Slot 1) initialization */
320#define CFG_EBC_PB4AP 0x050007C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
321#define CFG_EBC_PB4CR PCMCIA1_BA | 0xFA000 /*BAS=0x200,BS=128MB,BU=R/W,BW=16bit*/
322
323/* Memory Bank 5 (Epson VGA) initialization */
324#define CFG_EBC_PB5AP 0x03805380 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=0 */
325#define CFG_EBC_PB5CR VGA_BA | 0x5A000 /* BAS=0xF10,BS=4MB,BU=R/W,BW=16bit */
326
327/* Memory Bank 6 (PCMCIA Slot 2) initialization */
328#define CFG_EBC_PB6AP 0x050007C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
329#define CFG_EBC_PB6CR PCMCIA2_BA | 0xFA000 /*BAS=0x280,BS=128MB,BU=R/W,BW=16bit*/
330
331/*-----------------------------------------------------------------------
332 * FPGA stuff
333 */
334
335/* FPGA internal regs */
336#define CFG_FPGA_CTRL 0x008
stroese04e93ec2005-04-13 10:06:07 +0000337#define CFG_FPGA_CTRL2 0x00a
stroesea20b27a2004-12-16 18:05:42 +0000338
339/* FPGA Control Reg */
340#define CFG_FPGA_CTRL_CF_RESET 0x0001
341#define CFG_FPGA_CTRL_WDI 0x0002
342#define CFG_FPGA_CTRL_PS2_RESET 0x0020
343
344#define CFG_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */
345#define CFG_FPGA_MAX_SIZE 80*1024 /* 80kByte is enough for XC2S50 */
346
347/* FPGA program pin configuration */
348#define CFG_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */
349#define CFG_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */
350#define CFG_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */
351#define CFG_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */
352#define CFG_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */
353
354/*-----------------------------------------------------------------------
355 * LCD Setup
356 */
357
358#define CFG_LCD_BIG_MEM 0xF1200000 /* Epson S1D13806 Mem Base Address */
359#define CFG_LCD_BIG_REG 0xF1000000 /* Epson S1D13806 Reg Base Address */
360
361#define CONFIG_LCD_BIG 2 /* Epson S1D13806 used */
362
363/* Image information... */
364#define CONFIG_LCD_USED CONFIG_LCD_BIG
stroese04e93ec2005-04-13 10:06:07 +0000365#define CFG_LCD_HEADER_NAME "../common/s1d13806_640_480_16bpp.h"
stroesea20b27a2004-12-16 18:05:42 +0000366#define CFG_LCD_LOGO_NAME "logo_640_480_24bpp.c"
367
368#define CFG_LCD_MEM CFG_LCD_BIG_MEM
369#define CFG_LCD_REG CFG_LCD_BIG_REG
370
Stefan Roesec29ab9d2005-10-08 10:19:07 +0200371#define CFG_VIDEO_LOGO_MAX_SIZE (1 << 20)
stroesea20b27a2004-12-16 18:05:42 +0000372
373/*-----------------------------------------------------------------------
374 * Definitions for initial stack pointer and data area (in data cache)
375 */
376
377/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
378#define CFG_TEMP_STACK_OCM 1
379
380/* On Chip Memory location */
381#define CFG_OCM_DATA_ADDR 0xF8000000
382#define CFG_OCM_DATA_SIZE 0x1000
383
384#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */
385#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */
386#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
387#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
388#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
389
390/*
391 * Internal Definitions
392 *
393 * Boot Flags
394 */
395#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
396#define BOOTFLAG_WARM 0x02 /* Software reboot */
397
398#endif /* __CONFIG_H */