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wdenkdc7c9a12003-03-26 06:55:25 +00001/*
2 * Rick Bronson <rick@efn.org>
3 *
Jean-Christophe PLAGNIOL-VILLARD4a129a52008-11-30 19:36:53 +01004 * Configuration settings for the AT91RM9200DK board.
wdenkdc7c9a12003-03-26 06:55:25 +00005 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25#ifndef __CONFIG_H
26#define __CONFIG_H
27
28/* ARM asynchronous clock */
wdenk8b07a112004-07-10 21:45:47 +000029#define AT91C_MAIN_CLOCK 179712000 /* from 18.432 MHz crystal (18432000 / 4 * 39) */
30#define AT91C_MASTER_CLOCK 59904000 /* peripheral clock (AT91C_MASTER_CLOCK / 3) */
31/* #define AT91C_MASTER_CLOCK 44928000 */ /* peripheral clock (AT91C_MASTER_CLOCK / 4) */
wdenkdc7c9a12003-03-26 06:55:25 +000032
wdenkd9df1f42004-03-15 09:00:01 +000033#define AT91_SLOW_CLOCK 32768 /* slow clock */
34
wdenka85f9f22005-04-06 13:52:31 +000035#define CONFIG_ARM920T 1 /* This is an ARM920T Core */
36#define CONFIG_AT91RM9200 1 /* It's an Atmel AT91RM9200 SoC */
37#define CONFIG_AT91RM9200DK 1 /* on an AT91RM9200DK Board */
38#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
39#define USE_920T_MMU 1
40
wdenk8b07a112004-07-10 21:45:47 +000041#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
wdenkdc7c9a12003-03-26 06:55:25 +000042#define CONFIG_SETUP_MEMORY_TAGS 1
wdenk8b07a112004-07-10 21:45:47 +000043#define CONFIG_INITRD_TAG 1
wdenk2abbe072003-06-16 23:50:08 +000044
wdenk8aa1a2d2005-04-04 12:44:11 +000045#ifndef CONFIG_SKIP_LOWLEVEL_INIT
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020046#define CONFIG_SYS_USE_MAIN_OSCILLATOR 1
wdenkef2807c2005-03-31 23:44:33 +000047/* flash */
Jean-Christophe PLAGNIOL-VILLARDd481c802009-01-03 17:22:25 +010048#define CONFIG_SYS_MC_PUIA_VAL 0x00000000
49#define CONFIG_SYS_MC_PUP_VAL 0x00000000
50#define CONFIG_SYS_MC_PUER_VAL 0x00000000
51#define CONFIG_SYS_MC_ASR_VAL 0x00000000
52#define CONFIG_SYS_MC_AASR_VAL 0x00000000
53#define CONFIG_SYS_EBI_CFGR_VAL 0x00000000
54#define CONFIG_SYS_SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */
wdenkef2807c2005-03-31 23:44:33 +000055
56/* clocks */
Jean-Christophe PLAGNIOL-VILLARDd481c802009-01-03 17:22:25 +010057#define CONFIG_SYS_PLLAR_VAL 0x20263E04 /* 179.712000 MHz for PCK */
58#define CONFIG_SYS_PLLBR_VAL 0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */
59#define CONFIG_SYS_MCKR_VAL 0x00000202 /* PCK/3 = MCK Master Clock = 59.904000MHz from PLLA */
wdenkef2807c2005-03-31 23:44:33 +000060
61/* sdram */
Jean-Christophe PLAGNIOL-VILLARDd481c802009-01-03 17:22:25 +010062#define CONFIG_SYS_PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */
63#define CONFIG_SYS_PIOC_BSR_VAL 0x00000000
64#define CONFIG_SYS_PIOC_PDR_VAL 0xFFFF0000
65#define CONFIG_SYS_EBI_CSA_VAL 0x00000002 /* CS1=CONFIG_SYS_SDRAM */
66#define CONFIG_SYS_SDRC_CR_VAL 0x2188c155 /* set up the CONFIG_SYS_SDRAM */
67#define CONFIG_SYS_SDRAM 0x20000000 /* address of the CONFIG_SYS_SDRAM */
68#define CONFIG_SYS_SDRAM1 0x20000080 /* address of the CONFIG_SYS_SDRAM */
69#define CONFIG_SYS_SDRAM_VAL 0x00000000 /* value written to CONFIG_SYS_SDRAM */
70#define CONFIG_SYS_SDRC_MR_VAL 0x00000002 /* Precharge All */
71#define CONFIG_SYS_SDRC_MR_VAL1 0x00000004 /* refresh */
72#define CONFIG_SYS_SDRC_MR_VAL2 0x00000003 /* Load Mode Register */
73#define CONFIG_SYS_SDRC_MR_VAL3 0x00000000 /* Normal Mode */
74#define CONFIG_SYS_SDRC_TR_VAL 0x000002E0 /* Write refresh rate */
Jens Scharsig80523522008-11-18 10:48:46 +010075#else
76#define CONFIG_SKIP_RELOCATE_UBOOT
wdenk8aa1a2d2005-04-04 12:44:11 +000077#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
wdenkdc7c9a12003-03-26 06:55:25 +000078/*
79 * Size of malloc() pool
80 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020081#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
82#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
wdenka8c7c702003-12-06 19:49:23 +000083
wdenkdc7c9a12003-03-26 06:55:25 +000084#define CONFIG_BAUDRATE 115200
wdenka8c7c702003-12-06 19:49:23 +000085
wdenkdc7c9a12003-03-26 06:55:25 +000086/*
87 * Hardware drivers
88 */
89
wdenk9d5028c2004-11-21 00:06:33 +000090/* define one of these to choose the DBGU, USART0 or USART1 as console */
Jean-Christophe PLAGNIOL-VILLARDbeebd852009-03-27 23:26:43 +010091#define CONFIG_AT91RM9200_USART
wdenk4734cb72004-09-21 23:33:32 +000092#define CONFIG_DBGU
wdenk9d5028c2004-11-21 00:06:33 +000093#undef CONFIG_USART0
wdenk4734cb72004-09-21 23:33:32 +000094#undef CONFIG_USART1
95
wdenkdc7c9a12003-03-26 06:55:25 +000096#undef CONFIG_HWFLOW /* don't include RTS/CTS flow control support */
97
98#undef CONFIG_MODEM_SUPPORT /* disable modem initialization stuff */
99
wdenk8bde7f72003-06-27 21:31:46 +0000100#define CONFIG_BOOTDELAY 3
wdenk8b07a112004-07-10 21:45:47 +0000101/* #define CONFIG_ENV_OVERWRITE 1 */
wdenk2abbe072003-06-16 23:50:08 +0000102
wdenk8bde7f72003-06-27 21:31:46 +0000103
Jon Loeliger0b361c92007-07-04 22:31:42 -0500104/*
Jon Loeliger80ff4f92007-07-10 09:29:01 -0500105 * BOOTP options
106 */
107#define CONFIG_BOOTP_BOOTFILESIZE
108#define CONFIG_BOOTP_BOOTPATH
109#define CONFIG_BOOTP_GATEWAY
110#define CONFIG_BOOTP_HOSTNAME
111
112
113/*
Jon Loeliger0b361c92007-07-04 22:31:42 -0500114 * Command line configuration.
115 */
116#include <config_cmd_default.h>
117
Jon Loeliger0b361c92007-07-04 22:31:42 -0500118#define CONFIG_CMD_DHCP
Wolfgang Denk3c959602008-07-31 10:12:09 +0200119#define CONFIG_CMD_MII
120#define CONFIG_CMD_NAND
Jon Loeliger0b361c92007-07-04 22:31:42 -0500121
Jean-Christophe PLAGNIOL-VILLARDcc4a0ce2008-08-13 01:40:43 +0200122#define CONFIG_NAND_LEGACY
wdenkdc7c9a12003-03-26 06:55:25 +0000123
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200124#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
wdenkdc7c9a12003-03-26 06:55:25 +0000125#define SECTORSIZE 512
126
127#define ADDR_COLUMN 1
128#define ADDR_PAGE 2
129#define ADDR_COLUMN_PAGE 3
130
wdenk8b07a112004-07-10 21:45:47 +0000131#define NAND_ChipID_UNKNOWN 0x00
wdenkdc7c9a12003-03-26 06:55:25 +0000132#define NAND_MAX_FLOORS 1
wdenkdc7c9a12003-03-26 06:55:25 +0000133
wdenk8b07a112004-07-10 21:45:47 +0000134#define AT91_SMART_MEDIA_ALE (1 << 22) /* our ALE is AD22 */
135#define AT91_SMART_MEDIA_CLE (1 << 21) /* our CLE is AD21 */
wdenkdc7c9a12003-03-26 06:55:25 +0000136
Wolfgang Denk3c959602008-07-31 10:12:09 +0200137#include <asm/arch/AT91RM9200.h> /* needed for port definitions */
wdenkdc7c9a12003-03-26 06:55:25 +0000138#define NAND_DISABLE_CE(nand) do { *AT91C_PIOC_SODR = AT91C_PIO_PC0;} while(0)
139#define NAND_ENABLE_CE(nand) do { *AT91C_PIOC_CODR = AT91C_PIO_PC0;} while(0)
140
141#define NAND_WAIT_READY(nand) while (!(*AT91C_PIOC_PDSR & AT91C_PIO_PC2))
142
143#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | AT91_SMART_MEDIA_CLE) = (__u8)(d); } while(0)
144#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | AT91_SMART_MEDIA_ALE) = (__u8)(d); } while(0)
145#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
146#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
147/* the following are NOP's in our implementation */
148#define NAND_CTL_CLRALE(nandptr)
149#define NAND_CTL_SETALE(nandptr)
150#define NAND_CTL_CLRCLE(nandptr)
151#define NAND_CTL_SETCLE(nandptr)
152
153#define CONFIG_NR_DRAM_BANKS 1
154#define PHYS_SDRAM 0x20000000
155#define PHYS_SDRAM_SIZE 0x2000000 /* 32 megs */
156
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200157#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
158#define CONFIG_SYS_MEMTEST_END CONFIG_SYS_MEMTEST_START + PHYS_SDRAM_SIZE - 262144
wdenkdc7c9a12003-03-26 06:55:25 +0000159
160#define CONFIG_DRIVER_ETHER
wdenk8b07a112004-07-10 21:45:47 +0000161#define CONFIG_NET_RETRY_COUNT 20
wdenk074cff02004-02-24 00:16:43 +0000162#define CONFIG_AT91C_USE_RMII
wdenk2abbe072003-06-16 23:50:08 +0000163
Peter Pearsed4fc6012007-08-14 10:10:52 +0100164/* AC Characteristics */
165/* DLYBS = tCSS = 250ns min and DLYBCT = tCSH = 250ns */
166#define DATAFLASH_TCSS (0xC << 16)
167#define DATAFLASH_TCHS (0x1 << 24)
168
wdenk8b07a112004-07-10 21:45:47 +0000169#define CONFIG_HAS_DATAFLASH 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200170#define CONFIG_SYS_SPI_WRITE_TOUT (5*CONFIG_SYS_HZ)
171#define CONFIG_SYS_MAX_DATAFLASH_BANKS 2
172#define CONFIG_SYS_MAX_DATAFLASH_PAGES 16384
173#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* Logical adress for CS0 */
174#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3 0xD0000000 /* Logical adress for CS3 */
wdenkdc7c9a12003-03-26 06:55:25 +0000175
wdenk8b07a112004-07-10 21:45:47 +0000176#define PHYS_FLASH_1 0x10000000
177#define PHYS_FLASH_SIZE 0x200000 /* 2 megs main flash */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200178#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
179#define CONFIG_SYS_MAX_FLASH_BANKS 1
180#define CONFIG_SYS_MAX_FLASH_SECT 256
181#define CONFIG_SYS_FLASH_ERASE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
182#define CONFIG_SYS_FLASH_WRITE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Write */
wdenk5779d8d2003-12-06 23:55:10 +0000183
Jean-Christophe PLAGNIOL-VILLARD057c8492008-09-10 22:47:58 +0200184#undef CONFIG_ENV_IS_IN_DATAFLASH
wdenk5779d8d2003-12-06 23:55:10 +0000185
Jean-Christophe PLAGNIOL-VILLARD057c8492008-09-10 22:47:58 +0200186#ifdef CONFIG_ENV_IS_IN_DATAFLASH
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200187#define CONFIG_ENV_OFFSET 0x20000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200188#define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200189#define CONFIG_ENV_SIZE 0x2000 /* 0x8000 */
wdenk5779d8d2003-12-06 23:55:10 +0000190#else
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200191#define CONFIG_ENV_IS_IN_FLASH 1
wdenk8aa1a2d2005-04-04 12:44:11 +0000192#ifdef CONFIG_SKIP_LOWLEVEL_INIT
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200193#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0xe000) /* between boot.bin and u-boot.bin.gz */
194#define CONFIG_ENV_SIZE 0x2000 /* 0x8000 */
Ladislav Michl481f28b2007-12-06 22:59:16 +0100195#else
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200196#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x60000) /* after u-boot.bin */
197#define CONFIG_ENV_SIZE 0x10000 /* sectors are 64K here */
wdenk8aa1a2d2005-04-04 12:44:11 +0000198#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
Jean-Christophe PLAGNIOL-VILLARD057c8492008-09-10 22:47:58 +0200199#endif /* CONFIG_ENV_IS_IN_DATAFLASH */
wdenk5779d8d2003-12-06 23:55:10 +0000200
201
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200202#define CONFIG_SYS_LOAD_ADDR 0x21000000 /* default load address */
wdenkdc7c9a12003-03-26 06:55:25 +0000203
wdenk8aa1a2d2005-04-04 12:44:11 +0000204#ifdef CONFIG_SKIP_LOWLEVEL_INIT
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200205#define CONFIG_SYS_BOOT_SIZE 0x6000 /* 24 KBytes */
206#define CONFIG_SYS_U_BOOT_BASE (PHYS_FLASH_1 + 0x10000)
207#define CONFIG_SYS_U_BOOT_SIZE 0x10000 /* 64 KBytes */
Ladislav Michl481f28b2007-12-06 22:59:16 +0100208#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200209#define CONFIG_SYS_BOOT_SIZE 0x00 /* 0 KBytes */
210#define CONFIG_SYS_U_BOOT_BASE PHYS_FLASH_1
211#define CONFIG_SYS_U_BOOT_SIZE 0x60000 /* 384 KBytes */
wdenk8aa1a2d2005-04-04 12:44:11 +0000212#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
wdenk2abbe072003-06-16 23:50:08 +0000213
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200214#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 19200, 38400, 57600, 9600 }
wdenkdc7c9a12003-03-26 06:55:25 +0000215
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200216#define CONFIG_SYS_PROMPT "U-Boot> " /* Monitor Command Prompt */
217#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
218#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
219#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
wdenkdc7c9a12003-03-26 06:55:25 +0000220
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200221#define CONFIG_SYS_HZ 1000
222#define CONFIG_SYS_HZ_CLOCK AT91C_MASTER_CLOCK/2 /* AT91C_TC0_CMR is implicitly set to */
Ladislav Michl2c5260f2007-12-06 23:24:57 +0100223 /* AT91C_TC_TIMER_DIV1_CLOCK */
wdenkdc7c9a12003-03-26 06:55:25 +0000224
225#define CONFIG_STACKSIZE (32*1024) /* regular stack */
226
227#ifdef CONFIG_USE_IRQ
228#error CONFIG_USE_IRQ not supported
229#endif
230
231#endif