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stroesea20b27a2004-12-16 18:05:42 +00001/*
2 * (C) Copyright 2004
3 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
32 * High Level Configuration Options
33 * (easy to change)
34 */
35
36#define CONFIG_405EP 1 /* This is a PPC405 CPU */
37#define CONFIG_4xx 1 /* ...member of PPC4xx family */
38#define CONFIG_G2000 1 /* ...on a PLU405 board */
39
Wolfgang Denk2ae18242010-10-06 09:05:45 +020040#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
41
stroesea20b27a2004-12-16 18:05:42 +000042#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
43#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
44
45#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
46
47#if 0 /* test-only */
48#define CONFIG_BAUDRATE 115200
49#else
50#define CONFIG_BAUDRATE 9600
51#endif
52
53#define CONFIG_PREBOOT
54
55#undef CONFIG_BOOTARGS
56
57#define CONFIG_EXTRA_ENV_SETTINGS \
58 "nfsargs=setenv bootargs root=/dev/nfs rw " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010059 "nfsroot=${serverip}:${rootpath}\0" \
stroesea20b27a2004-12-16 18:05:42 +000060 "ramargs=setenv bootargs root=/dev/ram rw\0" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010061 "addip=setenv bootargs ${bootargs} " \
62 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
63 ":${hostname}:${netdev}:off\0" \
64 "addmisc=setenv bootargs ${bootargs} " \
65 "console=ttyS0,${baudrate} " \
stroesea20b27a2004-12-16 18:05:42 +000066 "panic=1\0" \
67 "flash_nfs=run nfsargs addip addmisc;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010068 "bootm ${kernel_addr}\0" \
stroesea20b27a2004-12-16 18:05:42 +000069 "flash_self=run ramargs addip addmisc;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010070 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
71 "net_nfs=tftp 200000 ${bootfile};" \
stroesea20b27a2004-12-16 18:05:42 +000072 "run nfsargs addip addmisc;bootm\0" \
73 "rootpath=/opt/eldk/ppc_4xx\0" \
74 "bootfile=/tftpboot/g2000/pImage\0" \
75 "kernel_addr=ff800000\0" \
76 "ramdisk_addr=ff900000\0" \
77 "pciconfighost=yes\0" \
78 ""
79#define CONFIG_BOOTCOMMAND "run net_nfs"
80
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020081#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
stroesea20b27a2004-12-16 18:05:42 +000082
83#define CONFIG_NET_MULTI 1
84
Ben Warren96e21f82008-10-27 23:50:15 -070085#define CONFIG_PPC4xx_EMAC
stroesea20b27a2004-12-16 18:05:42 +000086#define CONFIG_MII 1 /* MII PHY management */
87#define CONFIG_PHY_ADDR 0 /* PHY address */
88#define CONFIG_PHY1_ADDR 1 /* PHY address */
89
90#if 0 /* test-only */
91#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/
92#endif
93
stroesea20b27a2004-12-16 18:05:42 +000094
Jon Loeliger60a08762007-07-07 21:04:26 -050095/*
Jon Loeliger11799432007-07-10 09:02:57 -050096 * BOOTP options
97 */
98#define CONFIG_BOOTP_BOOTFILESIZE
99#define CONFIG_BOOTP_BOOTPATH
100#define CONFIG_BOOTP_GATEWAY
101#define CONFIG_BOOTP_HOSTNAME
102
103
104/*
Jon Loeliger60a08762007-07-07 21:04:26 -0500105 * Command line configuration.
106 */
107#include <config_cmd_default.h>
108
109#define CONFIG_CMD_DHCP
110#define CONFIG_CMD_PCI
111#define CONFIG_CMD_IRQ
112#define CONFIG_CMD_ELF
113#define CONFIG_CMD_DATE
114#define CONFIG_CMD_I2C
115#define CONFIG_CMD_MII
116#define CONFIG_CMD_PING
117#define CONFIG_CMD_BSP
118#define CONFIG_CMD_EEPROM
119
stroesea20b27a2004-12-16 18:05:42 +0000120
121#undef CONFIG_WATCHDOG /* watchdog disabled */
122
123#if 0 /* test-only */
124#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
125#endif
126
127/*
128 * Miscellaneous configurable options
129 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200130#define CONFIG_SYS_LONGHELP /* undef to save memory */
131#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
stroesea20b27a2004-12-16 18:05:42 +0000132
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200133#undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
134#ifdef CONFIG_SYS_HUSH_PARSER
135#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
stroesea20b27a2004-12-16 18:05:42 +0000136#endif
137
Jon Loeliger60a08762007-07-07 21:04:26 -0500138#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200139#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
stroesea20b27a2004-12-16 18:05:42 +0000140#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200141#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
stroesea20b27a2004-12-16 18:05:42 +0000142#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200143#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
144#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
145#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
stroesea20b27a2004-12-16 18:05:42 +0000146
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200147#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */
stroesea20b27a2004-12-16 18:05:42 +0000148
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200149#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
stroesea20b27a2004-12-16 18:05:42 +0000150
151#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
152
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200153#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
154#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
stroesea20b27a2004-12-16 18:05:42 +0000155
Stefan Roese550650d2010-09-20 16:05:31 +0200156#define CONFIG_CONS_INDEX 1
157#define CONFIG_SYS_NS16550
158#define CONFIG_SYS_NS16550_SERIAL
159#define CONFIG_SYS_NS16550_REG_SIZE 1
160#define CONFIG_SYS_NS16550_CLK get_serial_clock()
161
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200162#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200163#define CONFIG_SYS_BASE_BAUD 691200
stroesea20b27a2004-12-16 18:05:42 +0000164
165/* The following table includes the supported baudrates */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200166#define CONFIG_SYS_BAUDRATE_TABLE \
stroesea20b27a2004-12-16 18:05:42 +0000167 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
168 57600, 115200, 230400, 460800, 921600 }
169
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200170#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
171#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
stroesea20b27a2004-12-16 18:05:42 +0000172
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200173#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
stroesea20b27a2004-12-16 18:05:42 +0000174
175#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
176#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
177
178#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
179
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200180#define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
stroesea20b27a2004-12-16 18:05:42 +0000181
182/*----------------------------------------------------------------------------*/
183/* adding Ethernet setting: FTS OUI 00:11:0B */
184/*----------------------------------------------------------------------------*/
185#define CONFIG_ETHADDR 00:11:0B:00:00:01
wdenke2ffd592004-12-31 09:32:47 +0000186#define CONFIG_HAS_ETH1
stroesea20b27a2004-12-16 18:05:42 +0000187#define CONFIG_ETH1ADDR 00:11:0B:00:00:02
188#define CONFIG_IPADDR 10.48.8.178
189#define CONFIG_IP1ADDR 10.48.8.188
190#define CONFIG_NETMASK 255.255.255.128
191#define CONFIG_SERVERIP 10.48.8.138
192
193/*-----------------------------------------------------------------------
194 * RTC stuff
195 *-----------------------------------------------------------------------
196 */
197#define CONFIG_RTC_DS1337
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200198#define CONFIG_SYS_I2C_RTC_ADDR 0x68
stroesea20b27a2004-12-16 18:05:42 +0000199
200#if 0 /* test-only */
201/*-----------------------------------------------------------------------
202 * NAND-FLASH stuff
203 *-----------------------------------------------------------------------
204 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200205#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
stroesea20b27a2004-12-16 18:05:42 +0000206
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200207#define CONFIG_SYS_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
208#define CONFIG_SYS_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
209#define CONFIG_SYS_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
210#define CONFIG_SYS_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
stroesea20b27a2004-12-16 18:05:42 +0000211
stroesea20b27a2004-12-16 18:05:42 +0000212#endif
213
214/*-----------------------------------------------------------------------
215 * PCI stuff
216 *-----------------------------------------------------------------------
217 */
218#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
219#define PCI_HOST_FORCE 1 /* configure as pci host */
220#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
221
222#define CONFIG_PCI /* include pci support */
223#define CONFIG_PCI_HOST PCI_HOST_HOST /* select pci host function */
224#define CONFIG_PCI_PNP /* do pci plug-and-play */
225 /* resource configuration */
226
227#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
228
229#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
230
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200231#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
232#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */
233#define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
234#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */
235#define CONFIG_SYS_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */
236#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
237#define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */
238#define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
239#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
stroesea20b27a2004-12-16 18:05:42 +0000240
241/*
242 * For booting Linux, the board info and command line data
243 * have to be in the first 8 MB of memory, since this is
244 * the maximum mapped by the Linux kernel during initialization.
245 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200246#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
stroesea20b27a2004-12-16 18:05:42 +0000247
248/*-----------------------------------------------------------------------
249 * FLASH organization
250 */
251#if 0 /* APC405 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200252#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
253#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
254#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
255#undef CONFIG_SYS_FLASH_PROTECTION /* don't use hardware protection */
256#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
257#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* test-only...*/
258#define CONFIG_SYS_FLASH_INCREMENT 0x01000000 /* test-only */
stroesea20b27a2004-12-16 18:05:42 +0000259#else /* G2000 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200260#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
261#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
262#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
263#undef CONFIG_SYS_FLASH_PROTECTION /* don't use hardware protection */
264#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
265#define CONFIG_SYS_FLASH_BASE 0xFF800000 /* test-only...*/
266#define CONFIG_SYS_FLASH_INCREMENT 0x01000000 /* test-only */
stroesea20b27a2004-12-16 18:05:42 +0000267#endif
268
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200269#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
stroesea20b27a2004-12-16 18:05:42 +0000270
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200271#define CONFIG_SYS_JFFS2_FIRST_BANK 0 /* use for JFFS2 */
272#define CONFIG_SYS_JFFS2_NUM_BANKS 1 /* ! second bank contains u-boot */
stroesea20b27a2004-12-16 18:05:42 +0000273
274/*-----------------------------------------------------------------------
275 * Start addresses for the final memory configuration
276 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200277 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
stroesea20b27a2004-12-16 18:05:42 +0000278 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200279#define CONFIG_SYS_SDRAM_BASE 0x00000000
280#define CONFIG_SYS_MONITOR_BASE 0xFFFC0000
281#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
282#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
stroesea20b27a2004-12-16 18:05:42 +0000283
284/*-----------------------------------------------------------------------
285 * Environment Variable setup
286 */
287#if 1 /* test-only */
Jean-Christophe PLAGNIOL-VILLARDbb1f8b42008-09-05 09:19:30 +0200288#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200289#define CONFIG_ENV_OFFSET 0x100 /* environment starts at the beginning of the EEPROM */
290#define CONFIG_ENV_SIZE 0x700 /* 2048 bytes may be used for env vars*/
stroesea20b27a2004-12-16 18:05:42 +0000291 /* total size of a CAT24WC16 is 2048 bytes */
292
293#else /* DEFAULT: environment in flash, using redundand flash sectors */
294
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200295#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200296#define CONFIG_ENV_ADDR 0xFFFA0000 /* environment starts before u-boot */
297#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128k bytes may be used for env vars*/
stroesea20b27a2004-12-16 18:05:42 +0000298
299#endif
300
301/*-----------------------------------------------------------------------
302 * I2C EEPROM (CAT24WC16) for environment
303 */
304#define CONFIG_HARD_I2C /* I2c with hardware support */
Stefan Roesed0b0dca2010-04-01 14:37:24 +0200305#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200306#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
307#define CONFIG_SYS_I2C_SLAVE 0x7F
stroesea20b27a2004-12-16 18:05:42 +0000308
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200309#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT24WC08 */
stroesea20b27a2004-12-16 18:05:42 +0000310/* CAT24WC08/16... */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200311#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
stroesea20b27a2004-12-16 18:05:42 +0000312/* mask of address bits that overflow into the "EEPROM chip address" */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200313#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
314#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
stroesea20b27a2004-12-16 18:05:42 +0000315 /* 16 byte page write mode using*/
316 /* last 4 bits of the address */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200317#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
stroesea20b27a2004-12-16 18:05:42 +0000318
319/*-----------------------------------------------------------------------
stroesea20b27a2004-12-16 18:05:42 +0000320 * External Bus Controller (EBC) Setup
321 */
322
323/* Memory Bank 0 (Intel Strata Flash) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200324#define CONFIG_SYS_EBC_PB0AP 0x92015480
325#define CONFIG_SYS_EBC_PB0CR 0xFF87A000 /* BAS=0xFF8,BS=08MB,BU=R/W,BW=16bit*/
stroesea20b27a2004-12-16 18:05:42 +0000326
327/* Memory Bank 1 ( Power TAU) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200328/* #define CONFIG_SYS_EBC_PB1AP 0x04041000 */
329/* #define CONFIG_SYS_EBC_PB1CR 0xF0018000 */ /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
330#define CONFIG_SYS_EBC_PB1AP 0x00000000
331#define CONFIG_SYS_EBC_PB1CR 0x00000000
stroesea20b27a2004-12-16 18:05:42 +0000332
333/* Memory Bank 2 (Intel Flash) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200334#define CONFIG_SYS_EBC_PB2AP 0x00000000
335#define CONFIG_SYS_EBC_PB2CR 0x00000000
stroesea20b27a2004-12-16 18:05:42 +0000336
337/* Memory Bank 3 (NAND) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200338#define CONFIG_SYS_EBC_PB3AP 0x92015480
339#define CONFIG_SYS_EBC_PB3CR 0xF40B8000 /*addr 0xF40, BS=32M,BU=R/W, BW=8bit */
stroesea20b27a2004-12-16 18:05:42 +0000340
341/* Memory Bank 4 (FPGA regs) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200342#define CONFIG_SYS_EBC_PB4AP 0x00000000
343#define CONFIG_SYS_EBC_PB4CR 0x00000000 /* leave it blank */
stroesea20b27a2004-12-16 18:05:42 +0000344
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200345#define CONFIG_SYS_NAND_BASE 0xF4000000
stroesea20b27a2004-12-16 18:05:42 +0000346
347/*-----------------------------------------------------------------------
348 * Definitions for initial stack pointer and data area (in data cache)
349 */
350/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200351#define CONFIG_SYS_TEMP_STACK_OCM 1
stroesea20b27a2004-12-16 18:05:42 +0000352
353/* On Chip Memory location */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200354#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
355#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
356#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200357#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
stroesea20b27a2004-12-16 18:05:42 +0000358
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200359#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200360#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
stroesea20b27a2004-12-16 18:05:42 +0000361
362/*-----------------------------------------------------------------------
363 * Definitions for GPIO setup (PPC405EP specific)
364 *
365 * GPIO0[0] - External Bus Controller BLAST output
366 * GPIO0[1-9] - Instruction trace outputs
367 * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
368 * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs
369 * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
370 * GPIO0[24-27] - UART0 control signal inputs/outputs
371 * GPIO0[28-29] - UART1 data signal input/output
372 * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
373 *
374 * following GPIO setting changed for G20000, 080304
375 */
Stefan Roeseafabb492010-09-12 06:21:37 +0200376#define CONFIG_SYS_GPIO0_OSRL 0x40005555
377#define CONFIG_SYS_GPIO0_OSRH 0x40000110
378#define CONFIG_SYS_GPIO0_ISR1L 0x00000000
379#define CONFIG_SYS_GPIO0_ISR1H 0x15555445
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200380#define CONFIG_SYS_GPIO0_TSRL 0x00000000
Stefan Roeseafabb492010-09-12 06:21:37 +0200381#define CONFIG_SYS_GPIO0_TSRH 0x00000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200382#define CONFIG_SYS_GPIO0_TCR 0xF7FF8014
stroesea20b27a2004-12-16 18:05:42 +0000383
384/*
stroesea20b27a2004-12-16 18:05:42 +0000385 * Default speed selection (cpu_plb_opb_ebc) in mhz.
386 * This value will be set if iic boot eprom is disabled.
387 */
388#if 1
389#define PLLMR0_DEFAULT PLLMR0_266_66_33_33
390#define PLLMR1_DEFAULT PLLMR1_266_66_33_33
391#endif
392#if 0
393#define PLLMR0_DEFAULT PLLMR0_266_133_66_33
394#define PLLMR1_DEFAULT PLLMR1_266_133_66_33
395#endif
396#if 0
397#define PLLMR0_DEFAULT PLLMR0_200_100_50_33
398#define PLLMR1_DEFAULT PLLMR1_200_100_50_33
399#endif
400#if 0
401#define PLLMR0_DEFAULT PLLMR0_133_66_66_33
402#define PLLMR1_DEFAULT PLLMR1_133_66_66_33
403#endif
404
405#endif /* __CONFIG_H */