blob: a11897552806ea4836b32979aa09aecd1d9b1166 [file] [log] [blame]
Timur Tabic59e1b42010-06-14 15:28:24 -05001/*
Kumar Gala7c57f3e2011-01-11 00:52:35 -06002 * Copyright 2010-2011 Freescale Semiconductor, Inc.
Timur Tabic59e1b42010-06-14 15:28:24 -05003 * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
4 * Timur Tabi <timur@freescale.com>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the Free
8 * Software Foundation; either version 2 of the License, or (at your option)
9 * any later version.
10 */
11
12#ifndef __CONFIG_H
13#define __CONFIG_H
14
15#include "../board/freescale/common/ics307_clk.h"
16
Jiang Yutang9899ac12011-01-24 18:21:15 +080017#ifdef CONFIG_36BIT
18#define CONFIG_PHYS_64BIT
19#endif
20
Timur Tabic59e1b42010-06-14 15:28:24 -050021/* High Level Configuration Options */
22#define CONFIG_BOOKE /* BOOKE */
23#define CONFIG_E500 /* BOOKE e500 family */
24#define CONFIG_MPC85xx /* MPC8540/60/55/41/48 */
25#define CONFIG_P1022
26#define CONFIG_P1022DS
27#define CONFIG_MP /* support multiple processors */
28
Wolfgang Denk2ae18242010-10-06 09:05:45 +020029#ifndef CONFIG_SYS_TEXT_BASE
30#define CONFIG_SYS_TEXT_BASE 0xeff80000
31#endif
32
Kumar Gala7a577fd2011-01-12 02:48:53 -060033#ifndef CONFIG_RESET_VECTOR_ADDRESS
34#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
35#endif
36
Timur Tabic59e1b42010-06-14 15:28:24 -050037#define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */
38#define CONFIG_PCI /* Enable PCI/PCIE */
39#define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */
40#define CONFIG_PCIE2 /* PCIE controler 2 (slot 2) */
41#define CONFIG_PCIE3 /* PCIE controler 3 (ULI bridge) */
42#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
43#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
44#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
45
Jiang Yutang9899ac12011-01-24 18:21:15 +080046#ifdef CONFIG_PHYS_64BIT
Timur Tabic59e1b42010-06-14 15:28:24 -050047#define CONFIG_ENABLE_36BIT_PHYS
48#define CONFIG_ADDR_MAP
49#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
Jiang Yutang9899ac12011-01-24 18:21:15 +080050#endif
Timur Tabic59e1b42010-06-14 15:28:24 -050051
52#define CONFIG_FSL_LAW /* Use common FSL init code */
53
54#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
55#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
56#define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */
57
58/*
59 * These can be toggled for performance analysis, otherwise use default.
60 */
61#define CONFIG_L2_CACHE
62#define CONFIG_BTB
63
64#define CONFIG_SYS_MEMTEST_START 0x00000000
65#define CONFIG_SYS_MEMTEST_END 0x7fffffff
66
67/*
68 * Base addresses -- Note these are effective addresses where the
69 * actual resources get mapped (not physical addresses)
70 */
71#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
72#define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */
Jiang Yutang9899ac12011-01-24 18:21:15 +080073#ifdef CONFIG_PHYS_64BIT
Timur Tabic59e1b42010-06-14 15:28:24 -050074#define CONFIG_SYS_CCSRBAR_PHYS 0xfffe00000ull
Jiang Yutang9899ac12011-01-24 18:21:15 +080075#else
76#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR
77#endif
Timur Tabic59e1b42010-06-14 15:28:24 -050078#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR
79
Timur Tabic59e1b42010-06-14 15:28:24 -050080/* DDR Setup */
81#define CONFIG_DDR_SPD
82#define CONFIG_VERY_BIG_RAM
83#define CONFIG_FSL_DDR3
84
85#ifdef CONFIG_DDR_ECC
86#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
87#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
88#endif
89
90#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
91#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
92
93#define CONFIG_NUM_DDR_CONTROLLERS 1
94#define CONFIG_DIMM_SLOTS_PER_CTLR 1
95#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
96
97/* I2C addresses of SPD EEPROMs */
98#define CONFIG_SYS_SPD_BUS_NUM 1
Kumar Galac39f44d2011-01-31 22:18:47 -060099#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
Timur Tabic59e1b42010-06-14 15:28:24 -0500100
101/*
102 * Memory map
103 *
104 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
105 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable
106 * 0xffc0_0000 0xffc2_ffff PCI IO range 192K non-cacheable
107 *
108 * Localbus cacheable (TBD)
109 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable
110 *
111 * Localbus non-cacheable
112 * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable
113 * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable
114 * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0
115 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
116 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
117 */
118
119/*
120 * Local Bus Definitions
121 */
122#define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */
Jiang Yutang9899ac12011-01-24 18:21:15 +0800123#ifdef CONFIG_PHYS_64BIT
Timur Tabic59e1b42010-06-14 15:28:24 -0500124#define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
Jiang Yutang9899ac12011-01-24 18:21:15 +0800125#else
126#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
127#endif
Timur Tabic59e1b42010-06-14 15:28:24 -0500128
129#define CONFIG_FLASH_BR_PRELIM \
130 (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | BR_PS_16 | BR_V)
131#define CONFIG_FLASH_OR_PRELIM (OR_AM_128MB | 0xff7)
132
133#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
134#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
135
136#define CONFIG_SYS_BR1_PRELIM \
137 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
138#define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM
139
140#define CONFIG_SYS_FLASH_BANKS_LIST \
141 {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
142#define CONFIG_SYS_FLASH_QUIET_TEST
143#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
144
145#define CONFIG_SYS_MAX_FLASH_BANKS 2
146#define CONFIG_SYS_MAX_FLASH_SECT 1024
147
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200148#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
Timur Tabic59e1b42010-06-14 15:28:24 -0500149
150#define CONFIG_FLASH_CFI_DRIVER
151#define CONFIG_SYS_FLASH_CFI
152#define CONFIG_SYS_FLASH_EMPTY_INFO
153
154#define CONFIG_BOARD_EARLY_INIT_F
155#define CONFIG_BOARD_EARLY_INIT_R
156#define CONFIG_MISC_INIT_R
Timur Tabia2d12f82010-07-21 16:56:19 -0500157#define CONFIG_HWCONFIG
Timur Tabic59e1b42010-06-14 15:28:24 -0500158
159#define CONFIG_FSL_NGPIXIS
160#define PIXIS_BASE 0xffdf0000 /* PIXIS registers */
Jiang Yutang9899ac12011-01-24 18:21:15 +0800161#ifdef CONFIG_PHYS_64BIT
Timur Tabic59e1b42010-06-14 15:28:24 -0500162#define PIXIS_BASE_PHYS 0xfffdf0000ull
Jiang Yutang9899ac12011-01-24 18:21:15 +0800163#else
164#define PIXIS_BASE_PHYS PIXIS_BASE
165#endif
Timur Tabic59e1b42010-06-14 15:28:24 -0500166
167#define CONFIG_SYS_BR2_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
168#define CONFIG_SYS_OR2_PRELIM (OR_AM_32KB | 0x6ff7)
169
170#define PIXIS_LBMAP_SWITCH 7
York Sun29068452011-01-26 10:30:00 -0800171#define PIXIS_LBMAP_MASK 0xF0
Timur Tabic59e1b42010-06-14 15:28:24 -0500172#define PIXIS_LBMAP_ALTBANK 0x20
Jiang Yutang9b6e9d12011-02-24 16:11:56 +0800173#define PIXIS_ELBC_SPI_MASK 0xc0
174#define PIXIS_SPI 0x80
Timur Tabic59e1b42010-06-14 15:28:24 -0500175
176#define CONFIG_SYS_INIT_RAM_LOCK
177#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200178#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
Timur Tabic59e1b42010-06-14 15:28:24 -0500179
Timur Tabic59e1b42010-06-14 15:28:24 -0500180#define CONFIG_SYS_GBL_DATA_OFFSET \
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200181 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Timur Tabic59e1b42010-06-14 15:28:24 -0500182#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
183
184#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
185#define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024)
186
187/*
188 * Serial Port
189 */
190#define CONFIG_CONS_INDEX 1
191#define CONFIG_SYS_NS16550
192#define CONFIG_SYS_NS16550_SERIAL
193#define CONFIG_SYS_NS16550_REG_SIZE 1
194#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
195
196#define CONFIG_SYS_BAUDRATE_TABLE \
197 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
198
199#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
200#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
201
202/* Use the HUSH parser */
203#define CONFIG_SYS_HUSH_PARSER
204#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
205
Timur Tabic59e1b42010-06-14 15:28:24 -0500206/* Video */
Timur Tabiba8e76b2011-04-11 14:18:22 -0500207#define CONFIG_FSL_DIU_FB
208
Timur Tabid5e01e42010-09-24 01:25:53 +0200209#ifdef CONFIG_FSL_DIU_FB
210#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x10000)
211#define CONFIG_VIDEO
212#define CONFIG_CMD_BMP
Timur Tabic59e1b42010-06-14 15:28:24 -0500213#define CONFIG_CFB_CONSOLE
Timur Tabi7d3053f2011-02-15 17:09:19 -0600214#define CONFIG_VIDEO_SW_CURSOR
Timur Tabic59e1b42010-06-14 15:28:24 -0500215#define CONFIG_VGA_AS_SINGLE_DEVICE
Timur Tabid5e01e42010-09-24 01:25:53 +0200216#define CONFIG_VIDEO_LOGO
217#define CONFIG_VIDEO_BMP_LOGO
Timur Tabi55b05232010-09-16 16:35:44 -0500218#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
219/*
220 * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
221 * disable empty flash sector detection, which is I/O-intensive.
222 */
223#undef CONFIG_SYS_FLASH_EMPTY_INFO
Timur Tabic59e1b42010-06-14 15:28:24 -0500224#endif
225
Timur Tabiba8e76b2011-04-11 14:18:22 -0500226#ifndef CONFIG_FSL_DIU_FB
Jiang Yutang218a7582011-01-24 18:21:19 +0800227#define CONFIG_ATI
228#endif
229
230#ifdef CONFIG_ATI
231#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT
232#define CONFIG_VIDEO
233#define CONFIG_BIOSEMU
234#define CONFIG_VIDEO_SW_CURSOR
235#define CONFIG_ATI_RADEON_FB
236#define CONFIG_VIDEO_LOGO
237#define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
238#define CONFIG_CFB_CONSOLE
239#define CONFIG_VGA_AS_SINGLE_DEVICE
240#endif
241
Timur Tabic59e1b42010-06-14 15:28:24 -0500242/*
243 * Pass open firmware flat tree
244 */
245#define CONFIG_OF_LIBFDT
246#define CONFIG_OF_BOARD_SETUP
247#define CONFIG_OF_STDOUT_VIA_ALIAS
248
249/* new uImage format support */
250#define CONFIG_FIT
251#define CONFIG_FIT_VERBOSE
252
253/* I2C */
254#define CONFIG_FSL_I2C
255#define CONFIG_HARD_I2C
256#define CONFIG_I2C_MULTI_BUS
257#define CONFIG_SYS_I2C_SPEED 400000
258#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
259#define CONFIG_SYS_I2C_SLAVE 0x7F
260#define CONFIG_SYS_I2C_NOPROBES {{0, 0x29}}
261#define CONFIG_SYS_I2C_OFFSET 0x3000
262#define CONFIG_SYS_I2C2_OFFSET 0x3100
263
264/*
265 * I2C2 EEPROM
266 */
267#define CONFIG_ID_EEPROM
268#define CONFIG_SYS_I2C_EEPROM_NXID
269#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
270#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
271#define CONFIG_SYS_EEPROM_BUS_NUM 1
272
273/*
Jiang Yutang9b6e9d12011-02-24 16:11:56 +0800274 * eSPI - Enhanced SPI
275 */
276#define CONFIG_SPI_FLASH
277#define CONFIG_SPI_FLASH_SPANSION
278
279#define CONFIG_HARD_SPI
280#define CONFIG_FSL_ESPI
281
282#define CONFIG_CMD_SF
283#define CONFIG_SF_DEFAULT_SPEED 10000000
284#define CONFIG_SF_DEFAULT_MODE 0
285
286/*
Timur Tabic59e1b42010-06-14 15:28:24 -0500287 * General PCI
288 * Memory space is mapped 1-1, but I/O space must start from 0.
289 */
290
291/* controller 1, Slot 2, tgtid 1, Base address a000 */
292#define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
Jiang Yutang9899ac12011-01-24 18:21:15 +0800293#ifdef CONFIG_PHYS_64BIT
Timur Tabic59e1b42010-06-14 15:28:24 -0500294#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
295#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull
Jiang Yutang9899ac12011-01-24 18:21:15 +0800296#else
297#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
298#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000
299#endif
Timur Tabic59e1b42010-06-14 15:28:24 -0500300#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
301#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000
302#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
Jiang Yutang9899ac12011-01-24 18:21:15 +0800303#ifdef CONFIG_PHYS_64BIT
Timur Tabic59e1b42010-06-14 15:28:24 -0500304#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull
Jiang Yutang9899ac12011-01-24 18:21:15 +0800305#else
306#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000
307#endif
Timur Tabic59e1b42010-06-14 15:28:24 -0500308#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
309
310/* controller 2, direct to uli, tgtid 2, Base address 9000 */
311#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
Jiang Yutang9899ac12011-01-24 18:21:15 +0800312#ifdef CONFIG_PHYS_64BIT
Timur Tabic59e1b42010-06-14 15:28:24 -0500313#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
314#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
Jiang Yutang9899ac12011-01-24 18:21:15 +0800315#else
316#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
317#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
318#endif
Timur Tabic59e1b42010-06-14 15:28:24 -0500319#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
320#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
321#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
Jiang Yutang9899ac12011-01-24 18:21:15 +0800322#ifdef CONFIG_PHYS_64BIT
Timur Tabic59e1b42010-06-14 15:28:24 -0500323#define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
Jiang Yutang9899ac12011-01-24 18:21:15 +0800324#else
325#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
326#endif
Timur Tabic59e1b42010-06-14 15:28:24 -0500327#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
328
329/* controller 3, Slot 1, tgtid 3, Base address b000 */
330#define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000
Jiang Yutang9899ac12011-01-24 18:21:15 +0800331#ifdef CONFIG_PHYS_64BIT
Timur Tabic59e1b42010-06-14 15:28:24 -0500332#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
333#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull
Jiang Yutang9899ac12011-01-24 18:21:15 +0800334#else
335#define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000
336#define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000
337#endif
Timur Tabic59e1b42010-06-14 15:28:24 -0500338#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
339#define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000
340#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
Jiang Yutang9899ac12011-01-24 18:21:15 +0800341#ifdef CONFIG_PHYS_64BIT
Timur Tabic59e1b42010-06-14 15:28:24 -0500342#define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull
Jiang Yutang9899ac12011-01-24 18:21:15 +0800343#else
344#define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000
345#endif
Timur Tabic59e1b42010-06-14 15:28:24 -0500346#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
347
348#ifdef CONFIG_PCI
349#define CONFIG_NET_MULTI
350#define CONFIG_PCI_PNP /* do pci plug-and-play */
351#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Kumar Gala16855ec2010-11-09 23:19:50 -0600352#define CONFIG_E1000 /* Define e1000 pci Ethernet card */
Timur Tabic59e1b42010-06-14 15:28:24 -0500353#endif
354
355/* SATA */
356#define CONFIG_LIBATA
357#define CONFIG_FSL_SATA
Jiang Yutang2d7534a2011-01-30 17:06:20 -0600358#define CONFIG_FSL_SATA_V2
Timur Tabic59e1b42010-06-14 15:28:24 -0500359
360#define CONFIG_SYS_SATA_MAX_DEVICE 2
361#define CONFIG_SATA1
362#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
363#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
364#define CONFIG_SATA2
365#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
366#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
367
368#ifdef CONFIG_FSL_SATA
369#define CONFIG_LBA48
370#define CONFIG_CMD_SATA
371#define CONFIG_DOS_PARTITION
372#define CONFIG_CMD_EXT2
373#endif
374
375#define CONFIG_MMC
376#ifdef CONFIG_MMC
377#define CONFIG_CMD_MMC
378#define CONFIG_FSL_ESDHC
379#define CONFIG_GENERIC_MMC
380#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
381#endif
382
383#if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI)
384#define CONFIG_CMD_EXT2
385#define CONFIG_CMD_FAT
386#define CONFIG_DOS_PARTITION
387#endif
388
389#define CONFIG_TSEC_ENET
390#ifdef CONFIG_TSEC_ENET
391
392#define CONFIG_TSECV2
393#define CONFIG_NET_MULTI
394
395#define CONFIG_MII /* MII PHY management */
396#define CONFIG_TSEC1 1
397#define CONFIG_TSEC1_NAME "eTSEC1"
398#define CONFIG_TSEC2 1
399#define CONFIG_TSEC2_NAME "eTSEC2"
400
401#define TSEC1_PHY_ADDR 1
402#define TSEC2_PHY_ADDR 2
403
404#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
405#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
406
407#define TSEC1_PHYIDX 0
408#define TSEC2_PHYIDX 0
409
410#define CONFIG_ETHPRIME "eTSEC1"
411
412#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
413#endif
414
415/*
416 * Environment
417 */
418#define CONFIG_ENV_IS_IN_FLASH
419#define CONFIG_ENV_OVERWRITE
420#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
421#define CONFIG_ENV_SIZE 0x2000
422#define CONFIG_ENV_SECT_SIZE 0x20000
423
424#define CONFIG_LOADS_ECHO
425#define CONFIG_SYS_LOADS_BAUD_CHANGE
426
427/*
428 * Command line configuration.
429 */
430#include <config_cmd_default.h>
431
Kumar Gala79ee3442010-06-09 22:59:41 -0500432#define CONFIG_CMD_ELF
433#define CONFIG_CMD_ERRATA
Timur Tabic59e1b42010-06-14 15:28:24 -0500434#define CONFIG_CMD_IRQ
Timur Tabic59e1b42010-06-14 15:28:24 -0500435#define CONFIG_CMD_I2C
436#define CONFIG_CMD_MII
Kumar Gala79ee3442010-06-09 22:59:41 -0500437#define CONFIG_CMD_PING
Timur Tabic59e1b42010-06-14 15:28:24 -0500438#define CONFIG_CMD_SETEXPR
Matthew McClintockb8339e22010-12-17 17:26:41 -0600439#define CONFIG_CMD_REGINFO
Timur Tabic59e1b42010-06-14 15:28:24 -0500440
441#ifdef CONFIG_PCI
442#define CONFIG_CMD_PCI
443#define CONFIG_CMD_NET
444#endif
445
446/*
447 * USB
448 */
449#define CONFIG_USB_EHCI
450
451#ifdef CONFIG_USB_EHCI
452#define CONFIG_CMD_USB
453#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
454#define CONFIG_USB_EHCI_FSL
455#define CONFIG_USB_STORAGE
456#define CONFIG_CMD_FAT
457#endif
458
459/*
460 * Miscellaneous configurable options
461 */
462#define CONFIG_SYS_LONGHELP /* undef to save memory */
463#define CONFIG_CMDLINE_EDITING /* Command-line editing */
Kim Phillips5be58f52010-07-14 19:47:18 -0500464#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
Timur Tabic59e1b42010-06-14 15:28:24 -0500465#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
466#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
467#ifdef CONFIG_CMD_KGDB
468#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
469#else
470#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
471#endif
472/* Print Buffer Size */
473#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
474#define CONFIG_SYS_MAXARGS 16
475#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
476#define CONFIG_SYS_HZ 1000
477
478/*
479 * For booting Linux, the board info and command line data
Kumar Galaa832ac42011-04-28 10:13:41 -0500480 * have to be in the first 64 MB of memory, since this is
Timur Tabic59e1b42010-06-14 15:28:24 -0500481 * the maximum mapped by the Linux kernel during initialization.
482 */
Kumar Galaa832ac42011-04-28 10:13:41 -0500483#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
484#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
Timur Tabic59e1b42010-06-14 15:28:24 -0500485
Timur Tabic59e1b42010-06-14 15:28:24 -0500486#ifdef CONFIG_CMD_KGDB
487#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
488#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
489#endif
490
491/*
492 * Environment Configuration
493 */
494
495#define CONFIG_HOSTNAME p1022ds
496#define CONFIG_ROOTPATH /opt/nfsroot
497#define CONFIG_BOOTFILE uImage
498#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
499
500#define CONFIG_LOADADDR 1000000
501
502#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
503#define CONFIG_BOOTARGS
504
505#define CONFIG_BAUDRATE 115200
506
507#define CONFIG_EXTRA_ENV_SETTINGS \
508 "perf_mode=stable\0" \
509 "memctl_intlv_ctl=2\0" \
510 "netdev=eth0\0" \
511 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
512 "tftpflash=tftpboot $loadaddr $uboot; " \
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200513 "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
514 "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
515 "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \
516 "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
517 "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
Timur Tabic59e1b42010-06-14 15:28:24 -0500518 "consoledev=ttyS0\0" \
519 "ramdiskaddr=2000000\0" \
520 "ramdiskfile=uramdisk\0" \
521 "fdtaddr=c00000\0" \
522 "fdtfile=p1022ds.dtb\0" \
523 "bdev=sda3\0" \
524 "diuregs=md e002c000 1d\0" \
525 "dium=mw e002c01c\0" \
526 "diuerr=md e002c014 1\0" \
Timur Tabiba8e76b2011-04-11 14:18:22 -0500527 "hwconfig=esdhc;audclk:12\0"
Timur Tabic59e1b42010-06-14 15:28:24 -0500528
529#define CONFIG_HDBOOT \
530 "setenv bootargs root=/dev/$bdev rw " \
531 "console=$consoledev,$baudrate $othbootargs;" \
532 "tftp $loadaddr $bootfile;" \
533 "tftp $fdtaddr $fdtfile;" \
534 "bootm $loadaddr - $fdtaddr"
535
536#define CONFIG_NFSBOOTCOMMAND \
537 "setenv bootargs root=/dev/nfs rw " \
538 "nfsroot=$serverip:$rootpath " \
539 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
540 "console=$consoledev,$baudrate $othbootargs;" \
541 "tftp $loadaddr $bootfile;" \
542 "tftp $fdtaddr $fdtfile;" \
543 "bootm $loadaddr - $fdtaddr"
544
545#define CONFIG_RAMBOOTCOMMAND \
546 "setenv bootargs root=/dev/ram rw " \
547 "console=$consoledev,$baudrate $othbootargs;" \
548 "tftp $ramdiskaddr $ramdiskfile;" \
549 "tftp $loadaddr $bootfile;" \
550 "tftp $fdtaddr $fdtfile;" \
551 "bootm $loadaddr $ramdiskaddr $fdtaddr"
552
553#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
554
555#endif