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Andreas Bießmannad7a1782011-06-30 22:03:20 +00001/*
2 * Copyright (C) 2011
3 * Corscience GmbH & Co.KG, Andreas Bießmann <biessmann@corscience.de>
4 *
5 * Configuration settings for the grasshopper (ICnova AP7000) board
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25#ifndef __GRASSHOPPER_CONFIG_H
26#define __GRASSHOPPER_CONFIG_H
27
28#include <asm/arch/hardware.h>
29
30#define CONFIG_AVR32
31#define CONFIG_AT32AP
32#define CONFIG_AT32AP7000
33
34/*
35 * Timer clock frequency. We're using the CPU-internal COUNT register
36 * for this, so this is equivalent to the CPU core clock frequency
37 */
38#define CONFIG_SYS_HZ 1000
39
40/*
41 * Set up the PLL to run at 140 MHz, the CPU to run at the PLL
42 * frequency, the HSB and PBB at 1/2, and the PBA to run at 1/4 the
43 * PLL frequency.
44 * (CONFIG_SYS_OSC0_HZ * CONFIG_SYS_PLL0_MUL) / CONFIG_SYS_PLL0_DIV = PLL MHz
45 */
46#define CONFIG_PLL
47#define CONFIG_SYS_POWER_MANAGER
48#define CONFIG_SYS_OSC0_HZ 20000000
49#define CONFIG_SYS_PLL0_DIV 1
50#define CONFIG_SYS_PLL0_MUL 7
51#define CONFIG_SYS_PLL0_SUPPRESS_CYCLES 16
52/*
53 * Set the CPU running at:
54 * PLL / (2^CONFIG_SYS_CLKDIV_CPU) = CPU MHz
55 */
56#define CONFIG_SYS_CLKDIV_CPU 0
57/*
58 * Set the HSB running at:
59 * PLL / (2^CONFIG_SYS_CLKDIV_HSB) = HSB MHz
60 */
61#define CONFIG_SYS_CLKDIV_HSB 1
62/*
63 * Set the PBA running at:
64 * PLL / (2^CONFIG_SYS_CLKDIV_PBA) = PBA MHz
65 */
66#define CONFIG_SYS_CLKDIV_PBA 2
67/*
68 * Set the PBB running at:
69 * PLL / (2^CONFIG_SYS_CLKDIV_PBB) = PBB MHz
70 */
71#define CONFIG_SYS_CLKDIV_PBB 1
72
73/* Reserve VM regions for SDRAM and NOR flash */
74#define CONFIG_SYS_NR_VM_REGIONS 2
75
76/*
77 * The PLLOPT register controls the PLL like this:
78 * icp = PLLOPT<2>
79 * ivco = PLLOPT<1:0>
80 *
81 * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz).
82 */
83#define CONFIG_SYS_PLL0_OPT 0x04
84
85#define CONFIG_USART_BASE ATMEL_BASE_USART1
86#define CONFIG_USART_ID 1
87
88/* User serviceable stuff */
89#define CONFIG_CMDLINE_TAG
90#define CONFIG_SETUP_MEMORY_TAGS
91#define CONFIG_INITRD_TAG
92
93#define CONFIG_STACKSIZE (2048)
94
95#define CONFIG_BAUDRATE 115200
96
97/*
98 * Only interrupt autoboot if <space> is pressed. Otherwise, garbage
99 * data on the serial line may interrupt the boot sequence.
100 */
101#define CONFIG_BOOTDELAY 1
102#define CONFIG_AUTOBOOT
103#define CONFIG_AUTOBOOT_KEYED
104#define CONFIG_AUTOBOOT_PROMPT "Press SPACE to abort autoboot in %d" \
105 " seconds\n", bootdelay
106#define CONFIG_AUTOBOOT_DELAY_STR "d"
107#define CONFIG_AUTOBOOT_STOP_STR " "
108
109/*
110 * After booting the board for the first time, new ethernet addresses
111 * should be generated and assigned to the environment variables
112 * "ethaddr". This is normally done during production.
113 */
114#define CONFIG_OVERWRITE_ETHADDR_ONCE
115#define CONFIG_NET_MULTI
116
117/*
118 * BOOTP options
119 */
120#define CONFIG_BOOTP_SUBNETMASK
121#define CONFIG_BOOTP_GATEWAY
122
123/*
124 * Command line configuration.
125 */
126#include <config_cmd_default.h>
127
128/* remove unneeded commands */
129#undef CONFIG_CMD_FPGA
130#undef CONFIG_CMD_SETGETDCR
131
132/* add useful commands */
133#define CONFIG_CMD_ASKENV
134#define CONFIG_CMD_DHCP
135#define CONFIG_CMD_JFFS2
136#define CONFIG_CMD_PING
137#define CONFIG_CMD_REGINFO
138
139#define CONFIG_SYS_HUSH_PARSER
140#define CONFIG_AUTO_COMPLETE
141#define CONFIG_SYS_PROMPT_HUSH_PS2 "~> "
142#define CONFIG_CMDLINE_EDITING
143
144#define CONFIG_ATMEL_USART
145#define CONFIG_MACB
146#define CONFIG_PORTMUX_PIO
147#define CONFIG_SYS_NR_PIOS 5
148#define CONFIG_SYS_HSDRAMC
149
150#define CONFIG_SYS_DCACHE_LINESZ 32
151#define CONFIG_SYS_ICACHE_LINESZ 32
152
153#define CONFIG_NR_DRAM_BANKS 1
154
155#define CONFIG_SYS_FLASH_CFI
156#define CONFIG_FLASH_CFI_DRIVER
157
158#define CONFIG_SYS_FLASH_BASE 0x00000000
159#define CONFIG_SYS_FLASH_SIZE 0x800000
160#define CONFIG_SYS_MAX_FLASH_BANKS 1
161#define CONFIG_SYS_MAX_FLASH_SECT 135
162
163#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
164#define CONFIG_SYS_TEXT_BASE 0x00000000
165
166#define CONFIG_SYS_INTRAM_BASE INTERNAL_SRAM_BASE
167#define CONFIG_SYS_INTRAM_SIZE INTERNAL_SRAM_SIZE
168#define CONFIG_SYS_SDRAM_BASE EBI_SDRAM_BASE
169
170#define CONFIG_ENV_IS_IN_FLASH
171/* place u-boot env in flash sector after u-boot */
172#define CONFIG_ENV_SIZE 0x10000
173#define CONFIG_ENV_ADDR 0x20000
174
175#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INTRAM_BASE + \
176 CONFIG_SYS_INTRAM_SIZE)
177
178#define CONFIG_SYS_MALLOC_LEN (256*1024)
179#define CONFIG_SYS_DMA_ALLOC_LEN (16384)
180
181/* Allow 4MB for the kernel run-time image */
182#define CONFIG_SYS_LOAD_ADDR (EBI_SDRAM_BASE + 0x00400000)
183#define CONFIG_SYS_BOOTPARAMS_LEN (16 * 1024)
184
185/* Other configuration settings that shouldn't have to change all that often */
186#define CONFIG_SYS_PROMPT "U-Boot> "
187#define CONFIG_SYS_CBSIZE 256
188#define CONFIG_SYS_MAXARGS 16
189#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
190 sizeof(CONFIG_SYS_PROMPT) + 16)
191#define CONFIG_SYS_LONGHELP
192
193#define CONFIG_SYS_MEMTEST_START EBI_SDRAM_BASE
194#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x700000)
195#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 }
196
197#endif /* __GRASSHOPPER_CONFIG_H */
198/* vim: set ts=8 noet: */