blob: a74766dcec9248cf68db9816866a26ced08e9ddb [file] [log] [blame]
Peter Tyserccf0fdd2008-12-17 16:36:23 -06001/*
2 * Copyright 2008 Extreme Engineering Solutions, Inc.
3 * Copyright 2007-2008 Freescale Semiconductor, Inc.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
Peter Tyserc00ac252010-10-22 00:20:26 -050025 * xpedite537x board configuration file
Peter Tyserccf0fdd2008-12-17 16:36:23 -060026 */
27#ifndef __CONFIG_H
28#define __CONFIG_H
29
30/*
31 * High Level Configuration Options
32 */
33#define CONFIG_BOOKE 1 /* BOOKE */
34#define CONFIG_E500 1 /* BOOKE e500 family */
35#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */
36#define CONFIG_MPC8572 1
37#define CONFIG_XPEDITE5370 1
38#define CONFIG_SYS_BOARD_NAME "XPedite5370"
John Schmoller92af65492010-10-22 00:20:24 -050039#define CONFIG_SYS_FORM_3U_VPX 1
Peter Tyserccf0fdd2008-12-17 16:36:23 -060040#define CONFIG_BOARD_EARLY_INIT_R /* Call board_pre_init */
Peter Tyserccf0fdd2008-12-17 16:36:23 -060041
Wolfgang Denk2ae18242010-10-06 09:05:45 +020042#ifndef CONFIG_SYS_TEXT_BASE
43#define CONFIG_SYS_TEXT_BASE 0xfff80000
44#endif
45
Peter Tyserccf0fdd2008-12-17 16:36:23 -060046#define CONFIG_PCI 1 /* Enable PCI/PCIE */
47#define CONFIG_PCI_PNP 1 /* do pci plug-and-play */
48#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
49#define CONFIG_PCIE1 1 /* PCIE controler 1 */
50#define CONFIG_PCIE2 1 /* PCIE controler 2 */
51#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
52#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
53#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
54#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
Becky Bruce0914f482010-06-17 11:37:18 -050055#define CONFIG_FSL_ELBC 1
Peter Tyserccf0fdd2008-12-17 16:36:23 -060056
57/*
Peter Tyser48618122009-10-23 15:55:48 -050058 * Multicore config
59 */
60#define CONFIG_MP
61#define CONFIG_BPTR_VIRT_ADDR 0xee000000 /* virt boot page address */
62#define CONFIG_MPC8xxx_DISABLE_BPTR /* Don't leave BPTR enabled */
63
64/*
Peter Tyserccf0fdd2008-12-17 16:36:23 -060065 * DDR config
66 */
67#define CONFIG_FSL_DDR2
68#undef CONFIG_FSL_DDR_INTERACTIVE
69#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
70#define CONFIG_DDR_SPD
71#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
72#define SPD_EEPROM_ADDRESS1 0x54 /* Both channels use the */
73#define SPD_EEPROM_ADDRESS2 0x54 /* same SPD data */
74#define SPD_EEPROM_OFFSET 0x200 /* OFFSET of SPD in EEPROM */
75#define CONFIG_NUM_DDR_CONTROLLERS 2
76#define CONFIG_DIMM_SLOTS_PER_CTLR 1
77#define CONFIG_CHIP_SELECTS_PER_CTRL 1
78#define CONFIG_DDR_ECC
79#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
80#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
81#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
82#define CONFIG_VERY_BIG_RAM
83
84#ifndef __ASSEMBLY__
85extern unsigned long get_board_sys_clk(unsigned long dummy);
86extern unsigned long get_board_ddr_clk(unsigned long dummy);
87#endif
88
89#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */
90#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk(0) /* ddrclk for MPC85xx */
91
92/*
93 * These can be toggled for performance analysis, otherwise use default.
94 */
95#define CONFIG_L2_CACHE /* toggle L2 cache */
96#define CONFIG_BTB /* toggle branch predition */
97#define CONFIG_ENABLE_36BIT_PHYS 1
98
99/*
100 * Base addresses -- Note these are effective addresses where the
101 * actual resources get mapped (not physical addresses)
102 */
103#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
104#define CONFIG_SYS_CCSRBAR 0xef000000 /* relocated CCSRBAR */
105#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */
106#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
Peter Tyserccf0fdd2008-12-17 16:36:23 -0600107
108/*
109 * Diagnostics
110 */
111#define CONFIG_SYS_ALT_MEMTEST
112#define CONFIG_SYS_MEMTEST_START 0x10000000
113#define CONFIG_SYS_MEMTEST_END 0x20000000
Peter Tyser66a8b442010-10-22 00:20:33 -0500114#define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \
115 CONFIG_SYS_POST_I2C)
116#define I2C_ADDR_LIST {CONFIG_SYS_I2C_DS1621_ADDR, \
117 CONFIG_SYS_I2C_DS4510_ADDR, \
118 CONFIG_SYS_I2C_EEPROM_ADDR, \
119 CONFIG_SYS_I2C_LM90_ADDR, \
120 CONFIG_SYS_I2C_PCA953X_ADDR0, \
121 CONFIG_SYS_I2C_PCA953X_ADDR1, \
122 CONFIG_SYS_I2C_PCA953X_ADDR2, \
123 CONFIG_SYS_I2C_PCA953X_ADDR3, \
124 CONFIG_SYS_I2C_PEX8518_ADDR, \
125 CONFIG_SYS_I2C_RTC_ADDR}
126/* The XPedite5370 can host an XMC which has an EEPROM at address 0x50 */
127#define I2C_ADDR_IGNORE_LIST {0x50}
Peter Tyserccf0fdd2008-12-17 16:36:23 -0600128
129/*
130 * Memory map
131 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
132 * 0x8000_0000 0xbfff_ffff PCIe1 Mem 1G non-cacheable
133 * 0xc000_0000 0xcfff_ffff PCIe2 Mem 256M non-cacheable
134 * 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable
135 * 0xe800_0000 0xe87f_ffff PCIe1 IO 8M non-cacheable
136 * 0xe880_0000 0xe8ff_ffff PCIe2 IO 8M non-cacheable
Peter Tyser48618122009-10-23 15:55:48 -0500137 * 0xee00_0000 0xee00_ffff Boot page translation 4K non-cacheable
Peter Tyserccf0fdd2008-12-17 16:36:23 -0600138 * 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable
139 * 0xef80_0000 0xef8f_ffff NAND Flash 1M non-cacheable
140 * 0xf000_0000 0xf7ff_ffff NOR Flash 2 128M non-cacheable
141 * 0xf800_0000 0xffff_ffff NOR Flash 1 128M non-cacheable
142 */
143
Kumar Gala202d9482009-09-15 22:21:58 -0500144#define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_8 | LCRR_EADC_3)
Peter Tyserccf0fdd2008-12-17 16:36:23 -0600145
146/*
147 * NAND flash configuration
148 */
149#define CONFIG_SYS_NAND_BASE 0xef800000
150#define CONFIG_SYS_NAND_BASE2 0xef840000 /* Unused at this time */
Peter Tyser0a6d0c62009-07-21 13:51:08 -0500151#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE, \
152 CONFIG_SYS_NAND_BASE2}
153#define CONFIG_SYS_MAX_NAND_DEVICE 2
154#define CONFIG_MTD_NAND_VERIFY_WRITE
155#define CONFIG_SYS_NAND_QUIET_TEST /* 2nd NAND flash not always populated */
156#define CONFIG_NAND_FSL_ELBC
Peter Tyserccf0fdd2008-12-17 16:36:23 -0600157
158/*
159 * NOR flash configuration
160 */
161#define CONFIG_SYS_FLASH_BASE 0xf8000000
162#define CONFIG_SYS_FLASH_BASE2 0xf0000000
163#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
164#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
165#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
166#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
167#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
168#define CONFIG_FLASH_CFI_DRIVER
169#define CONFIG_SYS_FLASH_CFI
Peter Tyser5ff82102009-07-19 19:17:40 -0500170#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
Peter Tyserccf0fdd2008-12-17 16:36:23 -0600171#define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { {0xfff40000, 0xc0000}, \
172 {0xf7f40000, 0xc0000} }
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200173#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
Peter Tyserccf0fdd2008-12-17 16:36:23 -0600174
175/*
176 * Chip select configuration
177 */
178/* NOR Flash 0 on CS0 */
179#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \
180 BR_PS_16 | \
181 BR_V)
182#define CONFIG_SYS_OR0_PRELIM (OR_AM_128MB | \
183 OR_GPCM_CSNT | \
184 OR_GPCM_XACS | \
185 OR_GPCM_ACS_DIV2 | \
186 OR_GPCM_SCY_8 | \
187 OR_GPCM_TRLX | \
188 OR_GPCM_EHTR | \
189 OR_GPCM_EAD)
190
191/* NOR Flash 1 on CS1 */
192#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FLASH_BASE2 | \
193 BR_PS_16 | \
194 BR_V)
195#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
196
197/* NAND flash on CS2 */
198#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_NAND_BASE | \
199 (2<<BR_DECC_SHIFT) | \
200 BR_PS_8 | \
201 BR_MS_FCM | \
202 BR_V)
203
204/* NAND flash on CS2 */
205#define CONFIG_SYS_OR2_PRELIM (OR_AM_256KB | \
206 OR_FCM_PGS | \
207 OR_FCM_CSCT | \
208 OR_FCM_CST | \
209 OR_FCM_CHT | \
210 OR_FCM_SCY_1 | \
211 OR_FCM_TRLX | \
212 OR_FCM_EHTR)
213
214/* NAND flash on CS3 */
215#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE2 | \
216 (2<<BR_DECC_SHIFT) | \
217 BR_PS_8 | \
218 BR_MS_FCM | \
219 BR_V)
220#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
221
222/*
223 * Use L1 as initial stack
224 */
225#define CONFIG_SYS_INIT_RAM_LOCK 1
226#define CONFIG_SYS_INIT_RAM_ADDR 0xe0000000
Wolfgang Denk553f0982010-10-26 13:32:32 +0200227#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
Peter Tyserccf0fdd2008-12-17 16:36:23 -0600228
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200229#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Peter Tyserccf0fdd2008-12-17 16:36:23 -0600230#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
231
232#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */
233#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
234
235/*
236 * Serial Port
237 */
238#define CONFIG_CONS_INDEX 1
239#define CONFIG_SYS_NS16550
240#define CONFIG_SYS_NS16550_SERIAL
241#define CONFIG_SYS_NS16550_REG_SIZE 1
242#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
243#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
244#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
245#define CONFIG_SYS_BAUDRATE_TABLE \
246 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
247#define CONFIG_BAUDRATE 115200
248#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
249#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
250
251/*
252 * Use the HUSH parser
253 */
254#define CONFIG_SYS_HUSH_PARSER
255#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
256
257/*
258 * Pass open firmware flat tree
259 */
260#define CONFIG_OF_LIBFDT 1
261#define CONFIG_OF_BOARD_SETUP 1
262#define CONFIG_OF_STDOUT_VIA_ALIAS 1
263
Peter Tyserccf0fdd2008-12-17 16:36:23 -0600264/*
265 * I2C
266 */
267#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
268#define CONFIG_HARD_I2C /* I2C with hardware support */
269#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
270#define CONFIG_SYS_I2C_SLAVE 0x7F
271#define CONFIG_SYS_I2C_OFFSET 0x3000
272#define CONFIG_SYS_I2C2_OFFSET 0x3100
273#define CONFIG_I2C_MULTI_BUS
Peter Tyserccf0fdd2008-12-17 16:36:23 -0600274
275/* PEX8518 slave I2C interface */
276#define CONFIG_SYS_I2C_PEX8518_ADDR 0x70
277
278/* I2C DS1631 temperature sensor */
279#define CONFIG_SYS_I2C_DS1621_ADDR 0x48
280#define CONFIG_DTT_DS1621
281#define CONFIG_DTT_SENSORS { 0 }
Peter Tyser66a8b442010-10-22 00:20:33 -0500282#define CONFIG_SYS_I2C_LM90_ADDR 0x4c
Peter Tyserccf0fdd2008-12-17 16:36:23 -0600283
284/* I2C EEPROM - AT24C128B */
285#define CONFIG_SYS_I2C_EEPROM_ADDR 0x54
286#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
287#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */
288#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* take up to 10 msec */
289
290/* I2C RTC */
291#define CONFIG_RTC_M41T11 1
292#define CONFIG_SYS_I2C_RTC_ADDR 0x68
293#define CONFIG_SYS_M41T11_BASE_YEAR 2000
294
295/* GPIO/EEPROM/SRAM */
296#define CONFIG_DS4510
297#define CONFIG_SYS_I2C_DS4510_ADDR 0x51
298
299/* GPIO */
300#define CONFIG_PCA953X
301#define CONFIG_SYS_I2C_PCA953X_ADDR0 0x18
302#define CONFIG_SYS_I2C_PCA953X_ADDR1 0x1c
303#define CONFIG_SYS_I2C_PCA953X_ADDR2 0x1e
304#define CONFIG_SYS_I2C_PCA953X_ADDR3 0x1f
305#define CONFIG_SYS_I2C_PCA953X_ADDR CONFIG_SYS_I2C_PCA953X_ADDR0
306
307/*
308 * PU = pulled high, PD = pulled low
309 * I = input, O = output, IO = input/output
310 */
311/* PCA9557 @ 0x18*/
312#define CONFIG_SYS_PCA953X_C0_SER0_EN 0x01 /* PU; UART0 enable (1: enabled) */
313#define CONFIG_SYS_PCA953X_C0_SER0_MODE 0x02 /* PU; UART0 serial mode select */
314#define CONFIG_SYS_PCA953X_C0_SER1_EN 0x04 /* PU; UART1 enable (1: enabled) */
315#define CONFIG_SYS_PCA953X_C0_SER1_MODE 0x08 /* PU; UART1 serial mode select */
316#define CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS 0x10 /* PU; Boot flash CS select */
317#define CONFIG_SYS_PCA953X_NVM_WP 0x20 /* PU; Set to 0 to enable NVM writing */
318#define CONFIG_SYS_PCA953X_C0_VCORE_VID2 0x40 /* VID2 of ISL6262 */
319#define CONFIG_SYS_PCA953X_C0_VCORE_VID3 0x80 /* VID3 of ISL6262 */
320
321/* PCA9557 @ 0x1c*/
322#define CONFIG_SYS_PCA953X_XMC0_ROOT0 0x01 /* PU; Low if XMC is RC */
323#define CONFIG_SYS_PCA953X_XMC0_MVMR0 0x02 /* XMC EEPROM write protect */
324#define CONFIG_SYS_PCA953X_XMC0_WAKE 0x04 /* PU; XMC wake */
325#define CONFIG_SYS_PCA953X_XMC0_BIST 0x08 /* PU; XMC built in self test */
326#define CONFIG_SYS_PCA953X_XMC_PRESENT 0x10 /* PU; Low if XMC module installed */
327#define CONFIG_SYS_PCA953X_PMC_PRESENT 0x20 /* PU; Low if PMC module installed */
328#define CONFIG_SYS_PCA953X_PMC0_MONARCH 0x40 /* PMC monarch mode enable */
329#define CONFIG_SYS_PCA953X_PMC0_EREADY 0x80 /* PU; PMC PCI eready */
330
331/* PCA9557 @ 0x1e*/
332#define CONFIG_SYS_PCA953X_P0_GA0 0x01 /* PU; VPX Geographical address */
333#define CONFIG_SYS_PCA953X_P0_GA1 0x02 /* PU; VPX Geographical address */
334#define CONFIG_SYS_PCA953X_P0_GA2 0x04 /* PU; VPX Geographical address */
335#define CONFIG_SYS_PCA953X_P0_GA3 0x08 /* PU; VPX Geographical address */
336#define CONFIG_SYS_PCA953X_P0_GA4 0x10 /* PU; VPX Geographical address */
337#define CONFIG_SYS_PCA953X_P0_GAP 0x20 /* PU; tied to VPX P0.GAP */
338#define CONFIG_SYS_PCA953X_P1_SYSEN 0x80 /* PU; Pulled high; tied to VPX P1.SYSCON */
339
340/* PCA9557 @ 0x1f */
341#define CONFIG_SYS_PCA953X_GPIO_VPX0 0x01 /* PU */
342#define CONFIG_SYS_PCA953X_GPIO_VPX1 0x02 /* PU */
343#define CONFIG_SYS_PCA953X_GPIO_VPX2 0x04 /* PU */
344#define CONFIG_SYS_PCA953X_GPIO_VPX3 0x08 /* PU */
345#define CONFIG_SYS_PCA953X_VPX_FRU_WRCTL 0x10 /* PD; I2C master source for FRU SEEPROM */
346
347/*
348 * General PCI
349 * Memory space is mapped 1-1, but I/O space must start from 0.
350 */
351/* PCIE1 - VPX P1 */
Peter Tyser9660c5d2010-10-22 00:20:22 -0500352#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
353#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS
Peter Tyserccf0fdd2008-12-17 16:36:23 -0600354#define CONFIG_SYS_PCIE1_MEM_SIZE 0x40000000 /* 1G */
Peter Tyser9660c5d2010-10-22 00:20:22 -0500355#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
Peter Tyserccf0fdd2008-12-17 16:36:23 -0600356#define CONFIG_SYS_PCIE1_IO_PHYS 0xe8000000
357#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */
358
359/* PCIE2 - PEX8518 */
Peter Tyser9660c5d2010-10-22 00:20:22 -0500360#define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000
361#define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BUS
Peter Tyserccf0fdd2008-12-17 16:36:23 -0600362#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
Peter Tyser9660c5d2010-10-22 00:20:22 -0500363#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
Peter Tyserccf0fdd2008-12-17 16:36:23 -0600364#define CONFIG_SYS_PCIE2_IO_PHYS 0xe8800000
365#define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000 /* 8M */
366
367/*
368 * Networking options
369 */
370#define CONFIG_TSEC_ENET /* tsec ethernet support */
371#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
372#define CONFIG_NET_MULTI 1
373#define CONFIG_TSEC_TBI
374#define CONFIG_MII 1 /* MII PHY management */
375#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
376#define CONFIG_ETHPRIME "eTSEC2"
377
Kumar Gala72c96a62010-12-01 22:55:54 -0600378/*
379 * In-band SGMII auto-negotiation between TBI and BCM5482S PHY fails, force
380 * 1000mbps SGMII link
381 */
382#define CONFIG_TSEC_TBICR_SETTINGS ( \
383 TBICR_PHY_RESET \
384 | TBICR_FULL_DUPLEX \
385 | TBICR_SPEED1_SET \
386 )
387
Peter Tyserccf0fdd2008-12-17 16:36:23 -0600388#define CONFIG_TSEC1 1
389#define CONFIG_TSEC1_NAME "eTSEC1"
390#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
391#define TSEC1_PHY_ADDR 1
392#define TSEC1_PHYIDX 0
393#define CONFIG_HAS_ETH0
394
395#define CONFIG_TSEC2 1
396#define CONFIG_TSEC2_NAME "eTSEC2"
397#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
398#define TSEC2_PHY_ADDR 2
399#define TSEC2_PHYIDX 0
400#define CONFIG_HAS_ETH1
401
402/*
403 * Command configuration.
404 */
405#include <config_cmd_default.h>
406
407#define CONFIG_CMD_ASKENV
408#define CONFIG_CMD_DATE
409#define CONFIG_CMD_DHCP
410#define CONFIG_CMD_DS4510
411#define CONFIG_CMD_DS4510_INFO
412#define CONFIG_CMD_DTT
413#define CONFIG_CMD_EEPROM
414#define CONFIG_CMD_ELF
Peter Tyserccf0fdd2008-12-17 16:36:23 -0600415#define CONFIG_CMD_FLASH
416#define CONFIG_CMD_I2C
417#define CONFIG_CMD_JFFS2
418#define CONFIG_CMD_MII
Peter Tyser0a6d0c62009-07-21 13:51:08 -0500419#define CONFIG_CMD_NAND
Peter Tyserccf0fdd2008-12-17 16:36:23 -0600420#define CONFIG_CMD_NET
421#define CONFIG_CMD_PCA953X
422#define CONFIG_CMD_PCA953X_INFO
423#define CONFIG_CMD_PCI
John Schmoller96d61602010-10-22 00:20:23 -0500424#define CONFIG_CMD_PCI_ENUM
Peter Tyserccf0fdd2008-12-17 16:36:23 -0600425#define CONFIG_CMD_PING
Peter Tyser0a6d0c62009-07-21 13:51:08 -0500426#define CONFIG_CMD_SAVEENV
Peter Tyserccf0fdd2008-12-17 16:36:23 -0600427#define CONFIG_CMD_SNTP
Becky Bruce199e2622010-06-17 11:37:25 -0500428#define CONFIG_CMD_REGINFO
Peter Tyserccf0fdd2008-12-17 16:36:23 -0600429
430/*
431 * Miscellaneous configurable options
432 */
433#define CONFIG_SYS_LONGHELP /* undef to save memory */
434#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
435#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
436#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
437#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
438#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
439#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
440#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
441#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
Kim Phillips5be58f52010-07-14 19:47:18 -0500442#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
Peter Tyserccf0fdd2008-12-17 16:36:23 -0600443#define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */
444#define CONFIG_BOOTDELAY 3 /* -1 disables auto-boot */
445#define CONFIG_PANIC_HANG /* do not reset board on panic */
446#define CONFIG_PREBOOT /* enable preboot variable */
447#define CONFIG_FIT 1
448#define CONFIG_FIT_VERBOSE 1
449#define CONFIG_INTEGRITY /* support booting INTEGRITY OS */
450
451/*
452 * For booting Linux, the board info and command line data
453 * have to be in the first 16 MB of memory, since this is
454 * the maximum mapped by the Linux kernel during initialization.
455 */
456#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
Peter Tyser39121c02009-07-21 13:51:07 -0500457#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */
Peter Tyserccf0fdd2008-12-17 16:36:23 -0600458
459/*
Peter Tyserccf0fdd2008-12-17 16:36:23 -0600460 * Environment Configuration
461 */
462#define CONFIG_ENV_IS_IN_FLASH 1
463#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128k (one sector) for env */
464#define CONFIG_ENV_SIZE 0x8000
465#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - (256 * 1024))
466
467/*
468 * Flash memory map:
469 * fff80000 - ffffffff Pri U-Boot (512 KB)
470 * fff40000 - fff7ffff Pri U-Boot Environment (256 KB)
471 * fff00000 - fff3ffff Pri FDT (256KB)
472 * fef00000 - ffefffff Pri OS image (16MB)
473 * f8000000 - feefffff Pri OS Use/Filesystem (111MB)
474 *
475 * f7f80000 - f7ffffff Sec U-Boot (512 KB)
476 * f7f40000 - f7f7ffff Sec U-Boot Environment (256 KB)
477 * f7f00000 - f7f3ffff Sec FDT (256KB)
478 * f6f00000 - f7efffff Sec OS image (16MB)
479 * f0000000 - f6efffff Sec OS Use/Filesystem (111MB)
480 */
481#define CONFIG_UBOOT1_ENV_ADDR MK_STR(0xfff80000)
482#define CONFIG_UBOOT2_ENV_ADDR MK_STR(0xf7f80000)
483#define CONFIG_FDT1_ENV_ADDR MK_STR(0xfff00000)
484#define CONFIG_FDT2_ENV_ADDR MK_STR(0xf7f00000)
485#define CONFIG_OS1_ENV_ADDR MK_STR(0xfef00000)
486#define CONFIG_OS2_ENV_ADDR MK_STR(0xf6f00000)
487
488#define CONFIG_PROG_UBOOT1 \
489 "$download_cmd $loadaddr $ubootfile; " \
490 "if test $? -eq 0; then " \
491 "protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
492 "erase "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
493 "cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; " \
494 "protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
495 "cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; " \
496 "if test $? -ne 0; then " \
497 "echo PROGRAM FAILED; " \
498 "else; " \
499 "echo PROGRAM SUCCEEDED; " \
500 "fi; " \
501 "else; " \
502 "echo DOWNLOAD FAILED; " \
503 "fi;"
504
505#define CONFIG_PROG_UBOOT2 \
506 "$download_cmd $loadaddr $ubootfile; " \
507 "if test $? -eq 0; then " \
508 "protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
509 "erase "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
510 "cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; " \
511 "protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
512 "cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; " \
513 "if test $? -ne 0; then " \
514 "echo PROGRAM FAILED; " \
515 "else; " \
516 "echo PROGRAM SUCCEEDED; " \
517 "fi; " \
518 "else; " \
519 "echo DOWNLOAD FAILED; " \
520 "fi;"
521
522#define CONFIG_BOOT_OS_NET \
523 "$download_cmd $osaddr $osfile; " \
524 "if test $? -eq 0; then " \
525 "if test -n $fdtaddr; then " \
526 "$download_cmd $fdtaddr $fdtfile; " \
527 "if test $? -eq 0; then " \
528 "bootm $osaddr - $fdtaddr; " \
529 "else; " \
530 "echo FDT DOWNLOAD FAILED; " \
531 "fi; " \
532 "else; " \
533 "bootm $osaddr; " \
534 "fi; " \
535 "else; " \
536 "echo OS DOWNLOAD FAILED; " \
537 "fi;"
538
539#define CONFIG_PROG_OS1 \
540 "$download_cmd $osaddr $osfile; " \
541 "if test $? -eq 0; then " \
542 "erase "CONFIG_OS1_ENV_ADDR" +$filesize; " \
543 "cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
544 "cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
545 "if test $? -ne 0; then " \
546 "echo OS PROGRAM FAILED; " \
547 "else; " \
548 "echo OS PROGRAM SUCCEEDED; " \
549 "fi; " \
550 "else; " \
551 "echo OS DOWNLOAD FAILED; " \
552 "fi;"
553
554#define CONFIG_PROG_OS2 \
555 "$download_cmd $osaddr $osfile; " \
556 "if test $? -eq 0; then " \
557 "erase "CONFIG_OS2_ENV_ADDR" +$filesize; " \
558 "cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
559 "cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
560 "if test $? -ne 0; then " \
561 "echo OS PROGRAM FAILED; " \
562 "else; " \
563 "echo OS PROGRAM SUCCEEDED; " \
564 "fi; " \
565 "else; " \
566 "echo OS DOWNLOAD FAILED; " \
567 "fi;"
568
569#define CONFIG_PROG_FDT1 \
570 "$download_cmd $fdtaddr $fdtfile; " \
571 "if test $? -eq 0; then " \
572 "erase "CONFIG_FDT1_ENV_ADDR" +$filesize;" \
573 "cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
574 "cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
575 "if test $? -ne 0; then " \
576 "echo FDT PROGRAM FAILED; " \
577 "else; " \
578 "echo FDT PROGRAM SUCCEEDED; " \
579 "fi; " \
580 "else; " \
581 "echo FDT DOWNLOAD FAILED; " \
582 "fi;"
583
584#define CONFIG_PROG_FDT2 \
585 "$download_cmd $fdtaddr $fdtfile; " \
586 "if test $? -eq 0; then " \
587 "erase "CONFIG_FDT2_ENV_ADDR" +$filesize;" \
588 "cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
589 "cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
590 "if test $? -ne 0; then " \
591 "echo FDT PROGRAM FAILED; " \
592 "else; " \
593 "echo FDT PROGRAM SUCCEEDED; " \
594 "fi; " \
595 "else; " \
596 "echo FDT DOWNLOAD FAILED; " \
597 "fi;"
598
599#define CONFIG_EXTRA_ENV_SETTINGS \
600 "autoload=yes\0" \
601 "download_cmd=tftp\0" \
602 "console_args=console=ttyS0,115200\0" \
603 "root_args=root=/dev/nfs rw\0" \
604 "misc_args=ip=on\0" \
605 "set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
606 "bootfile=/home/user/file\0" \
Peter Tyserc00ac252010-10-22 00:20:26 -0500607 "osfile=/home/user/board.uImage\0" \
608 "fdtfile=/home/user/board.dtb\0" \
Peter Tyserccf0fdd2008-12-17 16:36:23 -0600609 "ubootfile=/home/user/u-boot.bin\0" \
610 "fdtaddr=c00000\0" \
611 "osaddr=0x1000000\0" \
612 "loadaddr=0x1000000\0" \
613 "prog_uboot1="CONFIG_PROG_UBOOT1"\0" \
614 "prog_uboot2="CONFIG_PROG_UBOOT2"\0" \
615 "prog_os1="CONFIG_PROG_OS1"\0" \
616 "prog_os2="CONFIG_PROG_OS2"\0" \
617 "prog_fdt1="CONFIG_PROG_FDT1"\0" \
618 "prog_fdt2="CONFIG_PROG_FDT2"\0" \
619 "bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0" \
620 "bootcmd_flash1=run set_bootargs; " \
621 "bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\
622 "bootcmd_flash2=run set_bootargs; " \
623 "bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\
624 "bootcmd=run bootcmd_flash1\0"
625#endif /* __CONFIG_H */