blob: 50ca6b0bad67a2345992799f5bd24db101e147a6 [file] [log] [blame]
wdenkc6097192002-11-03 00:24:07 +00001/*
2 * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
3 * Andreas Heppel <aheppel@sysgo.de>
4 *
wdenkf07771c2003-05-28 08:06:31 +00005 * (C) Copyright 2002, 2003
wdenkc6097192002-11-03 00:24:07 +00006 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27/*
28 * PCI routines
29 */
30
31#include <common.h>
32
33#ifdef CONFIG_PCI
34
35#include <command.h>
wdenkc6097192002-11-03 00:24:07 +000036#include <asm/processor.h>
37#include <asm/io.h>
38#include <pci.h>
39
wdenkf07771c2003-05-28 08:06:31 +000040#define PCI_HOSE_OP(rw, size, type) \
41int pci_hose_##rw##_config_##size(struct pci_controller *hose, \
42 pci_dev_t dev, \
43 int offset, type value) \
44{ \
45 return hose->rw##_##size(hose, dev, offset, value); \
wdenkc6097192002-11-03 00:24:07 +000046}
47
48PCI_HOSE_OP(read, byte, u8 *)
49PCI_HOSE_OP(read, word, u16 *)
50PCI_HOSE_OP(read, dword, u32 *)
51PCI_HOSE_OP(write, byte, u8)
52PCI_HOSE_OP(write, word, u16)
53PCI_HOSE_OP(write, dword, u32)
54
wdenka1191902005-01-09 17:12:27 +000055#ifndef CONFIG_IXP425
wdenkf07771c2003-05-28 08:06:31 +000056#define PCI_OP(rw, size, type, error_code) \
57int pci_##rw##_config_##size(pci_dev_t dev, int offset, type value) \
58{ \
59 struct pci_controller *hose = pci_bus_to_hose(PCI_BUS(dev)); \
60 \
61 if (!hose) \
62 { \
63 error_code; \
64 return -1; \
65 } \
66 \
67 return pci_hose_##rw##_config_##size(hose, dev, offset, value); \
wdenkc6097192002-11-03 00:24:07 +000068}
69
70PCI_OP(read, byte, u8 *, *value = 0xff)
71PCI_OP(read, word, u16 *, *value = 0xffff)
72PCI_OP(read, dword, u32 *, *value = 0xffffffff)
73PCI_OP(write, byte, u8, )
74PCI_OP(write, word, u16, )
75PCI_OP(write, dword, u32, )
wdenka1191902005-01-09 17:12:27 +000076#endif /* CONFIG_IXP425 */
wdenkc6097192002-11-03 00:24:07 +000077
wdenkf07771c2003-05-28 08:06:31 +000078#define PCI_READ_VIA_DWORD_OP(size, type, off_mask) \
79int pci_hose_read_config_##size##_via_dword(struct pci_controller *hose,\
80 pci_dev_t dev, \
81 int offset, type val) \
82{ \
83 u32 val32; \
84 \
Shinya Kuribayashi815b5bd2007-08-17 12:43:44 +090085 if (pci_hose_read_config_dword(hose, dev, offset & 0xfc, &val32) < 0) { \
86 *val = -1; \
wdenkf07771c2003-05-28 08:06:31 +000087 return -1; \
Shinya Kuribayashi815b5bd2007-08-17 12:43:44 +090088 } \
wdenkf07771c2003-05-28 08:06:31 +000089 \
90 *val = (val32 >> ((offset & (int)off_mask) * 8)); \
91 \
92 return 0; \
wdenkc6097192002-11-03 00:24:07 +000093}
94
wdenkf07771c2003-05-28 08:06:31 +000095#define PCI_WRITE_VIA_DWORD_OP(size, type, off_mask, val_mask) \
96int pci_hose_write_config_##size##_via_dword(struct pci_controller *hose,\
97 pci_dev_t dev, \
98 int offset, type val) \
99{ \
wdenk498b8db2004-04-18 22:26:17 +0000100 u32 val32, mask, ldata, shift; \
wdenkf07771c2003-05-28 08:06:31 +0000101 \
102 if (pci_hose_read_config_dword(hose, dev, offset & 0xfc, &val32) < 0)\
103 return -1; \
104 \
wdenk498b8db2004-04-18 22:26:17 +0000105 shift = ((offset & (int)off_mask) * 8); \
106 ldata = (((unsigned long)val) & val_mask) << shift; \
107 mask = val_mask << shift; \
wdenkf07771c2003-05-28 08:06:31 +0000108 val32 = (val32 & ~mask) | ldata; \
109 \
110 if (pci_hose_write_config_dword(hose, dev, offset & 0xfc, val32) < 0)\
111 return -1; \
112 \
113 return 0; \
wdenkc6097192002-11-03 00:24:07 +0000114}
115
116PCI_READ_VIA_DWORD_OP(byte, u8 *, 0x03)
117PCI_READ_VIA_DWORD_OP(word, u16 *, 0x02)
118PCI_WRITE_VIA_DWORD_OP(byte, u8, 0x03, 0x000000ff)
119PCI_WRITE_VIA_DWORD_OP(word, u16, 0x02, 0x0000ffff)
120
121/*
122 *
123 */
124
125static struct pci_controller* hose_head = NULL;
126
127void pci_register_hose(struct pci_controller* hose)
128{
129 struct pci_controller **phose = &hose_head;
130
131 while(*phose)
132 phose = &(*phose)->next;
133
134 hose->next = NULL;
135
136 *phose = hose;
137}
138
wdenkf07771c2003-05-28 08:06:31 +0000139struct pci_controller *pci_bus_to_hose (int bus)
wdenkc6097192002-11-03 00:24:07 +0000140{
141 struct pci_controller *hose;
142
143 for (hose = hose_head; hose; hose = hose->next)
wdenkf07771c2003-05-28 08:06:31 +0000144 if (bus >= hose->first_busno && bus <= hose->last_busno)
wdenkc6097192002-11-03 00:24:07 +0000145 return hose;
146
Rafal Jaworowski6902df52005-10-17 02:39:53 +0200147 printf("pci_bus_to_hose() failed\n");
wdenkc6097192002-11-03 00:24:07 +0000148 return NULL;
149}
150
wdenka1191902005-01-09 17:12:27 +0000151#ifndef CONFIG_IXP425
wdenkc6097192002-11-03 00:24:07 +0000152pci_dev_t pci_find_devices(struct pci_device_id *ids, int index)
153{
154 struct pci_controller * hose;
155 u16 vendor, device;
156 u8 header_type;
157 pci_dev_t bdf;
158 int i, bus, found_multi = 0;
159
160 for (hose = hose_head; hose; hose = hose->next)
161 {
wdenk42dfe7a2004-03-14 22:25:36 +0000162#ifdef CFG_SCSI_SCAN_BUS_REVERSE
wdenkc6097192002-11-03 00:24:07 +0000163 for (bus = hose->last_busno; bus >= hose->first_busno; bus--)
164#else
165 for (bus = hose->first_busno; bus <= hose->last_busno; bus++)
166#endif
167 for (bdf = PCI_BDF(bus,0,0);
Heiko Schocherf5e0d032006-06-19 11:02:41 +0200168#if defined(CONFIG_ELPPC) || defined(CONFIG_PPMC7XX)
wdenkc6097192002-11-03 00:24:07 +0000169 bdf < PCI_BDF(bus,PCI_MAX_PCI_DEVICES-1,PCI_MAX_PCI_FUNCTIONS-1);
170#else
171 bdf < PCI_BDF(bus+1,0,0);
172#endif
173 bdf += PCI_BDF(0,0,1))
174 {
wdenkf07771c2003-05-28 08:06:31 +0000175 if (!PCI_FUNC(bdf)) {
wdenkc6097192002-11-03 00:24:07 +0000176 pci_read_config_byte(bdf,
177 PCI_HEADER_TYPE,
178 &header_type);
179
180 found_multi = header_type & 0x80;
wdenkf07771c2003-05-28 08:06:31 +0000181 } else {
wdenkc6097192002-11-03 00:24:07 +0000182 if (!found_multi)
183 continue;
184 }
185
186 pci_read_config_word(bdf,
187 PCI_VENDOR_ID,
188 &vendor);
189 pci_read_config_word(bdf,
190 PCI_DEVICE_ID,
191 &device);
192
193 for (i=0; ids[i].vendor != 0; i++)
194 if (vendor == ids[i].vendor &&
195 device == ids[i].device)
196 {
197 if (index <= 0)
198 return bdf;
199
200 index--;
201 }
202 }
203 }
204
205 return (-1);
206}
wdenka1191902005-01-09 17:12:27 +0000207#endif /* CONFIG_IXP425 */
wdenkc6097192002-11-03 00:24:07 +0000208
209pci_dev_t pci_find_device(unsigned int vendor, unsigned int device, int index)
210{
211 static struct pci_device_id ids[2] = {{}, {0, 0}};
212
213 ids[0].vendor = vendor;
214 ids[0].device = device;
215
216 return pci_find_devices(ids, index);
217}
218
219/*
220 *
221 */
222
wdenkf07771c2003-05-28 08:06:31 +0000223unsigned long pci_hose_phys_to_bus (struct pci_controller *hose,
224 unsigned long phys_addr,
225 unsigned long flags)
wdenkc6097192002-11-03 00:24:07 +0000226{
227 struct pci_region *res;
228 unsigned long bus_addr;
229 int i;
230
wdenkf07771c2003-05-28 08:06:31 +0000231 if (!hose) {
232 printf ("pci_hose_phys_to_bus: %s\n", "invalid hose");
wdenkc6097192002-11-03 00:24:07 +0000233 goto Done;
234 }
235
wdenkf07771c2003-05-28 08:06:31 +0000236 for (i = 0; i < hose->region_count; i++) {
wdenkc6097192002-11-03 00:24:07 +0000237 res = &hose->regions[i];
238
239 if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0)
240 continue;
241
242 bus_addr = phys_addr - res->phys_start + res->bus_start;
243
244 if (bus_addr >= res->bus_start &&
wdenkf07771c2003-05-28 08:06:31 +0000245 bus_addr < res->bus_start + res->size) {
wdenkc6097192002-11-03 00:24:07 +0000246 return bus_addr;
247 }
248 }
249
wdenkf07771c2003-05-28 08:06:31 +0000250 printf ("pci_hose_phys_to_bus: %s\n", "invalid physical address");
wdenkc6097192002-11-03 00:24:07 +0000251
wdenkf07771c2003-05-28 08:06:31 +0000252Done:
wdenkc6097192002-11-03 00:24:07 +0000253 return 0;
254}
255
256unsigned long pci_hose_bus_to_phys(struct pci_controller* hose,
257 unsigned long bus_addr,
258 unsigned long flags)
259{
260 struct pci_region *res;
261 int i;
262
wdenkf07771c2003-05-28 08:06:31 +0000263 if (!hose) {
264 printf ("pci_hose_bus_to_phys: %s\n", "invalid hose");
wdenkc6097192002-11-03 00:24:07 +0000265 goto Done;
266 }
267
wdenkf07771c2003-05-28 08:06:31 +0000268 for (i = 0; i < hose->region_count; i++) {
wdenkc6097192002-11-03 00:24:07 +0000269 res = &hose->regions[i];
270
271 if (((res->flags ^ flags) & PCI_REGION_TYPE) != 0)
272 continue;
273
274 if (bus_addr >= res->bus_start &&
wdenkf07771c2003-05-28 08:06:31 +0000275 bus_addr < res->bus_start + res->size) {
wdenkc6097192002-11-03 00:24:07 +0000276 return bus_addr - res->bus_start + res->phys_start;
277 }
278 }
279
wdenkf07771c2003-05-28 08:06:31 +0000280 printf ("pci_hose_bus_to_phys: %s\n", "invalid physical address");
wdenkc6097192002-11-03 00:24:07 +0000281
wdenkf07771c2003-05-28 08:06:31 +0000282Done:
wdenkc6097192002-11-03 00:24:07 +0000283 return 0;
284}
285
286/*
287 *
288 */
289
290int pci_hose_config_device(struct pci_controller *hose,
291 pci_dev_t dev,
292 unsigned long io,
293 unsigned long mem,
294 unsigned long command)
295{
296 unsigned int bar_response, bar_size, bar_value, old_command;
297 unsigned char pin;
298 int bar, found_mem64;
299
wdenka1191902005-01-09 17:12:27 +0000300 debug ("PCI Config: I/O=0x%lx, Memory=0x%lx, Command=0x%lx\n",
wdenkf07771c2003-05-28 08:06:31 +0000301 io, mem, command);
wdenkc6097192002-11-03 00:24:07 +0000302
wdenkf07771c2003-05-28 08:06:31 +0000303 pci_hose_write_config_dword (hose, dev, PCI_COMMAND, 0);
wdenkc6097192002-11-03 00:24:07 +0000304
wdenkf07771c2003-05-28 08:06:31 +0000305 for (bar = PCI_BASE_ADDRESS_0; bar < PCI_BASE_ADDRESS_5; bar += 4) {
306 pci_hose_write_config_dword (hose, dev, bar, 0xffffffff);
307 pci_hose_read_config_dword (hose, dev, bar, &bar_response);
wdenkc6097192002-11-03 00:24:07 +0000308
309 if (!bar_response)
310 continue;
311
312 found_mem64 = 0;
313
314 /* Check the BAR type and set our address mask */
wdenkf07771c2003-05-28 08:06:31 +0000315 if (bar_response & PCI_BASE_ADDRESS_SPACE) {
wdenkc6097192002-11-03 00:24:07 +0000316 bar_size = ~(bar_response & PCI_BASE_ADDRESS_IO_MASK) + 1;
wdenkf07771c2003-05-28 08:06:31 +0000317 /* round up region base address to a multiple of size */
wdenkc6097192002-11-03 00:24:07 +0000318 io = ((io - 1) | (bar_size - 1)) + 1;
wdenkf07771c2003-05-28 08:06:31 +0000319 bar_value = io;
320 /* compute new region base address */
321 io = io + bar_size;
322 } else {
323 if ((bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
324 PCI_BASE_ADDRESS_MEM_TYPE_64)
wdenkc6097192002-11-03 00:24:07 +0000325 found_mem64 = 1;
326
327 bar_size = ~(bar_response & PCI_BASE_ADDRESS_MEM_MASK) + 1;
wdenkc6097192002-11-03 00:24:07 +0000328
wdenkf07771c2003-05-28 08:06:31 +0000329 /* round up region base address to multiple of size */
wdenkc6097192002-11-03 00:24:07 +0000330 mem = ((mem - 1) | (bar_size - 1)) + 1;
wdenkf07771c2003-05-28 08:06:31 +0000331 bar_value = mem;
332 /* compute new region base address */
333 mem = mem + bar_size;
wdenkc6097192002-11-03 00:24:07 +0000334 }
335
336 /* Write it out and update our limit */
wdenkf07771c2003-05-28 08:06:31 +0000337 pci_hose_write_config_dword (hose, dev, bar, bar_value);
wdenkc6097192002-11-03 00:24:07 +0000338
wdenkf07771c2003-05-28 08:06:31 +0000339 if (found_mem64) {
wdenkc6097192002-11-03 00:24:07 +0000340 bar += 4;
wdenkf07771c2003-05-28 08:06:31 +0000341 pci_hose_write_config_dword (hose, dev, bar, 0x00000000);
wdenkc6097192002-11-03 00:24:07 +0000342 }
343 }
344
345 /* Configure Cache Line Size Register */
wdenkf07771c2003-05-28 08:06:31 +0000346 pci_hose_write_config_byte (hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
wdenkc6097192002-11-03 00:24:07 +0000347
348 /* Configure Latency Timer */
wdenkf07771c2003-05-28 08:06:31 +0000349 pci_hose_write_config_byte (hose, dev, PCI_LATENCY_TIMER, 0x80);
wdenkc6097192002-11-03 00:24:07 +0000350
351 /* Disable interrupt line, if device says it wants to use interrupts */
wdenkf07771c2003-05-28 08:06:31 +0000352 pci_hose_read_config_byte (hose, dev, PCI_INTERRUPT_PIN, &pin);
353 if (pin != 0) {
354 pci_hose_write_config_byte (hose, dev, PCI_INTERRUPT_LINE, 0xff);
wdenkc6097192002-11-03 00:24:07 +0000355 }
356
wdenkf07771c2003-05-28 08:06:31 +0000357 pci_hose_read_config_dword (hose, dev, PCI_COMMAND, &old_command);
358 pci_hose_write_config_dword (hose, dev, PCI_COMMAND,
359 (old_command & 0xffff0000) | command);
wdenkc6097192002-11-03 00:24:07 +0000360
361 return 0;
362}
363
364/*
365 *
366 */
367
368struct pci_config_table *pci_find_config(struct pci_controller *hose,
369 unsigned short class,
370 unsigned int vendor,
371 unsigned int device,
372 unsigned int bus,
373 unsigned int dev,
374 unsigned int func)
375{
376 struct pci_config_table *table;
377
wdenkf07771c2003-05-28 08:06:31 +0000378 for (table = hose->config_table; table && table->vendor; table++) {
wdenkc6097192002-11-03 00:24:07 +0000379 if ((table->vendor == PCI_ANY_ID || table->vendor == vendor) &&
380 (table->device == PCI_ANY_ID || table->device == device) &&
381 (table->class == PCI_ANY_ID || table->class == class) &&
382 (table->bus == PCI_ANY_ID || table->bus == bus) &&
383 (table->dev == PCI_ANY_ID || table->dev == dev) &&
wdenkf07771c2003-05-28 08:06:31 +0000384 (table->func == PCI_ANY_ID || table->func == func)) {
wdenkc6097192002-11-03 00:24:07 +0000385 return table;
386 }
387 }
388
389 return NULL;
390}
391
392void pci_cfgfunc_config_device(struct pci_controller *hose,
393 pci_dev_t dev,
394 struct pci_config_table *entry)
395{
396 pci_hose_config_device(hose, dev, entry->priv[0], entry->priv[1], entry->priv[2]);
397}
398
399void pci_cfgfunc_do_nothing(struct pci_controller *hose,
400 pci_dev_t dev, struct pci_config_table *entry)
401{
402}
403
404/*
405 *
406 */
407
wdenkc7de8292002-11-19 11:04:11 +0000408/* HJF: Changed this to return int. I think this is required
409 * to get the correct result when scanning bridges
410 */
411extern int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev);
wdenkc6097192002-11-03 00:24:07 +0000412extern void pciauto_config_init(struct pci_controller *hose);
wdenkc6097192002-11-03 00:24:07 +0000413
414int pci_hose_scan_bus(struct pci_controller *hose, int bus)
415{
416 unsigned int sub_bus, found_multi=0;
417 unsigned short vendor, device, class;
418 unsigned char header_type;
419 struct pci_config_table *cfg;
420 pci_dev_t dev;
421
422 sub_bus = bus;
423
424 for (dev = PCI_BDF(bus,0,0);
425 dev < PCI_BDF(bus,PCI_MAX_PCI_DEVICES-1,PCI_MAX_PCI_FUNCTIONS-1);
426 dev += PCI_BDF(0,0,1))
427 {
wdenkc6097192002-11-03 00:24:07 +0000428 /* Skip our host bridge */
stroese6bb992b2004-12-16 17:48:41 +0000429 if ( dev == PCI_BDF(hose->first_busno,0,0) ) {
430#if defined(CONFIG_PCI_CONFIG_HOST_BRIDGE) /* don't skip host bridge */
431 /*
432 * Only skip hostbridge configuration if "pciconfighost" is not set
433 */
434 if (getenv("pciconfighost") == NULL) {
435 continue; /* Skip our host bridge */
436 }
437#else
438 continue; /* Skip our host bridge */
439#endif
440 }
wdenkc6097192002-11-03 00:24:07 +0000441
442 if (PCI_FUNC(dev) && !found_multi)
443 continue;
444
445 pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, &header_type);
446
447 pci_hose_read_config_word(hose, dev, PCI_VENDOR_ID, &vendor);
448
wdenkc7de8292002-11-19 11:04:11 +0000449 if (vendor != 0xffff && vendor != 0x0000) {
wdenkc6097192002-11-03 00:24:07 +0000450
451 if (!PCI_FUNC(dev))
452 found_multi = header_type & 0x80;
453
wdenka1191902005-01-09 17:12:27 +0000454 debug ("PCI Scan: Found Bus %d, Device %d, Function %d\n",
455 PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev) );
wdenkc6097192002-11-03 00:24:07 +0000456
457 pci_hose_read_config_word(hose, dev, PCI_DEVICE_ID, &device);
458 pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class);
459
460 cfg = pci_find_config(hose, class, vendor, device,
461 PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev));
wdenkc7de8292002-11-19 11:04:11 +0000462 if (cfg) {
wdenkc6097192002-11-03 00:24:07 +0000463 cfg->config_device(hose, dev, cfg);
Kumar Gala3411d112006-01-11 13:27:19 -0600464 sub_bus = max(sub_bus, hose->current_busno);
wdenkc6097192002-11-03 00:24:07 +0000465#ifdef CONFIG_PCI_PNP
wdenkc7de8292002-11-19 11:04:11 +0000466 } else {
467 int n = pciauto_config_device(hose, dev);
468
469 sub_bus = max(sub_bus, n);
wdenkc6097192002-11-03 00:24:07 +0000470#endif
wdenkc7de8292002-11-19 11:04:11 +0000471 }
wdenkc6097192002-11-03 00:24:07 +0000472 if (hose->fixup_irq)
473 hose->fixup_irq(hose, dev);
474
475#ifdef CONFIG_PCI_SCAN_SHOW
476 /* Skip our host bridge */
477 if ( dev != PCI_BDF(hose->first_busno,0,0) ) {
478 unsigned char int_line;
479
480 pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_LINE,
481 &int_line);
482 printf(" %02x %02x %04x %04x %04x %02x\n",
483 PCI_BUS(dev), PCI_DEV(dev), vendor, device, class,
484 int_line);
485 }
486#endif
487 }
488 }
489
490 return sub_bus;
491}
492
493int pci_hose_scan(struct pci_controller *hose)
494{
Ed Swarthout40e81ad2007-07-11 14:51:35 -0500495 /* Start scan at current_busno.
496 * PCIe will start scan at first_busno+1.
497 */
498 /* For legacy support, ensure current>=first */
499 if (hose->first_busno > hose->current_busno)
500 hose->current_busno = hose->first_busno;
wdenkc6097192002-11-03 00:24:07 +0000501#ifdef CONFIG_PCI_PNP
502 pciauto_config_init(hose);
503#endif
Ed Swarthout40e81ad2007-07-11 14:51:35 -0500504 return pci_hose_scan_bus(hose, hose->current_busno);
wdenkc6097192002-11-03 00:24:07 +0000505}
506
stroesead10dd92003-02-14 11:21:23 +0000507void pci_init(void)
508{
509#if defined(CONFIG_PCI_BOOTDELAY)
510 char *s;
511 int i;
512
513 /* wait "pcidelay" ms (if defined)... */
514 s = getenv ("pcidelay");
515 if (s) {
516 int val = simple_strtoul (s, NULL, 10);
517 for (i=0; i<val; i++)
518 udelay (1000);
519 }
520#endif /* CONFIG_PCI_BOOTDELAY */
521
522 /* now call board specific pci_init()... */
523 pci_init_board();
524}
525
wdenkc6097192002-11-03 00:24:07 +0000526#endif /* CONFIG_PCI */