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Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Marek Vasut2e499842010-05-11 04:31:44 +02002/*
3 * Toradex Colibri PXA270 configuration file
4 *
5 * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
Marcel Ziswilerb891d012016-11-16 17:49:23 +01006 * Copyright (C) 2015-2016 Marcel Ziswiler <marcel@ziswiler.com>
Marek Vasut2e499842010-05-11 04:31:44 +02007 */
8
Marcel Ziswiler7c49b522015-03-01 00:53:15 +01009#ifndef __CONFIG_H
10#define __CONFIG_H
Marek Vasut2e499842010-05-11 04:31:44 +020011
12/*
13 * High Level Board Configuration Options
14 */
Marek Vasutabc20ab2011-11-26 07:20:07 +010015#define CONFIG_CPU_PXA27X 1 /* Marvell PXA270 CPU */
Marcel Ziswiler7c49b522015-03-01 00:53:15 +010016/* Avoid overwriting factory configuration block */
17#define CONFIG_BOARD_SIZE_LIMIT 0x40000
Marek Vasut2e499842010-05-11 04:31:44 +020018
Marek Vasut2e499842010-05-11 04:31:44 +020019/*
20 * Environment settings
21 */
Marek Vasutf9f54862011-11-26 07:15:36 +010022#define CONFIG_ENV_OVERWRITE
23#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
Marek Vasut2e499842010-05-11 04:31:44 +020024#define CONFIG_BOOTCOMMAND \
Marcel Ziswiler99d672f2015-03-01 00:53:16 +010025 "if fatload mmc 0 0xa0000000 uImage; then " \
Marek Vasut2e499842010-05-11 04:31:44 +020026 "bootm 0xa0000000; " \
27 "fi; " \
28 "if usb reset && fatload usb 0 0xa0000000 uImage; then " \
29 "bootm 0xa0000000; " \
30 "fi; " \
Marcel Ziswiler99d672f2015-03-01 00:53:16 +010031 "bootm 0xc0000;"
Marek Vasut2e499842010-05-11 04:31:44 +020032#define CONFIG_TIMESTAMP
Marek Vasut2e499842010-05-11 04:31:44 +020033#define CONFIG_CMDLINE_TAG
34#define CONFIG_SETUP_MEMORY_TAGS
Marek Vasut2e499842010-05-11 04:31:44 +020035
36/*
37 * Serial Console Configuration
38 */
Marek Vasut2e499842010-05-11 04:31:44 +020039
40/*
41 * Bootloader Components Configuration
42 */
Marek Vasut2e499842010-05-11 04:31:44 +020043
Marcel Ziswiler3664fa12015-08-16 04:16:36 +020044/* I2C support */
45#ifdef CONFIG_SYS_I2C
Marcel Ziswiler3664fa12015-08-16 04:16:36 +020046#define CONFIG_SYS_I2C_PXA
47#define CONFIG_PXA_STD_I2C
48#define CONFIG_PXA_PWR_I2C
49#define CONFIG_SYS_I2C_SPEED 100000
50#endif
51
Marcel Ziswiler4f9bbd92015-08-16 04:16:35 +020052/* LCD support */
53#ifdef CONFIG_LCD
54#define CONFIG_PXA_LCD
55#define CONFIG_PXA_VGA
Marcel Ziswiler4f9bbd92015-08-16 04:16:35 +020056#define CONFIG_LCD_LOGO
57#endif
58
Marek Vasut2e499842010-05-11 04:31:44 +020059/*
60 * Networking Configuration
Marek Vasut2e499842010-05-11 04:31:44 +020061 */
62#ifdef CONFIG_CMD_NET
Marek Vasut2e499842010-05-11 04:31:44 +020063
Marek Vasut2e499842010-05-11 04:31:44 +020064#define CONFIG_DRIVER_DM9000 1
65#define CONFIG_DM9000_BASE 0x08000000
66#define DM9000_IO (CONFIG_DM9000_BASE)
67#define DM9000_DATA (CONFIG_DM9000_BASE + 4)
68#define CONFIG_NET_RETRY_COUNT 10
69
70#define CONFIG_BOOTP_BOOTFILESIZE
Marek Vasut2e499842010-05-11 04:31:44 +020071#endif
72
Marek Vasut2e499842010-05-11 04:31:44 +020073#define CONFIG_SYS_DEVICE_NULLDEV 1
Marek Vasutf9f54862011-11-26 07:15:36 +010074
Marek Vasut2e499842010-05-11 04:31:44 +020075/*
76 * Clock Configuration
77 */
Marek Vasutf9f54862011-11-26 07:15:36 +010078#define CONFIG_SYS_CPUSPEED 0x290 /* 520MHz */
Marek Vasut2e499842010-05-11 04:31:44 +020079
80/*
Marek Vasut2e499842010-05-11 04:31:44 +020081 * DRAM Map
82 */
Marek Vasut2e499842010-05-11 04:31:44 +020083#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
84#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
85
86#define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */
87#define CONFIG_SYS_DRAM_SIZE 0x04000000 /* 64 MB DRAM */
88
89#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */
90#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
91
Marek Vasutf9f54862011-11-26 07:15:36 +010092#define CONFIG_SYS_LOAD_ADDR PHYS_SDRAM_1
Marek Vasut6ef6eb92010-09-23 09:46:57 +020093#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
Marek Vasutf9f54862011-11-26 07:15:36 +010094#define CONFIG_SYS_INIT_SP_ADDR 0x5c010000
Marek Vasut6ef6eb92010-09-23 09:46:57 +020095
Marek Vasut2e499842010-05-11 04:31:44 +020096/*
97 * NOR FLASH
98 */
99#ifdef CONFIG_CMD_FLASH
100#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
Marcel Ziswilerd8178892015-08-16 04:16:34 +0200101#define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */
Marek Vasut2e499842010-05-11 04:31:44 +0200102#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
103
Marcel Ziswilerd8178892015-08-16 04:16:34 +0200104#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_32BIT
Marek Vasut2e499842010-05-11 04:31:44 +0200105
106#define CONFIG_SYS_MAX_FLASH_SECT (4 + 255)
107#define CONFIG_SYS_MAX_FLASH_BANKS 1
108
Marek Vasutf9f54862011-11-26 07:15:36 +0100109#define CONFIG_SYS_FLASH_ERASE_TOUT (25 * CONFIG_SYS_HZ)
110#define CONFIG_SYS_FLASH_WRITE_TOUT (25 * CONFIG_SYS_HZ)
Marcel Ziswilerd8178892015-08-16 04:16:34 +0200111#define CONFIG_SYS_FLASH_LOCK_TOUT (25 * CONFIG_SYS_HZ)
112#define CONFIG_SYS_FLASH_UNLOCK_TOUT (25 * CONFIG_SYS_HZ)
Marek Vasut2e499842010-05-11 04:31:44 +0200113#endif
114
Marek Vasutf9f54862011-11-26 07:15:36 +0100115#define CONFIG_SYS_MONITOR_BASE 0x0
Marcel Ziswiler7c49b522015-03-01 00:53:15 +0100116#define CONFIG_SYS_MONITOR_LEN 0x40000
Marek Vasut2e499842010-05-11 04:31:44 +0200117
Marcel Ziswiler7c49b522015-03-01 00:53:15 +0100118/* Skip factory configuration block */
Marek Vasut2e499842010-05-11 04:31:44 +0200119
120/*
121 * GPIO settings
122 */
123#define CONFIG_SYS_GPSR0_VAL 0x00000000
124#define CONFIG_SYS_GPSR1_VAL 0x00020000
Marcel Ziswiler44ba7a32015-03-01 00:53:19 +0100125#define CONFIG_SYS_GPSR2_VAL 0x0002c000
Marek Vasut2e499842010-05-11 04:31:44 +0200126#define CONFIG_SYS_GPSR3_VAL 0x00000000
127
128#define CONFIG_SYS_GPCR0_VAL 0x00000000
129#define CONFIG_SYS_GPCR1_VAL 0x00000000
130#define CONFIG_SYS_GPCR2_VAL 0x00000000
131#define CONFIG_SYS_GPCR3_VAL 0x00000000
132
Marcel Ziswiler44ba7a32015-03-01 00:53:19 +0100133#define CONFIG_SYS_GPDR0_VAL 0xc8008000
134#define CONFIG_SYS_GPDR1_VAL 0xfc02a981
135#define CONFIG_SYS_GPDR2_VAL 0x92c3ffff
136#define CONFIG_SYS_GPDR3_VAL 0x0061e804
Marek Vasut2e499842010-05-11 04:31:44 +0200137
Marcel Ziswiler44ba7a32015-03-01 00:53:19 +0100138#define CONFIG_SYS_GAFR0_L_VAL 0x80100000
139#define CONFIG_SYS_GAFR0_U_VAL 0xa5c00010
140#define CONFIG_SYS_GAFR1_L_VAL 0x6992901a
141#define CONFIG_SYS_GAFR1_U_VAL 0xaaa50008
142#define CONFIG_SYS_GAFR2_L_VAL 0xaaaaaaaa
143#define CONFIG_SYS_GAFR2_U_VAL 0x4109a002
144#define CONFIG_SYS_GAFR3_L_VAL 0x54000310
145#define CONFIG_SYS_GAFR3_U_VAL 0x00005401
Marek Vasut2e499842010-05-11 04:31:44 +0200146
147#define CONFIG_SYS_PSSR_VAL 0x30
148
149/*
150 * Clock settings
151 */
152#define CONFIG_SYS_CKEN 0x00500240
153#define CONFIG_SYS_CCCR 0x02000290
154
155/*
156 * Memory settings
157 */
Marcel Ziswiler44ba7a32015-03-01 00:53:19 +0100158#define CONFIG_SYS_MSC0_VAL 0x9ee1c5f2
159#define CONFIG_SYS_MSC1_VAL 0x9ee1f994
160#define CONFIG_SYS_MSC2_VAL 0x9ee19ee1
161#define CONFIG_SYS_MDCNFG_VAL 0x090009c9
162#define CONFIG_SYS_MDREFR_VAL 0x2003a031
163#define CONFIG_SYS_MDMRS_VAL 0x00220022
164#define CONFIG_SYS_FLYCNFG_VAL 0x00010001
Marek Vasut2e499842010-05-11 04:31:44 +0200165#define CONFIG_SYS_SXCNFG_VAL 0x40044004
166
167/*
168 * PCMCIA and CF Interfaces
169 */
Marcel Ziswiler44ba7a32015-03-01 00:53:19 +0100170#define CONFIG_SYS_MECR_VAL 0x00000000
171#define CONFIG_SYS_MCMEM0_VAL 0x00028307
Marek Vasut2e499842010-05-11 04:31:44 +0200172#define CONFIG_SYS_MCMEM1_VAL 0x00014307
Marcel Ziswiler44ba7a32015-03-01 00:53:19 +0100173#define CONFIG_SYS_MCATT0_VAL 0x00038787
Marek Vasut2e499842010-05-11 04:31:44 +0200174#define CONFIG_SYS_MCATT1_VAL 0x0001c787
Marcel Ziswiler44ba7a32015-03-01 00:53:19 +0100175#define CONFIG_SYS_MCIO0_VAL 0x0002830f
Marek Vasut2e499842010-05-11 04:31:44 +0200176#define CONFIG_SYS_MCIO1_VAL 0x0001430f
177
Marek Vasut67a1f002011-11-26 11:27:50 +0100178#include "pxa-common.h"
Marek Vasut2e499842010-05-11 04:31:44 +0200179
Marcel Ziswiler7c49b522015-03-01 00:53:15 +0100180#endif /* __CONFIG_H */