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Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Ashish Kumar77697762017-08-31 16:12:55 +05302/*
3 * Copyright 2017 NXP
Ashish Kumar77697762017-08-31 16:12:55 +05304 */
5
6#ifndef __LS1088A_QDS_H
7#define __LS1088A_QDS_H
8
9#include "ls1088a_common.h"
10
11
Ashish Kumar77697762017-08-31 16:12:55 +053012#ifndef __ASSEMBLY__
13unsigned long get_board_sys_clk(void);
14unsigned long get_board_ddr_clk(void);
15#endif
16
Pankit Garg1a12b4a2018-12-27 04:37:57 +000017#ifdef CONFIG_TFABOOT
18#define CONFIG_SYS_MMC_ENV_DEV 0
Ashish Kumar77697762017-08-31 16:12:55 +053019
Chuanhua Han17489902019-08-01 16:36:57 +080020#define CONFIG_MISC_INIT_R
Pankit Garg1a12b4a2018-12-27 04:37:57 +000021#else
Ashish Kumar77697762017-08-31 16:12:55 +053022#if defined(CONFIG_QSPI_BOOT)
Ashish Kumar91fded62017-11-06 13:18:44 +053023#elif defined(CONFIG_SD_BOOT)
Ashish Kumar91fded62017-11-06 13:18:44 +053024#define CONFIG_SYS_MMC_ENV_DEV 0
Ashish Kumar77697762017-08-31 16:12:55 +053025#endif
Pankit Garg1a12b4a2018-12-27 04:37:57 +000026#endif
Ashish Kumar77697762017-08-31 16:12:55 +053027
Ashish Kumar91fded62017-11-06 13:18:44 +053028#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
Ashish Kumar77697762017-08-31 16:12:55 +053029#define CONFIG_QIXIS_I2C_ACCESS
30#define SYS_NO_FLASH
31
Ashish Kumar91fded62017-11-06 13:18:44 +053032#undef CONFIG_CMD_IMLS
Ashish Kumar77697762017-08-31 16:12:55 +053033#define CONFIG_SYS_CLK_FREQ 100000000
34#define CONFIG_DDR_CLK_FREQ 100000000
35#else
Ashish Kumarc1c597e2018-02-19 14:16:58 +053036#define CONFIG_QIXIS_I2C_ACCESS
Chuanhua Hanc8b2e362019-07-26 20:25:35 +080037#ifndef CONFIG_DM_I2C
Ashish Kumarc1c597e2018-02-19 14:16:58 +053038#define CONFIG_SYS_I2C_EARLY_INIT
Chuanhua Hanc8b2e362019-07-26 20:25:35 +080039#endif
Ashish Kumar77697762017-08-31 16:12:55 +053040#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
41#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
42#endif
43
44#define COUNTER_FREQUENCY_REAL (CONFIG_SYS_CLK_FREQ/4)
45#define COUNTER_FREQUENCY 25000000 /* 25MHz */
46
47#define CONFIG_DIMM_SLOTS_PER_CTLR 1
48
49#define CONFIG_DDR_SPD
50#define CONFIG_DDR_ECC
51#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
52#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
53#define SPD_EEPROM_ADDRESS 0x51
54#define CONFIG_SYS_SPD_BUS_NUM 0
55
56
57/*
58 * IFC Definitions
59 */
60#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
61#define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
62#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
63#define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64*1024*1024)
64
65#define CONFIG_SYS_NOR0_CSPR \
66 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
67 CSPR_PORT_SIZE_16 | \
68 CSPR_MSEL_NOR | \
69 CSPR_V)
70#define CONFIG_SYS_NOR0_CSPR_EARLY \
71 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \
72 CSPR_PORT_SIZE_16 | \
73 CSPR_MSEL_NOR | \
74 CSPR_V)
75#define CONFIG_SYS_NOR1_CSPR \
76 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS) | \
77 CSPR_PORT_SIZE_16 | \
78 CSPR_MSEL_NOR | \
79 CSPR_V)
80#define CONFIG_SYS_NOR1_CSPR_EARLY \
81 (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS_EARLY) | \
82 CSPR_PORT_SIZE_16 | \
83 CSPR_MSEL_NOR | \
84 CSPR_V)
85#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(12)
86#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
87 FTIM0_NOR_TEADC(0x5) | \
Ashish Kumarc1c597e2018-02-19 14:16:58 +053088 FTIM0_NOR_TAVDS(0x6) | \
Ashish Kumar77697762017-08-31 16:12:55 +053089 FTIM0_NOR_TEAHC(0x5))
90#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
Ashish Kumarc1c597e2018-02-19 14:16:58 +053091 FTIM1_NOR_TRAD_NOR(0x1a) | \
Ashish Kumar77697762017-08-31 16:12:55 +053092 FTIM1_NOR_TSEQRAD_NOR(0x13))
Ashish Kumarc1c597e2018-02-19 14:16:58 +053093#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x8) | \
94 FTIM2_NOR_TCH(0x8) | \
95 FTIM2_NOR_TWPH(0xe) | \
Ashish Kumar77697762017-08-31 16:12:55 +053096 FTIM2_NOR_TWP(0x1c))
97#define CONFIG_SYS_NOR_FTIM3 0x04000000
98#define CONFIG_SYS_IFC_CCR 0x01000000
99
100#ifndef SYS_NO_FLASH
Ashish Kumar77697762017-08-31 16:12:55 +0530101#define CONFIG_SYS_FLASH_QUIET_TEST
102#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
103
104#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
105#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
106#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
107#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
108
109#define CONFIG_SYS_FLASH_EMPTY_INFO
110#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE,\
111 CONFIG_SYS_FLASH_BASE + 0x40000000}
112#endif
113#endif
114
115#define CONFIG_NAND_FSL_IFC
116#define CONFIG_SYS_NAND_MAX_ECCPOS 256
117#define CONFIG_SYS_NAND_MAX_OOBFREE 2
118
119#define CONFIG_SYS_NAND_CSPR_EXT (0x0)
120#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
121 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
122 | CSPR_MSEL_NAND /* MSEL = NAND */ \
123 | CSPR_V)
124#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
125
126#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
127 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
128 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
129 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
130 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
131 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
132 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
133
134#define CONFIG_SYS_NAND_ONFI_DETECTION
135
136/* ONFI NAND Flash mode0 Timing Params */
137#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
138 FTIM0_NAND_TWP(0x18) | \
139 FTIM0_NAND_TWCHT(0x07) | \
140 FTIM0_NAND_TWH(0x0a))
141#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
142 FTIM1_NAND_TWBE(0x39) | \
143 FTIM1_NAND_TRR(0x0e) | \
144 FTIM1_NAND_TRP(0x18))
145#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
146 FTIM2_NAND_TREH(0x0a) | \
147 FTIM2_NAND_TWHRE(0x1e))
148#define CONFIG_SYS_NAND_FTIM3 0x0
149
150#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
151#define CONFIG_SYS_MAX_NAND_DEVICE 1
152#define CONFIG_MTD_NAND_VERIFY_WRITE
153#define CONFIG_CMD_NAND
154
155#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
156
157#define CONFIG_FSL_QIXIS
158#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
159#define QIXIS_LBMAP_SWITCH 6
160#define QIXIS_QMAP_MASK 0xe0
161#define QIXIS_QMAP_SHIFT 5
162#define QIXIS_LBMAP_MASK 0x0f
163#define QIXIS_LBMAP_SHIFT 0
164#define QIXIS_LBMAP_DFLTBANK 0x0e
165#define QIXIS_LBMAP_ALTBANK 0x2e
166#define QIXIS_LBMAP_SD 0x00
Ashish Kumar6c8945e2018-01-17 12:16:37 +0530167#define QIXIS_LBMAP_EMMC 0x00
168#define QIXIS_LBMAP_IFC 0x00
Ashish Kumar77697762017-08-31 16:12:55 +0530169#define QIXIS_LBMAP_SD_QSPI 0x0e
170#define QIXIS_LBMAP_QSPI 0x0e
Ashish Kumar6c8945e2018-01-17 12:16:37 +0530171#define QIXIS_RCW_SRC_IFC 0x25
Ashish Kumar77697762017-08-31 16:12:55 +0530172#define QIXIS_RCW_SRC_SD 0x40
Ashish Kumar6c8945e2018-01-17 12:16:37 +0530173#define QIXIS_RCW_SRC_EMMC 0x41
Ashish Kumar77697762017-08-31 16:12:55 +0530174#define QIXIS_RCW_SRC_QSPI 0x62
175#define QIXIS_RST_CTL_RESET 0x41
176#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
177#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
178#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
179#define QIXIS_RST_FORCE_MEM 0x01
180#define QIXIS_STAT_PRES1 0xb
181#define QIXIS_SDID_MASK 0x07
182#define QIXIS_ESDHC_NO_ADAPTER 0x7
183
184#define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
185#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
186 | CSPR_PORT_SIZE_8 \
187 | CSPR_MSEL_GPCM \
188 | CSPR_V)
189#define SYS_FPGA_CSPR_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
190 | CSPR_PORT_SIZE_8 \
191 | CSPR_MSEL_GPCM \
192 | CSPR_V)
193
Ashish Kumarb555e292018-02-19 14:14:09 +0530194#define SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
Ashish Kumar91fded62017-11-06 13:18:44 +0530195#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
Ashish Kumar77697762017-08-31 16:12:55 +0530196#define CONFIG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(0)
197#else
198#define CONFIG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(12)
199#endif
200/* QIXIS Timing parameters*/
201#define SYS_FPGA_CS_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
202 FTIM0_GPCM_TEADC(0x0e) | \
203 FTIM0_GPCM_TEAHC(0x0e))
204#define SYS_FPGA_CS_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
205 FTIM1_GPCM_TRAD(0x3f))
206#define SYS_FPGA_CS_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
207 FTIM2_GPCM_TCH(0xf) | \
208 FTIM2_GPCM_TWP(0x3E))
209#define SYS_FPGA_CS_FTIM3 0x0
210
Pankit Garg1a12b4a2018-12-27 04:37:57 +0000211#ifdef CONFIG_TFABOOT
212#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
213#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
214#define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR
215#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
216#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
217#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
218#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
219#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
220#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
221#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
222#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR_EARLY
223#define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR1_CSPR
224#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK_EARLY
225#define CONFIG_SYS_AMASK1_FINAL CONFIG_SYS_NOR_AMASK
226#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
227#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
228#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
229#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
230#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
231#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
232#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
233#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
234#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
235#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
236#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
237#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
238#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
239#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
240#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
241#define CONFIG_SYS_CSPR3_FINAL SYS_FPGA_CSPR_FINAL
242#define CONFIG_SYS_AMASK3 SYS_FPGA_AMASK
243#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
244#define CONFIG_SYS_CS3_FTIM0 SYS_FPGA_CS_FTIM0
245#define CONFIG_SYS_CS3_FTIM1 SYS_FPGA_CS_FTIM1
246#define CONFIG_SYS_CS3_FTIM2 SYS_FPGA_CS_FTIM2
247#define CONFIG_SYS_CS3_FTIM3 SYS_FPGA_CS_FTIM3
248#else
Ashish Kumar77697762017-08-31 16:12:55 +0530249#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
250#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
251#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
252#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
253#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
254#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
255#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
256#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
257#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
258#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_FPGA_CSPR_EXT
259#define CONFIG_SYS_CSPR2 CONFIG_SYS_FPGA_CSPR
260#define CONFIG_SYS_CSPR2_FINAL SYS_FPGA_CSPR_FINAL
Ashish Kumarb555e292018-02-19 14:14:09 +0530261#define CONFIG_SYS_AMASK2 SYS_FPGA_AMASK
Ashish Kumar77697762017-08-31 16:12:55 +0530262#define CONFIG_SYS_CSOR2 CONFIG_SYS_FPGA_CSOR
263#define CONFIG_SYS_CS2_FTIM0 SYS_FPGA_CS_FTIM0
264#define CONFIG_SYS_CS2_FTIM1 SYS_FPGA_CS_FTIM1
265#define CONFIG_SYS_CS2_FTIM2 SYS_FPGA_CS_FTIM2
266#define CONFIG_SYS_CS2_FTIM3 SYS_FPGA_CS_FTIM3
267#else
268#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
269#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
270#define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR
271#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
272#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
273#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
274#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
275#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
276#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
277#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
278#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR_EARLY
279#define CONFIG_SYS_CSPR1_FINAL CONFIG_SYS_NOR1_CSPR
280#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK_EARLY
281#define CONFIG_SYS_AMASK1_FINAL CONFIG_SYS_NOR_AMASK
282#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
283#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
284#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
285#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
286#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
287#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
288#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
289#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
290#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
291#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
292#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
293#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
294#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
295#define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
296#define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
Ashish Kumarb555e292018-02-19 14:14:09 +0530297#define CONFIG_SYS_CSPR3_FINAL SYS_FPGA_CSPR_FINAL
298#define CONFIG_SYS_AMASK3 SYS_FPGA_AMASK
Ashish Kumar77697762017-08-31 16:12:55 +0530299#define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
Ashish Kumarb555e292018-02-19 14:14:09 +0530300#define CONFIG_SYS_CS3_FTIM0 SYS_FPGA_CS_FTIM0
301#define CONFIG_SYS_CS3_FTIM1 SYS_FPGA_CS_FTIM1
302#define CONFIG_SYS_CS3_FTIM2 SYS_FPGA_CS_FTIM2
303#define CONFIG_SYS_CS3_FTIM3 SYS_FPGA_CS_FTIM3
Ashish Kumar77697762017-08-31 16:12:55 +0530304#endif
Pankit Garg1a12b4a2018-12-27 04:37:57 +0000305#endif
Ashish Kumar77697762017-08-31 16:12:55 +0530306
307#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
308
309/*
310 * I2C bus multiplexer
311 */
312#define I2C_MUX_PCA_ADDR_PRI 0x77
313#define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */
314#define I2C_RETIMER_ADDR 0x18
315#define I2C_RETIMER_ADDR2 0x19
316#define I2C_MUX_CH_DEFAULT 0x8
317#define I2C_MUX_CH5 0xD
318
Rajesh Bhagat23a12cb2018-01-17 16:13:05 +0530319#define I2C_MUX_CH_VOL_MONITOR 0xA
320
321/* Voltage monitor on channel 2*/
322#define I2C_VOL_MONITOR_ADDR 0x63
323#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
324#define I2C_VOL_MONITOR_BUS_V_OVF 0x1
325#define I2C_VOL_MONITOR_BUS_V_SHIFT 3
Rajesh Bhagatef0789b2018-01-17 16:13:09 +0530326#define I2C_SVDD_MONITOR_ADDR 0x4F
327
328#define CONFIG_VID_FLS_ENV "ls1088aqds_vdd_mv"
329#define CONFIG_VID
330
331/* The lowest and highest voltage allowed for LS1088AQDS */
332#define VDD_MV_MIN 819
333#define VDD_MV_MAX 1212
334
335#define CONFIG_VOL_MONITOR_LTC3882_SET
336#define CONFIG_VOL_MONITOR_LTC3882_READ
Rajesh Bhagat23a12cb2018-01-17 16:13:05 +0530337
338/* PM Bus commands code for LTC3882*/
339#define PMBUS_CMD_PAGE 0x0
340#define PMBUS_CMD_READ_VOUT 0x8B
341#define PMBUS_CMD_PAGE_PLUS_WRITE 0x05
342#define PMBUS_CMD_VOUT_COMMAND 0x21
343
344#define PWM_CHANNEL0 0x0
345
Ashish Kumar77697762017-08-31 16:12:55 +0530346/*
347* RTC configuration
348*/
349#define RTC
Ashish Kumar77697762017-08-31 16:12:55 +0530350#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/
Ashish Kumar77697762017-08-31 16:12:55 +0530351
352/* EEPROM */
353#define CONFIG_ID_EEPROM
354#define CONFIG_SYS_I2C_EEPROM_NXID
355#define CONFIG_SYS_EEPROM_BUS_NUM 0
356#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
357#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
358#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
359#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
360
361/* QSPI device */
Pankit Garg1a12b4a2018-12-27 04:37:57 +0000362#if defined(CONFIG_TFABOOT) || \
363 defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
Ashish Kumar77697762017-08-31 16:12:55 +0530364#define FSL_QSPI_FLASH_SIZE (1 << 26)
365#define FSL_QSPI_FLASH_NUM 2
366
367#endif
368
369#ifdef CONFIG_FSL_DSPI
370#define CONFIG_SPI_FLASH_STMICRO
371#define CONFIG_SPI_FLASH_SST
372#define CONFIG_SPI_FLASH_EON
Pankit Garg1a12b4a2018-12-27 04:37:57 +0000373#if !defined(CONFIG_TFABOOT) && \
374 !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
Ashish Kumar77697762017-08-31 16:12:55 +0530375#endif
376#endif
377
378#define CONFIG_CMD_MEMINFO
Ashish Kumar77697762017-08-31 16:12:55 +0530379#define CONFIG_SYS_MEMTEST_START 0x80000000
380#define CONFIG_SYS_MEMTEST_END 0x9fffffff
381
Ashish Kumar91fded62017-11-06 13:18:44 +0530382#ifdef CONFIG_SPL_BUILD
383#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
384#else
Ashish Kumar77697762017-08-31 16:12:55 +0530385#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
Ashish Kumar91fded62017-11-06 13:18:44 +0530386#endif
Ashish Kumar77697762017-08-31 16:12:55 +0530387
388#define CONFIG_FSL_MEMAC
389
390/* MMC */
Ashish Kumar77697762017-08-31 16:12:55 +0530391#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
392#define CONFIG_ESDHC_DETECT_QUIRK ((readb(QIXIS_BASE + QIXIS_STAT_PRES1) & \
393 QIXIS_SDID_MASK) != QIXIS_ESDHC_NO_ADAPTER)
394
395/* Initial environment variables */
Udit Agarwal5536c3c2019-11-07 16:11:32 +0000396#ifdef CONFIG_NXP_ESBC
Udit Agarwal30c41d22017-11-22 09:01:26 +0530397#undef CONFIG_EXTRA_ENV_SETTINGS
398#define CONFIG_EXTRA_ENV_SETTINGS \
399 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
400 "loadaddr=0x90100000\0" \
401 "kernel_addr=0x100000\0" \
402 "ramdisk_addr=0x800000\0" \
403 "ramdisk_size=0x2000000\0" \
404 "fdt_high=0xa0000000\0" \
405 "initrd_high=0xffffffffffffffff\0" \
406 "kernel_start=0x1000000\0" \
407 "kernel_load=0xa0000000\0" \
408 "kernel_size=0x2800000\0" \
409 "mcinitcmd=sf probe 0:0;sf read 0xa0a00000 0xa00000 0x100000;" \
410 "sf read 0xa0700000 0x700000 0x4000; esbc_validate 0xa0700000;" \
411 "sf read 0xa0e00000 0xe00000 0x100000;" \
412 "sf read 0xa0740000 0x740000 0x4000;esbc_validate 0xa0740000;" \
413 "fsl_mc start mc 0xa0a00000 0xa0e00000\0" \
414 "mcmemsize=0x70000000 \0"
Udit Agarwal5536c3c2019-11-07 16:11:32 +0000415#else /* if !(CONFIG_NXP_ESBC) */
Pankit Garg1a12b4a2018-12-27 04:37:57 +0000416#ifdef CONFIG_TFABOOT
417#define QSPI_MC_INIT_CMD \
418 "sf probe 0:0;sf read 0x80000000 0xA00000 0x100000;" \
419 "sf read 0x80100000 0xE00000 0x100000;" \
420 "fsl_mc start mc 0x80000000 0x80100000\0"
421#define SD_MC_INIT_CMD \
422 "mmcinfo;mmc read 0x80000000 0x5000 0x800;" \
423 "mmc read 0x80100000 0x7000 0x800;" \
424 "fsl_mc start mc 0x80000000 0x80100000\0"
425#define IFC_MC_INIT_CMD \
426 "fsl_mc start mc 0x580A00000 0x580E00000\0"
427
428#undef CONFIG_EXTRA_ENV_SETTINGS
429#define CONFIG_EXTRA_ENV_SETTINGS \
430 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
431 "loadaddr=0x90100000\0" \
432 "kernel_addr=0x100000\0" \
433 "kernel_addr_sd=0x800\0" \
434 "ramdisk_addr=0x800000\0" \
435 "ramdisk_size=0x2000000\0" \
436 "fdt_high=0xa0000000\0" \
437 "initrd_high=0xffffffffffffffff\0" \
438 "kernel_start=0x1000000\0" \
439 "kernel_start_sd=0x8000\0" \
440 "kernel_load=0xa0000000\0" \
441 "kernel_size=0x2800000\0" \
442 "kernel_size_sd=0x14000\0" \
443 "mcinitcmd=sf probe 0:0;sf read 0x80000000 0xA00000 0x100000;" \
444 "sf read 0x80100000 0xE00000 0x100000;" \
445 "fsl_mc start mc 0x80000000 0x80100000\0" \
446 "mcmemsize=0x70000000 \0"
447#define QSPI_NOR_BOOTCOMMAND "sf probe 0:0;" \
448 "sf read 0x80001000 0xd00000 0x100000;"\
449 " fsl_mc lazyapply dpl 0x80001000 &&" \
450 " sf read $kernel_load $kernel_start" \
451 " $kernel_size && bootm $kernel_load"
452#define SD_BOOTCOMMAND "mmcinfo;mmc read 0x80001000 0x6800 0x800;"\
453 " fsl_mc lazyapply dpl 0x80001000 &&" \
454 " mmc read $kernel_load $kernel_start_sd" \
455 " $kernel_size_sd && bootm $kernel_load"
456#define IFC_NOR_BOOTCOMMAND "fsl_mc lazyapply dpl 0x580d00000 &&" \
457 " cp.b $kernel_start $kernel_load" \
458 " $kernel_size && bootm $kernel_load"
459#else
Ashish Kumar77697762017-08-31 16:12:55 +0530460#if defined(CONFIG_QSPI_BOOT)
461#undef CONFIG_EXTRA_ENV_SETTINGS
462#define CONFIG_EXTRA_ENV_SETTINGS \
463 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
464 "loadaddr=0x90100000\0" \
465 "kernel_addr=0x100000\0" \
466 "ramdisk_addr=0x800000\0" \
467 "ramdisk_size=0x2000000\0" \
468 "fdt_high=0xa0000000\0" \
469 "initrd_high=0xffffffffffffffff\0" \
470 "kernel_start=0x1000000\0" \
471 "kernel_load=0xa0000000\0" \
472 "kernel_size=0x2800000\0" \
473 "mcinitcmd=sf probe 0:0;sf read 0x80000000 0xA00000 0x100000;" \
474 "sf read 0x80100000 0xE00000 0x100000;" \
475 "fsl_mc start mc 0x80000000 0x80100000\0" \
476 "mcmemsize=0x70000000 \0"
Ashish Kumar91fded62017-11-06 13:18:44 +0530477#elif defined(CONFIG_SD_BOOT)
478#undef CONFIG_EXTRA_ENV_SETTINGS
479#define CONFIG_EXTRA_ENV_SETTINGS \
480 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
481 "loadaddr=0x90100000\0" \
482 "kernel_addr=0x800\0" \
483 "ramdisk_addr=0x800000\0" \
484 "ramdisk_size=0x2000000\0" \
485 "fdt_high=0xa0000000\0" \
486 "initrd_high=0xffffffffffffffff\0" \
487 "kernel_start=0x8000\0" \
488 "kernel_load=0xa0000000\0" \
489 "kernel_size=0x14000\0" \
490 "mcinitcmd=mmcinfo;mmc read 0x80000000 0x5000 0x800;" \
491 "mmc read 0x80100000 0x7000 0x800;" \
492 "fsl_mc start mc 0x80000000 0x80100000\0" \
493 "mcmemsize=0x70000000 \0"
Ashish Kumar77697762017-08-31 16:12:55 +0530494#else /* NOR BOOT */
495#undef CONFIG_EXTRA_ENV_SETTINGS
496#define CONFIG_EXTRA_ENV_SETTINGS \
497 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
498 "loadaddr=0x90100000\0" \
499 "kernel_addr=0x100000\0" \
500 "ramdisk_addr=0x800000\0" \
501 "ramdisk_size=0x2000000\0" \
502 "fdt_high=0xa0000000\0" \
503 "initrd_high=0xffffffffffffffff\0" \
504 "kernel_start=0x1000000\0" \
505 "kernel_load=0xa0000000\0" \
506 "kernel_size=0x2800000\0" \
507 "mcinitcmd=fsl_mc start mc 0x580A00000 0x580E00000\0" \
508 "mcmemsize=0x70000000 \0"
509#endif
Pankit Garg1a12b4a2018-12-27 04:37:57 +0000510#endif /* CONFIG_TFABOOT */
Udit Agarwal5536c3c2019-11-07 16:11:32 +0000511#endif /* CONFIG_NXP_ESBC */
Ashish Kumar77697762017-08-31 16:12:55 +0530512
513#ifdef CONFIG_FSL_MC_ENET
514#define CONFIG_FSL_MEMAC
515#define CONFIG_PHYLIB
516#define CONFIG_PHYLIB_10G
517#define CONFIG_PHY_VITESSE
518#define CONFIG_PHY_REALTEK
519#define CONFIG_PHY_TERANETICS
520#define RGMII_PHY1_ADDR 0x1
521#define RGMII_PHY2_ADDR 0x2
522#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
523#define SGMII_CARD_PORT2_PHY_ADDR 0x1d
524#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
525#define SGMII_CARD_PORT4_PHY_ADDR 0x1F
526
527#define XQSGMII_CARD_PHY1_PORT0_ADDR 0x0
528#define XQSGMII_CARD_PHY1_PORT1_ADDR 0x1
529#define XQSGMII_CARD_PHY1_PORT2_ADDR 0x2
530#define XQSGMII_CARD_PHY1_PORT3_ADDR 0x3
531#define XQSGMII_CARD_PHY2_PORT0_ADDR 0x4
532#define XQSGMII_CARD_PHY2_PORT1_ADDR 0x5
533#define XQSGMII_CARD_PHY2_PORT2_ADDR 0x6
534#define XQSGMII_CARD_PHY2_PORT3_ADDR 0x7
535#define XQSGMII_CARD_PHY3_PORT0_ADDR 0x8
536#define XQSGMII_CARD_PHY3_PORT1_ADDR 0x9
537#define XQSGMII_CARD_PHY3_PORT2_ADDR 0xa
538#define XQSGMII_CARD_PHY3_PORT3_ADDR 0xb
539#define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc
540#define XQSGMII_CARD_PHY4_PORT1_ADDR 0xd
541#define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe
542#define XQSGMII_CARD_PHY4_PORT3_ADDR 0xf
543
Ashish Kumar77697762017-08-31 16:12:55 +0530544#define CONFIG_ETHPRIME "DPMAC1@xgmii"
545#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
546
547#endif
548
Ashish Kumar77697762017-08-31 16:12:55 +0530549#define BOOT_TARGET_DEVICES(func) \
550 func(USB, usb, 0) \
551 func(MMC, mmc, 0) \
552 func(SCSI, scsi, 0) \
553 func(DHCP, dhcp, na)
554#include <config_distro_bootcmd.h>
555
556#include <asm/fsl_secure_boot.h>
557
558#endif /* __LS1088A_QDS_H */