Stefan Roese | 5bef6fd | 2014-11-07 13:50:31 +0100 | [diff] [blame^] | 1 | /* |
| 2 | * Designware master SPI core controller driver |
| 3 | * |
| 4 | * Copyright (C) 2014 Stefan Roese <sr@denx.de> |
| 5 | * |
| 6 | * Very loosly based on the Linux driver version which is: |
| 7 | * Copyright (c) 2009, Intel Corporation. |
| 8 | * |
| 9 | * SPDX-License-Identifier: GPL-2.0 |
| 10 | */ |
| 11 | |
| 12 | #include <common.h> |
| 13 | #include <dm.h> |
| 14 | #include <errno.h> |
| 15 | #include <malloc.h> |
| 16 | #include <spi.h> |
| 17 | #include <fdtdec.h> |
| 18 | #include <linux/compat.h> |
| 19 | #include <asm/io.h> |
| 20 | |
| 21 | DECLARE_GLOBAL_DATA_PTR; |
| 22 | |
| 23 | /* Register offsets */ |
| 24 | #define DW_SPI_CTRL0 0x00 |
| 25 | #define DW_SPI_CTRL1 0x04 |
| 26 | #define DW_SPI_SSIENR 0x08 |
| 27 | #define DW_SPI_MWCR 0x0c |
| 28 | #define DW_SPI_SER 0x10 |
| 29 | #define DW_SPI_BAUDR 0x14 |
| 30 | #define DW_SPI_TXFLTR 0x18 |
| 31 | #define DW_SPI_RXFLTR 0x1c |
| 32 | #define DW_SPI_TXFLR 0x20 |
| 33 | #define DW_SPI_RXFLR 0x24 |
| 34 | #define DW_SPI_SR 0x28 |
| 35 | #define DW_SPI_IMR 0x2c |
| 36 | #define DW_SPI_ISR 0x30 |
| 37 | #define DW_SPI_RISR 0x34 |
| 38 | #define DW_SPI_TXOICR 0x38 |
| 39 | #define DW_SPI_RXOICR 0x3c |
| 40 | #define DW_SPI_RXUICR 0x40 |
| 41 | #define DW_SPI_MSTICR 0x44 |
| 42 | #define DW_SPI_ICR 0x48 |
| 43 | #define DW_SPI_DMACR 0x4c |
| 44 | #define DW_SPI_DMATDLR 0x50 |
| 45 | #define DW_SPI_DMARDLR 0x54 |
| 46 | #define DW_SPI_IDR 0x58 |
| 47 | #define DW_SPI_VERSION 0x5c |
| 48 | #define DW_SPI_DR 0x60 |
| 49 | |
| 50 | /* Bit fields in CTRLR0 */ |
| 51 | #define SPI_DFS_OFFSET 0 |
| 52 | |
| 53 | #define SPI_FRF_OFFSET 4 |
| 54 | #define SPI_FRF_SPI 0x0 |
| 55 | #define SPI_FRF_SSP 0x1 |
| 56 | #define SPI_FRF_MICROWIRE 0x2 |
| 57 | #define SPI_FRF_RESV 0x3 |
| 58 | |
| 59 | #define SPI_MODE_OFFSET 6 |
| 60 | #define SPI_SCPH_OFFSET 6 |
| 61 | #define SPI_SCOL_OFFSET 7 |
| 62 | |
| 63 | #define SPI_TMOD_OFFSET 8 |
| 64 | #define SPI_TMOD_MASK (0x3 << SPI_TMOD_OFFSET) |
| 65 | #define SPI_TMOD_TR 0x0 /* xmit & recv */ |
| 66 | #define SPI_TMOD_TO 0x1 /* xmit only */ |
| 67 | #define SPI_TMOD_RO 0x2 /* recv only */ |
| 68 | #define SPI_TMOD_EPROMREAD 0x3 /* eeprom read mode */ |
| 69 | |
| 70 | #define SPI_SLVOE_OFFSET 10 |
| 71 | #define SPI_SRL_OFFSET 11 |
| 72 | #define SPI_CFS_OFFSET 12 |
| 73 | |
| 74 | /* Bit fields in SR, 7 bits */ |
| 75 | #define SR_MASK 0x7f /* cover 7 bits */ |
| 76 | #define SR_BUSY (1 << 0) |
| 77 | #define SR_TF_NOT_FULL (1 << 1) |
| 78 | #define SR_TF_EMPT (1 << 2) |
| 79 | #define SR_RF_NOT_EMPT (1 << 3) |
| 80 | #define SR_RF_FULL (1 << 4) |
| 81 | #define SR_TX_ERR (1 << 5) |
| 82 | #define SR_DCOL (1 << 6) |
| 83 | |
| 84 | #define RX_TIMEOUT 1000 |
| 85 | |
| 86 | struct dw_spi_platdata { |
| 87 | s32 frequency; /* Default clock frequency, -1 for none */ |
| 88 | void __iomem *regs; |
| 89 | }; |
| 90 | |
| 91 | struct dw_spi_priv { |
| 92 | void __iomem *regs; |
| 93 | unsigned int freq; /* Default frequency */ |
| 94 | unsigned int mode; |
| 95 | |
| 96 | int bits_per_word; |
| 97 | u8 cs; /* chip select pin */ |
| 98 | u8 n_bytes; /* current is a 1/2/4 byte op */ |
| 99 | u8 tmode; /* TR/TO/RO/EEPROM */ |
| 100 | u8 type; /* SPI/SSP/MicroWire */ |
| 101 | int len; |
| 102 | |
| 103 | u32 fifo_len; /* depth of the FIFO buffer */ |
| 104 | void *tx; |
| 105 | void *tx_end; |
| 106 | void *rx; |
| 107 | void *rx_end; |
| 108 | }; |
| 109 | |
| 110 | static inline u32 dw_readl(struct dw_spi_priv *priv, u32 offset) |
| 111 | { |
| 112 | return __raw_readl(priv->regs + offset); |
| 113 | } |
| 114 | |
| 115 | static inline void dw_writel(struct dw_spi_priv *priv, u32 offset, u32 val) |
| 116 | { |
| 117 | __raw_writel(val, priv->regs + offset); |
| 118 | } |
| 119 | |
| 120 | static inline u16 dw_readw(struct dw_spi_priv *priv, u32 offset) |
| 121 | { |
| 122 | return __raw_readw(priv->regs + offset); |
| 123 | } |
| 124 | |
| 125 | static inline void dw_writew(struct dw_spi_priv *priv, u32 offset, u16 val) |
| 126 | { |
| 127 | __raw_writew(val, priv->regs + offset); |
| 128 | } |
| 129 | |
| 130 | static int dw_spi_ofdata_to_platdata(struct udevice *bus) |
| 131 | { |
| 132 | struct dw_spi_platdata *plat = bus->platdata; |
| 133 | const void *blob = gd->fdt_blob; |
| 134 | int node = bus->of_offset; |
| 135 | |
| 136 | plat->regs = (struct dw_spi *)fdtdec_get_addr(blob, node, "reg"); |
| 137 | |
| 138 | /* Use 500KHz as a suitable default */ |
| 139 | plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency", |
| 140 | 500000); |
| 141 | debug("%s: regs=%p max-frequency=%d\n", __func__, plat->regs, |
| 142 | plat->frequency); |
| 143 | |
| 144 | return 0; |
| 145 | } |
| 146 | |
| 147 | static inline void spi_enable_chip(struct dw_spi_priv *priv, int enable) |
| 148 | { |
| 149 | dw_writel(priv, DW_SPI_SSIENR, (enable ? 1 : 0)); |
| 150 | } |
| 151 | |
| 152 | /* Restart the controller, disable all interrupts, clean rx fifo */ |
| 153 | static void spi_hw_init(struct dw_spi_priv *priv) |
| 154 | { |
| 155 | spi_enable_chip(priv, 0); |
| 156 | dw_writel(priv, DW_SPI_IMR, 0xff); |
| 157 | spi_enable_chip(priv, 1); |
| 158 | |
| 159 | /* |
| 160 | * Try to detect the FIFO depth if not set by interface driver, |
| 161 | * the depth could be from 2 to 256 from HW spec |
| 162 | */ |
| 163 | if (!priv->fifo_len) { |
| 164 | u32 fifo; |
| 165 | |
| 166 | for (fifo = 2; fifo <= 257; fifo++) { |
| 167 | dw_writew(priv, DW_SPI_TXFLTR, fifo); |
| 168 | if (fifo != dw_readw(priv, DW_SPI_TXFLTR)) |
| 169 | break; |
| 170 | } |
| 171 | |
| 172 | priv->fifo_len = (fifo == 257) ? 0 : fifo; |
| 173 | dw_writew(priv, DW_SPI_TXFLTR, 0); |
| 174 | } |
| 175 | debug("%s: fifo_len=%d\n", __func__, priv->fifo_len); |
| 176 | } |
| 177 | |
| 178 | static int dw_spi_probe(struct udevice *bus) |
| 179 | { |
| 180 | struct dw_spi_platdata *plat = dev_get_platdata(bus); |
| 181 | struct dw_spi_priv *priv = dev_get_priv(bus); |
| 182 | |
| 183 | priv->regs = plat->regs; |
| 184 | priv->freq = plat->frequency; |
| 185 | |
| 186 | /* Currently only bits_per_word == 8 supported */ |
| 187 | priv->bits_per_word = 8; |
| 188 | priv->n_bytes = 1; |
| 189 | |
| 190 | priv->tmode = 0; /* Tx & Rx */ |
| 191 | |
| 192 | /* Basic HW init */ |
| 193 | spi_hw_init(priv); |
| 194 | |
| 195 | return 0; |
| 196 | } |
| 197 | |
| 198 | /* Return the max entries we can fill into tx fifo */ |
| 199 | static inline u32 tx_max(struct dw_spi_priv *priv) |
| 200 | { |
| 201 | u32 tx_left, tx_room, rxtx_gap; |
| 202 | |
| 203 | tx_left = (priv->tx_end - priv->tx) / priv->n_bytes; |
| 204 | tx_room = priv->fifo_len - dw_readw(priv, DW_SPI_TXFLR); |
| 205 | |
| 206 | /* |
| 207 | * Another concern is about the tx/rx mismatch, we |
| 208 | * though to use (priv->fifo_len - rxflr - txflr) as |
| 209 | * one maximum value for tx, but it doesn't cover the |
| 210 | * data which is out of tx/rx fifo and inside the |
| 211 | * shift registers. So a control from sw point of |
| 212 | * view is taken. |
| 213 | */ |
| 214 | rxtx_gap = ((priv->rx_end - priv->rx) - (priv->tx_end - priv->tx)) / |
| 215 | priv->n_bytes; |
| 216 | |
| 217 | return min3(tx_left, tx_room, (u32)(priv->fifo_len - rxtx_gap)); |
| 218 | } |
| 219 | |
| 220 | /* Return the max entries we should read out of rx fifo */ |
| 221 | static inline u32 rx_max(struct dw_spi_priv *priv) |
| 222 | { |
| 223 | u32 rx_left = (priv->rx_end - priv->rx) / priv->n_bytes; |
| 224 | |
| 225 | return min_t(u32, rx_left, dw_readw(priv, DW_SPI_RXFLR)); |
| 226 | } |
| 227 | |
| 228 | static void dw_writer(struct dw_spi_priv *priv) |
| 229 | { |
| 230 | u32 max = tx_max(priv); |
| 231 | u16 txw = 0; |
| 232 | |
| 233 | while (max--) { |
| 234 | /* Set the tx word if the transfer's original "tx" is not null */ |
| 235 | if (priv->tx_end - priv->len) { |
| 236 | if (priv->n_bytes == 1) |
| 237 | txw = *(u8 *)(priv->tx); |
| 238 | else |
| 239 | txw = *(u16 *)(priv->tx); |
| 240 | } |
| 241 | dw_writew(priv, DW_SPI_DR, txw); |
| 242 | debug("%s: tx=0x%02x\n", __func__, txw); |
| 243 | priv->tx += priv->n_bytes; |
| 244 | } |
| 245 | } |
| 246 | |
| 247 | static int dw_reader(struct dw_spi_priv *priv) |
| 248 | { |
| 249 | unsigned start = get_timer(0); |
| 250 | u32 max; |
| 251 | u16 rxw; |
| 252 | |
| 253 | /* Wait for rx data to be ready */ |
| 254 | while (rx_max(priv) == 0) { |
| 255 | if (get_timer(start) > RX_TIMEOUT) |
| 256 | return -ETIMEDOUT; |
| 257 | } |
| 258 | |
| 259 | max = rx_max(priv); |
| 260 | |
| 261 | while (max--) { |
| 262 | rxw = dw_readw(priv, DW_SPI_DR); |
| 263 | debug("%s: rx=0x%02x\n", __func__, rxw); |
| 264 | /* Care rx only if the transfer's original "rx" is not null */ |
| 265 | if (priv->rx_end - priv->len) { |
| 266 | if (priv->n_bytes == 1) |
| 267 | *(u8 *)(priv->rx) = rxw; |
| 268 | else |
| 269 | *(u16 *)(priv->rx) = rxw; |
| 270 | } |
| 271 | priv->rx += priv->n_bytes; |
| 272 | } |
| 273 | |
| 274 | return 0; |
| 275 | } |
| 276 | |
| 277 | static int poll_transfer(struct dw_spi_priv *priv) |
| 278 | { |
| 279 | int ret; |
| 280 | |
| 281 | do { |
| 282 | dw_writer(priv); |
| 283 | ret = dw_reader(priv); |
| 284 | if (ret < 0) |
| 285 | return ret; |
| 286 | } while (priv->rx_end > priv->rx); |
| 287 | |
| 288 | return 0; |
| 289 | } |
| 290 | |
| 291 | static int dw_spi_xfer(struct udevice *dev, unsigned int bitlen, |
| 292 | const void *dout, void *din, unsigned long flags) |
| 293 | { |
| 294 | struct udevice *bus = dev->parent; |
| 295 | struct dw_spi_priv *priv = dev_get_priv(bus); |
| 296 | const u8 *tx = dout; |
| 297 | u8 *rx = din; |
| 298 | int ret = 0; |
| 299 | u32 cr0 = 0; |
| 300 | u8 bits = 0; |
| 301 | u32 cs; |
| 302 | |
| 303 | /* spi core configured to do 8 bit transfers */ |
| 304 | if (bitlen % 8) { |
| 305 | debug("Non byte aligned SPI transfer.\n"); |
| 306 | return -1; |
| 307 | } |
| 308 | |
| 309 | bits = priv->bits_per_word; |
| 310 | priv->n_bytes = bits >> 3; |
| 311 | cr0 = (bits - 1) | (priv->type << SPI_FRF_OFFSET) | |
| 312 | (priv->mode << SPI_MODE_OFFSET) | |
| 313 | (priv->tmode << SPI_TMOD_OFFSET); |
| 314 | |
| 315 | if (rx && tx) |
| 316 | priv->tmode = SPI_TMOD_TR; |
| 317 | else if (rx) |
| 318 | priv->tmode = SPI_TMOD_RO; |
| 319 | else |
| 320 | priv->tmode = SPI_TMOD_TO; |
| 321 | |
| 322 | cr0 &= ~SPI_TMOD_MASK; |
| 323 | cr0 |= (priv->tmode << SPI_TMOD_OFFSET); |
| 324 | |
| 325 | priv->len = bitlen / 8; |
| 326 | debug("%s: rx=%p tx=%p len=%d [bytes]\n", __func__, rx, tx, priv->len); |
| 327 | |
| 328 | priv->tx = (void *)tx; |
| 329 | priv->tx_end = priv->tx + priv->len; |
| 330 | priv->rx = rx; |
| 331 | priv->rx_end = priv->rx + priv->len; |
| 332 | |
| 333 | /* Disable controller before writing control registers */ |
| 334 | spi_enable_chip(priv, 0); |
| 335 | |
| 336 | debug("%s: cr0=%08x\n", __func__, cr0); |
| 337 | /* Reprogram cr0 only if changed */ |
| 338 | if (dw_readw(priv, DW_SPI_CTRL0) != cr0) |
| 339 | dw_writew(priv, DW_SPI_CTRL0, cr0); |
| 340 | |
| 341 | /* |
| 342 | * Configure the desired SS (slave select 0...3) in the controller |
| 343 | * The DW SPI controller will activate and deactivate this CS |
| 344 | * automatically. So no cs_activate() etc is needed in this driver. |
| 345 | */ |
| 346 | cs = spi_chip_select(dev); |
| 347 | dw_writel(priv, DW_SPI_SER, 1 << cs); |
| 348 | |
| 349 | /* Enable controller after writing control registers */ |
| 350 | spi_enable_chip(priv, 1); |
| 351 | |
| 352 | /* Start transfer in a polling loop */ |
| 353 | ret = poll_transfer(priv); |
| 354 | |
| 355 | return ret; |
| 356 | } |
| 357 | |
| 358 | static int dw_spi_set_speed(struct udevice *bus, uint speed) |
| 359 | { |
| 360 | struct dw_spi_platdata *plat = bus->platdata; |
| 361 | struct dw_spi_priv *priv = dev_get_priv(bus); |
| 362 | u16 clk_div; |
| 363 | |
| 364 | if (speed > plat->frequency) |
| 365 | speed = plat->frequency; |
| 366 | |
| 367 | /* Disable controller before writing control registers */ |
| 368 | spi_enable_chip(priv, 0); |
| 369 | |
| 370 | /* clk_div doesn't support odd number */ |
| 371 | clk_div = CONFIG_DW_SPI_REF_CLK / speed; |
| 372 | clk_div = (clk_div + 1) & 0xfffe; |
| 373 | dw_writel(priv, DW_SPI_BAUDR, clk_div); |
| 374 | |
| 375 | /* Enable controller after writing control registers */ |
| 376 | spi_enable_chip(priv, 1); |
| 377 | |
| 378 | priv->freq = speed; |
| 379 | debug("%s: regs=%p speed=%d clk_div=%d\n", __func__, priv->regs, |
| 380 | priv->freq, clk_div); |
| 381 | |
| 382 | return 0; |
| 383 | } |
| 384 | |
| 385 | static int dw_spi_set_mode(struct udevice *bus, uint mode) |
| 386 | { |
| 387 | struct dw_spi_priv *priv = dev_get_priv(bus); |
| 388 | |
| 389 | /* |
| 390 | * Can't set mode yet. Since this depends on if rx, tx, or |
| 391 | * rx & tx is requested. So we have to defer this to the |
| 392 | * real transfer function. |
| 393 | */ |
| 394 | priv->mode = mode; |
| 395 | debug("%s: regs=%p, mode=%d\n", __func__, priv->regs, priv->mode); |
| 396 | |
| 397 | return 0; |
| 398 | } |
| 399 | |
| 400 | static const struct dm_spi_ops dw_spi_ops = { |
| 401 | .xfer = dw_spi_xfer, |
| 402 | .set_speed = dw_spi_set_speed, |
| 403 | .set_mode = dw_spi_set_mode, |
| 404 | /* |
| 405 | * cs_info is not needed, since we require all chip selects to be |
| 406 | * in the device tree explicitly |
| 407 | */ |
| 408 | }; |
| 409 | |
| 410 | static const struct udevice_id dw_spi_ids[] = { |
| 411 | { .compatible = "snps,dw-spi-mmio" }, |
| 412 | { } |
| 413 | }; |
| 414 | |
| 415 | U_BOOT_DRIVER(dw_spi) = { |
| 416 | .name = "dw_spi", |
| 417 | .id = UCLASS_SPI, |
| 418 | .of_match = dw_spi_ids, |
| 419 | .ops = &dw_spi_ops, |
| 420 | .ofdata_to_platdata = dw_spi_ofdata_to_platdata, |
| 421 | .platdata_auto_alloc_size = sizeof(struct dw_spi_platdata), |
| 422 | .priv_auto_alloc_size = sizeof(struct dw_spi_priv), |
| 423 | .per_child_auto_alloc_size = sizeof(struct spi_slave), |
| 424 | .probe = dw_spi_probe, |
| 425 | }; |