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wdenk6310eb92005-01-09 21:28:15 +00001/*
2 * (C) Copyright 2002
3 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
4 *
5 * (C) Copyright 2002
6 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
7 * Marius Groeger <mgroeger@sysgo.de>
8 *
9 * Configuration settings for the PLEB 2 board.
10 *
11 * See file CREDITS for list of people who contributed to this
12 * project.
13 *
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 * MA 02111-1307 USA
28 */
29
30#ifndef __CONFIG_H
31#define __CONFIG_H
32
33/*
wdenk6310eb92005-01-09 21:28:15 +000034 * High Level Configuration Options
35 * (easy to change)
36 */
37#define CONFIG_PXA250 1 /* This is an PXA255 CPU */
38#define CONFIG_PLEB2 1 /* on an PLEB2 Board */
39#undef CONFIG_LCD
40#undef CONFIG_MMC
41#define BOARD_LATE_INIT 1
42
43#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
44
45/*
46 * Size of malloc() pool
47 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020048#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
49#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
wdenk6310eb92005-01-09 21:28:15 +000050
51/*
52 * Hardware drivers
53 */
54
55/* None - PLEB 2 doesn't have any of this.
56 #define CONFIG_DRIVER_LAN91C96
57 #define CONFIG_LAN91C96_BASE 0x0C000000 */
58
59/*
60 * select serial console configuration
61 */
62#define CONFIG_FFUART 1 /* we use FFUART on PLEB 2 */
63
64/* allow to overwrite serial and ethaddr */
65#define CONFIG_ENV_OVERWRITE
66
67#define CONFIG_BAUDRATE 115200
68
wdenk6310eb92005-01-09 21:28:15 +000069
Jon Loeliger26a34562007-07-04 22:33:17 -050070/*
Jon Loeliger079a1362007-07-10 10:12:10 -050071 * BOOTP options
72 */
73#define CONFIG_BOOTP_BOOTFILESIZE
74#define CONFIG_BOOTP_BOOTPATH
75#define CONFIG_BOOTP_GATEWAY
76#define CONFIG_BOOTP_HOSTNAME
77
78
79/*
Jon Loeliger26a34562007-07-04 22:33:17 -050080 * Command line configuration.
81 */
82#include <config_cmd_default.h>
83
84#undef CONFIG_CMD_NET
85
wdenk6310eb92005-01-09 21:28:15 +000086
87#define CONFIG_BOOTDELAY 3
88#define CONFIG_ETHADDR 08:00:3e:26:0a:5b
89#define CONFIG_NETMASK 255.255.0.0
90#define CONFIG_IPADDR 192.168.0.21
91#define CONFIG_SERVERIP 192.168.0.250
92#define CONFIG_BOOTCOMMAND "bootm 40000"
93#define CONFIG_BOOTARGS "root=/dev/mtdblock2 prompt_ramdisk=0 load_ramdisk=1 console=ttyS0,115200"
94
95#define CONFIG_CMDLINE_TAG
96#define CONFIG_INITRD_TAG
97#define CONFIG_SETUP_MEMORY_TAGS
98
Jon Loeliger26a34562007-07-04 22:33:17 -050099#if defined(CONFIG_CMD_KGDB)
wdenk6310eb92005-01-09 21:28:15 +0000100#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
101#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
102#endif
103
104/*
105 * Miscellaneous configurable options
106 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200107#define CONFIG_SYS_HUSH_PARSER 1
108#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
wdenk6310eb92005-01-09 21:28:15 +0000109
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200110#define CONFIG_SYS_LONGHELP /* undef to save memory */
111#ifdef CONFIG_SYS_HUSH_PARSER
112#define CONFIG_SYS_PROMPT "$ " /* Monitor Command Prompt */
wdenk6310eb92005-01-09 21:28:15 +0000113#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200114#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
wdenk6310eb92005-01-09 21:28:15 +0000115#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200116#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
117#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
118#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
119#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
120#define CONFIG_SYS_DEVICE_NULLDEV 1
wdenk6310eb92005-01-09 21:28:15 +0000121
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200122#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */
123#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
wdenk6310eb92005-01-09 21:28:15 +0000124
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200125#define CONFIG_SYS_LOAD_ADDR 0xa2000000 /* default load address */
wdenk6310eb92005-01-09 21:28:15 +0000126
Micha Kalfon94a33122009-02-11 19:50:11 +0200127#define CONFIG_SYS_HZ 1000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200128#define CONFIG_SYS_CPUSPEED 0x141 /* set core clock to 200/200/100 MHz */
wdenk6310eb92005-01-09 21:28:15 +0000129
130 /* valid baudrates */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200131#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
wdenk6310eb92005-01-09 21:28:15 +0000132
Jean-Christophe PLAGNIOL-VILLARDb03d92e2009-02-20 03:47:50 +0100133#ifdef CONFIG_MMC
134#define CONFIG_PXA_MMC
135#define CONFIG_CMD_MMC
136#endif
137
wdenk6310eb92005-01-09 21:28:15 +0000138/*
139 * Stack sizes
140 *
141 * The stack sizes are set up in start.S using the settings below
142 */
143#define CONFIG_STACKSIZE (128*1024) /* regular stack */
144#ifdef CONFIG_USE_IRQ
145#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
146#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
147#endif
148
149/*
150 * Physical Memory Map
151 */
152#define CONFIG_NR_DRAM_BANKS 4 /* we have 2 banks of DRAM */
153#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
154#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */
155#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */
156#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */
157#define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */
158#define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */
159#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */
160#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */
161
162#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
163#define PHYS_FLASH_2 0x04000000 /* Flash Bank #2 */
164#define PHYS_FLASH_SIZE 0x00800000 /* 4 MB */
165
166/* Not entirely sure about this - DS/CHC */
167#define PHYS_FLASH_BANK_SIZE 0x02000000 /* 32 MB Banks */
168#define PHYS_FLASH_SECT_SIZE 0x00010000 /* 64 KB sectors (x2) */
169
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200170#define CONFIG_SYS_DRAM_BASE PHYS_SDRAM_1
171#define CONFIG_SYS_DRAM_SIZE PHYS_SDRAM_1_SIZE
wdenk6310eb92005-01-09 21:28:15 +0000172
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200173#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
174#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
wdenk6310eb92005-01-09 21:28:15 +0000175
176/*
177 * GPIO settings
178 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200179#define CONFIG_SYS_GPSR0_VAL 0x00000000 /* Don't set anything */
180#define CONFIG_SYS_GPSR1_VAL 0x00000080
181#define CONFIG_SYS_GPSR2_VAL 0x00000000
wdenk6310eb92005-01-09 21:28:15 +0000182
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200183#define CONFIG_SYS_GPCR0_VAL 0x00000000 /* Don't clear anything */
184#define CONFIG_SYS_GPCR1_VAL 0x00000000
185#define CONFIG_SYS_GPCR2_VAL 0x00000000
wdenk6310eb92005-01-09 21:28:15 +0000186
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200187#define CONFIG_SYS_GPDR0_VAL 0x00000000
188#define CONFIG_SYS_GPDR1_VAL 0x000007C3
189#define CONFIG_SYS_GPDR2_VAL 0x00000000
wdenk6310eb92005-01-09 21:28:15 +0000190
191/* Edge detect registers (these are set by the kernel) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200192#define CONFIG_SYS_GRER0_VAL 0x00000000
193#define CONFIG_SYS_GRER1_VAL 0x00000000
194#define CONFIG_SYS_GRER2_VAL 0x00000000
195#define CONFIG_SYS_GFER0_VAL 0x00000000
196#define CONFIG_SYS_GFER1_VAL 0x00000000
197#define CONFIG_SYS_GFER2_VAL 0x00000000
wdenk6310eb92005-01-09 21:28:15 +0000198
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200199#define CONFIG_SYS_GAFR0_L_VAL 0x00000000
200#define CONFIG_SYS_GAFR0_U_VAL 0x00000000
201#define CONFIG_SYS_GAFR1_L_VAL 0x00008010 /* Use FF UART Send and Receive */
202#define CONFIG_SYS_GAFR1_U_VAL 0x00000000
203#define CONFIG_SYS_GAFR2_L_VAL 0x00000000
204#define CONFIG_SYS_GAFR2_U_VAL 0x00000000
wdenk6310eb92005-01-09 21:28:15 +0000205
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200206#define CONFIG_SYS_PSSR_VAL 0x20
207#define CONFIG_SYS_CCCR_VAL 0x00000141 /* 100 MHz memory, 200 MHz CPU */
208#define CONFIG_SYS_CKEN_VAL 0x00000060 /* FFUART and STUART enabled */
209#define CONFIG_SYS_ICMR_VAL 0x00000000 /* No interrupts enabled */
wdenk6310eb92005-01-09 21:28:15 +0000210
211/*
212 * Memory settings
213 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200214#define CONFIG_SYS_MSC0_VAL 0x00007FF0 /* Not properly calculated - FIXME (DS) */
215#define CONFIG_SYS_MSC1_VAL 0x00000000
216#define CONFIG_SYS_MSC2_VAL 0x00000000
wdenk6310eb92005-01-09 21:28:15 +0000217
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200218#define CONFIG_SYS_MDCNFG_VAL 0x00000aC9 /* Memory timings for the SDRAM.
wdenk6310eb92005-01-09 21:28:15 +0000219 tRP=2, CL=2, tRCD=2, tRAS=5, tRC=8 */
220
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200221#define CONFIG_SYS_MDREFR_VAL 0x00403018 /* Initial setting, individual */
wdenk400558b2005-04-02 23:52:25 +0000222 /* bits set in lowlevel_init.S */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200223#define CONFIG_SYS_MDMRS_VAL 0x00000000
wdenk6310eb92005-01-09 21:28:15 +0000224
225/*
226 * PCMCIA and CF Interfaces
227 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200228#define CONFIG_SYS_MECR_VAL 0x00000000 /* Hangover from Lubbock.
wdenk6310eb92005-01-09 21:28:15 +0000229 Needs calculating. (DS/CHC) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200230#define CONFIG_SYS_MCMEM0_VAL 0x00010504
231#define CONFIG_SYS_MCMEM1_VAL 0x00010504
232#define CONFIG_SYS_MCATT0_VAL 0x00010504
233#define CONFIG_SYS_MCATT1_VAL 0x00010504
234#define CONFIG_SYS_MCIO0_VAL 0x00004715
235#define CONFIG_SYS_MCIO1_VAL 0x00004715
wdenk6310eb92005-01-09 21:28:15 +0000236
237/*
238 * FLASH and environment organization
239 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200240#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
241#define CONFIG_SYS_MAX_FLASH_SECT 64 /* max number of sectors on one chip */
wdenk6310eb92005-01-09 21:28:15 +0000242
243/* timeout values are in ticks */
244/* FIXME */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200245#define CONFIG_SYS_FLASH_ERASE_TOUT (25*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
246#define CONFIG_SYS_FLASH_WRITE_TOUT (25*CONFIG_SYS_HZ) /* Timeout for Flash Write */
wdenk6310eb92005-01-09 21:28:15 +0000247
248/* Flash protection */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200249#define CONFIG_SYS_FLASH_PROTECTION 1
wdenk6310eb92005-01-09 21:28:15 +0000250
251/* FIXME */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200252#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200253#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x3C000) /* Addr of Environment Sector */
254#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment */
255#define CONFIG_ENV_SECT_SIZE 0x20000
wdenk6310eb92005-01-09 21:28:15 +0000256
257/* Option added to get around byte ordering issues in the flash driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200258#define CONFIG_SYS_LITTLE_ENDIAN 1
wdenk6310eb92005-01-09 21:28:15 +0000259
260#endif /* __CONFIG_H */