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Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
David Lechner2ac07f72016-02-26 00:46:07 -06002/*
3 * Copyright (C) 2016 David Lechner <david@lechnology.com>
4 *
5 * Based on da850evm.h
6 *
Nishanth Menona94a4072023-11-01 15:56:03 -05007 * Copyright (C) 2010 Texas Instruments Incorporated - https://www.ti.com/
David Lechner2ac07f72016-02-26 00:46:07 -06008 *
9 * Based on davinci_dvevm.h. Original Copyrights follow:
10 *
11 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
David Lechner2ac07f72016-02-26 00:46:07 -060012 */
13
14#ifndef __CONFIG_H
15#define __CONFIG_H
16
17/*
18 * SoC Configuration
19 */
Tom Rini65cc0e22022-11-16 13:10:41 -050020#define CFG_SYS_EXCEPTION_VECTORS_HIGH
21#define CFG_SYS_OSCIN_FREQ 24000000
22#define CFG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
23#define CFG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
David Lechner2ac07f72016-02-26 00:46:07 -060024
David Lechner2ac07f72016-02-26 00:46:07 -060025/*
26 * Memory Info
27 */
David Lechner2ac07f72016-02-26 00:46:07 -060028#define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
29#define PHYS_SDRAM_1_SIZE (64 << 20) /* SDRAM size 64MB */
Tom Rini8a897c42022-12-04 10:04:51 -050030#define CFG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
David Lechner2ac07f72016-02-26 00:46:07 -060031
32/* memtest start addr */
David Lechner2ac07f72016-02-26 00:46:07 -060033
34/* memtest will be run on 16MB */
David Lechner2ac07f72016-02-26 00:46:07 -060035
David Lechner2ac07f72016-02-26 00:46:07 -060036/*
37 * Serial Driver info
38 */
Tom Rini91092132022-11-16 13:10:28 -050039#define CFG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID)
David Lechner2ac07f72016-02-26 00:46:07 -060040
Tom Rini65cc0e22022-11-16 13:10:41 -050041#define CFG_SYS_SPI_CLK clk_get(DAVINCI_SPI0_CLKID)
David Lechner2ac07f72016-02-26 00:46:07 -060042
43/*
David Lechner2ac07f72016-02-26 00:46:07 -060044 * U-Boot general configuration
45 */
David Lechner2ac07f72016-02-26 00:46:07 -060046
47/*
48 * Linux Information
49 */
50#define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100)
Tom Rini0613c362022-12-04 10:03:50 -050051#define CFG_EXTRA_ENV_SETTINGS \
David Lechnerf203a472018-05-19 23:25:07 -050052 "bootenvfile=uEnv.txt\0" \
53 "fdtfile=da850-lego-ev3.dtb\0" \
David Lechner2ac07f72016-02-26 00:46:07 -060054 "memsize=64M\0" \
55 "filesyssize=10M\0" \
56 "verify=n\0" \
57 "console=ttyS1,115200n8\0" \
58 "bootscraddr=0xC0600000\0" \
David Lechnerf203a472018-05-19 23:25:07 -050059 "fdtaddr=0xC0600000\0" \
David Lechner2ac07f72016-02-26 00:46:07 -060060 "loadaddr=0xC0007FC0\0" \
61 "filesysaddr=0xC1180000\0" \
62 "fwupdateboot=mw 0xFFFF1FFC 0x5555AAAA; reset\0" \
David Lechnerf203a472018-05-19 23:25:07 -050063 "importbootenv=echo Importing environment...; " \
64 "env import -t ${loadaddr} ${filesize}\0" \
65 "loadbootenv=fatload mmc 0 ${loadaddr} ${bootenvfile}\0" \
66 "mmcargs=setenv bootargs console=${console} root=/dev/mmcblk0p2 rw " \
67 "rootwait ${optargs}\0" \
David Lechner2ac07f72016-02-26 00:46:07 -060068 "mmcboot=bootm ${loadaddr}\0" \
David Lechnerf203a472018-05-19 23:25:07 -050069 "flashargs=setenv bootargs initrd=${filesysaddr},${filesyssize} " \
70 "root=/dev/ram0 rw rootfstype=squashfs console=${console} " \
71 "${optargs}\0" \
72 "flashboot=sf probe 0; " \
73 "sf read ${fdtaddr} 0x40000 0x10000; " \
74 "sf read ${loadaddr} 0x50000 0x400000; " \
75 "sf read ${filesysaddr} 0x450000 0xA00000; " \
76 "run fdtfixup; " \
77 "run fdtboot\0" \
David Lechner2ac07f72016-02-26 00:46:07 -060078 "loadimage=fatload mmc 0 ${loadaddr} uImage\0" \
David Lechnerf203a472018-05-19 23:25:07 -050079 "loadfdt=fatload mmc 0 ${fdtaddr} ${fdtfile}\0" \
80 "fdtfixup=fdt addr ${fdtaddr}; fdt resize; fdt chosen\0" \
81 "fdtboot=bootm ${loadaddr} - ${fdtaddr}\0" \
David Lechner2ac07f72016-02-26 00:46:07 -060082 "loadbootscr=fatload mmc 0 ${bootscraddr} boot.scr\0" \
David Lechnerf203a472018-05-19 23:25:07 -050083 "bootscript=source ${bootscraddr}\0"
David Lechner2ac07f72016-02-26 00:46:07 -060084
David Lechner2ac07f72016-02-26 00:46:07 -060085/* additions for new relocation code, must added to all boards */
Tom Riniaa6e94d2022-11-16 13:10:37 -050086#define CFG_SYS_SDRAM_BASE 0xc0000000
David Lechner2ac07f72016-02-26 00:46:07 -060087
Simon Glass89f5eaa2017-05-17 08:23:09 -060088#include <asm/arch/hardware.h>
89
David Lechner2ac07f72016-02-26 00:46:07 -060090#endif /* __CONFIG_H */