blob: 02f56858244147b337be1d52b3912c4d92e5bf74 [file] [log] [blame]
wdenk855a4962004-03-14 18:23:55 +00001/*
2 * Memory Setup stuff - taken from blob memsetup.S
3 *
4 * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
5 * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
6 * 2003-2004 (c) MontaVista Software, Inc.
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27
28#include "config.h"
29#include "version.h"
30
31
32 .globl memsetup
33memsetup:
34 /* The ADS GC+ for Linux Boot Rom Ver. 1.73 does memory init for us.
35 * However the darn thing leaves the MMU enabled before handing control
36 * over to us. So we need to disable the MMU and we use memsetup
37 * to do it.
38 */
39
40@ The following code segment was borrowed with gratitude from:
41@ linux-2.4.19-rmk7/arch/arm/boot/compressed/head-sa1100.S
42
43 @ Data cache might be active.
44 @ Be sure to flush kernel binary out of the cache,
45 @ whatever state it is, before it is turned off.
46 @ This is done by fetching through currently executed
47 @ memory to be sure we hit the same cache.
48 bic r2, pc, #0x1f
49 add r3, r2, #0x4000 @ 16 kb is quite enough...
501: ldr r0, [r2], #32
51 teq r2, r3
52 bne 1b
53 mcr p15, 0, r0, c7, c10, 4 @ drain WB
54 mcr p15, 0, r0, c7, c7, 0 @ flush I & D caches
55
56 @ disabling MMU and caches
57 mrc p15, 0, r0, c1, c0, 0 @ read control reg
58 bic r0, r0, #0x0d @ clear WB, DC, MMU
59 bic r0, r0, #0x1000 @ clear Icache
60 mcr p15, 0, r0, c1, c0, 0
61
62 nop
63 nop
64 nop
65 nop
66 nop
67
68 b 2f
692:
70 nop
71 nop
72 nop
73 nop
74 nop
75
76
77 mov pc, lr