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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / 5ca9881aad8c413ac2a82868a5e3719178254502 / . / board / apollon / lowlevel_init.S
blob: 76762599b1d5a85239d2bec3b7716436bcfa61f1 [file] [log] [blame]
Peter Pearse5ca98812007-11-09 15:24:26 +0000[diff] [blame^]1/*
2 * Board specific setup info
3 *
4 * (C) Copyright 2005-2007
5 * Samsung Electronics,
6 * Kyungmin Park <kyungmin.park@samsung.com>
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27#include <config.h>
28#include <version.h>
29#include <asm/arch/omap2420.h>
30#include <asm/arch/mem.h>
31#include <asm/arch/clocks.h>
32#include "mem.h"
33
34#define APOLLON_CS0_BASE 0x00000000
35
36#ifdef PRCM_CONFIG_I
37# define SDRC_ACTIM_CTRLA_0_VAL 0x7BA35907
38# define SDRC_ACTIM_CTRLB_0_VAL 0x00000013
39# define SDRC_RFR_CTRL_0_VAL 0x00044C01
40#elif defined(PRCM_CONFIG_II)
41# define SDRC_ACTIM_CTRLA_0_VAL 0x4A59B485
42# define SDRC_ACTIM_CTRLB_0_VAL 0x0000000C
43# define SDRC_RFR_CTRL_0_VAL 0x00030001
44#endif
45
46#define SDRAM_BASE_ADDRESS 0x80008000
47
48_TEXT_BASE:
49 .word TEXT_BASE /* sdram load addr from config.mk */
50
51.globl lowlevel_init
52lowlevel_init:
53
54#ifdef CFG_NOR_BOOT
55 /* Check running in SDRAM */
56 mov r0, pc, lsr #28
57 cmp r0, #8
58 beq prcm_setup
59
60flash_setup:
61 /* In Flash */
62 ldr r0, =WD2_BASE
63 ldr r1, =WD_UNLOCK1
64 str r1, [r0, #WSPR]
65
66 ldr r1, =WD_UNLOCK2
67 str r1, [r0, #WSPR]
68
69 /* Pin muxing for SDRC */
70 mov r1, #0x00
71 ldr r0, =0x480000A1 /* ball C12, mode 0 */
72 strb r1, [r0]
73
74 ldr r0, =0x48000032 /* ball D11, mode 0 */
75 strb r1, [r0]
76
77 ldr r0, =0x480000A3 /* ball B13, mode 0 */
78 strb r1, [r0]
79
80 /* SDRC setting */
81 ldr r0, =OMAP2420_SDRC_BASE
82 ldr r1, =0x00000010
83 str r1, [r0, #0x10]
84
85 ldr r1, =0x00000100
86 str r1, [r0, #0x44]
87
88 /* SDRC CS0 configuration */
89 ldr r1, =0x00d04011
90 str r1, [r0, #0x80]
91
92 ldr r1, =SDRC_ACTIM_CTRLA_0_VAL
93 str r1, [r0, #0x9C]
94
95 ldr r1, =SDRC_ACTIM_CTRLB_0_VAL
96 str r1, [r0, #0xA0]
97
98 ldr r1, =SDRC_RFR_CTRL_0_VAL
99 str r1, [r0, #0xA4]
100
101 ldr r1, =0x00000041
102 str r1, [r0, #0x70]
103
104 /* Manual command sequence */
105 ldr r1, =0x00000007
106 str r1, [r0, #0xA8]
107
108 ldr r1, =0x00000000
109 str r1, [r0, #0xA8]
110
111 ldr r1, =0x00000001
112 str r1, [r0, #0xA8]
113
114 ldr r1, =0x00000002
115 str r1, [r0, #0xA8]
116 str r1, [r0, #0xA8]
117
118 /*
119 * CS0 SDRC Mode register
120 * Burst length = 4 - DDR memory
121 * Serial mode
122 * CAS latency = 3
123 */
124 ldr r1, =0x00000032
125 str r1, [r0, #0x84]
126
127 /* Note: You MUST set EMR values */
128 /* EMR1 & EMR2 */
129 ldr r1, =0x00000000
130 str r1, [r0, #0x88]
131 str r1, [r0, #0x8C]
132
133#ifdef OLD_SDRC_DLLA_CTRL
134 /* SDRC_DLLA_CTRL */
135 ldr r1, =0x00007306
136 str r1, [r0, #0x60]
137
138 ldr r1, =0x00007303
139 str r1, [r0, #0x60]
140#else
141 /* SDRC_DLLA_CTRL */
142 ldr r1, =0x00000506
143 str r1, [r0, #0x60]
144
145 ldr r1, =0x00000503
146 str r1, [r0, #0x60]
147#endif
148
149#ifdef __BROKEN_FEATURE__
150 /* SDRC_DLLB_CTRL */
151 ldr r1, =0x00000506
152 str r1, [r0, #0x68]
153
154 ldr r1, =0x00000503
155 str r1, [r0, #0x68]
156#endif
157
158 /* little delay after init */
159 mov r2, #0x1800
1601:
161 subs r2, r2, #0x1
162 bne 1b
163
164 /* Setup base address */
165 ldr r0, =0x00000000 /* NOR address */
166 ldr r1, =SDRAM_BASE_ADDRESS /* SDRAM address */
167 ldr r2, =0x20000 /* Size: 128KB */
168
169copy_loop:
170 ldmia r0!, {r3-r10}
171 stmia r1!, {r3-r10}
172 cmp r0, r2
173 ble copy_loop
174
175 ldr r1, =SDRAM_BASE_ADDRESS
176 mov lr, pc
177 mov pc, r1
178#endif
179
180prcm_setup:
181 ldr r0, =OMAP2420_CM_BASE
182 ldr r1, [r0, #0x544] /* CLKSEL2_PLL */
183 bic r1, r1, #0x03
184 orr r1, r1, #0x02
185 str r1, [r0, #0x544]
186
187 ldr r1, [r0, #0x500]
188 bic r1, r1, #0x03
189 orr r1, r1, #0x01
190 str r1, [r0, #0x500]
191
192 ldr r1, [r0, #0x140]
193 bic r1, r1, #0x1f
194 orr r1, r1, #0x02
195 str r1, [r0, #0x140]
196
197#ifdef PRCM_CONFIG_I
198 ldr r1, =0x000003C3
199#else
200 ldr r1, =0x00000343
201#endif
202 str r1, [r0, #0x840]
203
204 ldr r1, =0x00000002
205 str r1, [r0, #0x340]
206
207 ldr r1, =CM_CLKSEL1_CORE
208#ifdef PRCM_CONFIG_I
209 ldr r2, =0x08300C44
210#else
211 ldr r2, =0x04600C26
212#endif
213 str r2, [r1]
214
215 ldr r0, =OMAP2420_CM_BASE
216 ldr r1, [r0, #0x084]
217 and r1, r1, #0x01
218 cmp r1, #0x01
219 bne clkvalid
220
221 b .
222
223clkvalid:
224 mov r1, #0x01
225 str r1, [r0, #0x080]
226
227waitvalid:
228 ldr r1, [r0, #0x084]
229 and r1, r1, #0x01
230 cmp r1, #0x00
231 bne waitvalid
232
233 ldr r0, =CM_CLKSEL1_PLL
234#ifdef PRCM_CONFIG_I
235 ldr r1, =0x01837100
236#else
237 ldr r1, =0x01832100
238#endif
239 str r1, [r0]
240
241 ldr r0, =PRCM_CLKCFG_CTRL
242 mov r1, #0x01
243 str r1, [r0]
244 mov r6, #0x50
245loop1:
246 subs r6, r6, #0x01
247 cmp r6, #0x01
248 bne loop1
249
250 ldr r0, =CM_CLKEN_PLL
251 mov r1, #0x0f
252 str r1, [r0]
253
254 mov r6, #0x100
255loop2:
256 subs r6, r6, #0x01
257 cmp r6, #0x01
258 bne loop2
259
260 ldr r0, =0x48008200
261 ldr r1, =0xbfffffff
262 str r1, [r0]
263
264 ldr r0, =0x48008210
265 ldr r1, =0xfffffff9
266 str r1, [r0]
267
268 ldr r0, =0x4806a004
269 ldr r1, =0x00
270 strb r1, [r0]
271
272 ldr r0, =0x4806a020
273 ldr r1, =0x07
274 strb r1, [r0]
275
276 ldr r0, =0x4806a00c
277 ldr r1, =0x83
278 strb r1, [r0]
279
280 ldr r0, =0x4806a000
281 ldr r1, =0x1a
282 strb r1, [r0]
283
284 ldr r0, =0x4806a004
285 ldr r1, =0x00
286 strb r1, [r0]
287
288 ldr r0, =0x4806a00c
289 ldr r1, =0x03
290 strb r1, [r0]
291
292 ldr r0, =0x4806a010
293 ldr r1, =0x03
294 strb r1, [r0]
295
296 ldr r0, =0x4806a008
297 ldr r1, =0x04
298 strb r1, [r0]
299
300 ldr r0, =0x4806a020
301 ldr r1, =0x00
302 strb r1, [r0]
303
304#if 0
305 ldr r0, =0x4806a000
306 mov r1, #'u'
307 strb r1, [r0]
308#endif
309
310#if 0
311 /* LED0 OFF */
312 ldr r3, =0x480000E5
313 mov r4, #0x0b
314 strb r4, [r3]
315#endif
316
317 ldr sp, SRAM_STACK
318 str ip, [sp] /* stash old link register */
319 mov ip, lr /* save link reg across call */
320 bl s_init /* go setup pll,mux,memory */
321 ldr ip, [sp] /* restore save ip */
322 mov lr, ip /* restore link reg */
323
324 /* map interrupt controller */
325 ldr r0, VAL_INTH_SETUP
326 mcr p15, 0, r0, c15, c2, 4
327
328 /* back to arch calling code */
329 mov pc, lr
330
331 /* the literal pools origin */
332 .ltorg
333
334VAL_INTH_SETUP:
335 .word PERIFERAL_PORT_BASE
336SRAM_STACK:
337 .word LOW_LEVEL_SRAM_STACK