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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / 5cc69084189bf49aa99d13d57515be72d1844bdf / . / cpu / arm1176 / s3c64xx / cpu_init.S
blob: 32bb467f2f64c6b7e216b5bcc65b92b60acbd397 [file] [log] [blame]
Guennadi Liakhovetski9b077732008-08-31 00:39:46 +0200[diff] [blame]1/*
2 * Originates from Samsung's u-boot 1.1.6 port to S3C6400 / SMDK6400
3 *
4 * Copyright (C) 2008
5 * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26#include <config.h>
27#include <s3c6400.h>
28
29 .globl mem_ctrl_asm_init
30mem_ctrl_asm_init:
Guennadi Liakhovetski9b077732008-08-31 00:39:46 +0200[diff] [blame]31 /* DMC1 base address 0x7e001000 */
32 ldr r0, =ELFIN_DMC1_BASE
33
34 ldr r1, =0x4
35 str r1, [r0, #INDEX_DMC_MEMC_CMD]
36
37 ldr r1, =DMC_DDR_REFRESH_PRD
38 str r1, [r0, #INDEX_DMC_REFRESH_PRD]
39
40 ldr r1, =DMC_DDR_CAS_LATENCY
41 str r1, [r0, #INDEX_DMC_CAS_LATENCY]
42
43 ldr r1, =DMC_DDR_t_DQSS
44 str r1, [r0, #INDEX_DMC_T_DQSS]
45
46 ldr r1, =DMC_DDR_t_MRD
47 str r1, [r0, #INDEX_DMC_T_MRD]
48
49 ldr r1, =DMC_DDR_t_RAS
50 str r1, [r0, #INDEX_DMC_T_RAS]
51
52 ldr r1, =DMC_DDR_t_RC
53 str r1, [r0, #INDEX_DMC_T_RC]
54
55 ldr r1, =DMC_DDR_t_RCD
56 ldr r2, =DMC_DDR_schedule_RCD
57 orr r1, r1, r2
58 str r1, [r0, #INDEX_DMC_T_RCD]
59
60 ldr r1, =DMC_DDR_t_RFC
61 ldr r2, =DMC_DDR_schedule_RFC
62 orr r1, r1, r2
63 str r1, [r0, #INDEX_DMC_T_RFC]
64
65 ldr r1, =DMC_DDR_t_RP
66 ldr r2, =DMC_DDR_schedule_RP
67 orr r1, r1, r2
68 str r1, [r0, #INDEX_DMC_T_RP]
69
70 ldr r1, =DMC_DDR_t_RRD
71 str r1, [r0, #INDEX_DMC_T_RRD]
72
73 ldr r1, =DMC_DDR_t_WR
74 str r1, [r0, #INDEX_DMC_T_WR]
75
76 ldr r1, =DMC_DDR_t_WTR
77 str r1, [r0, #INDEX_DMC_T_WTR]
78
79 ldr r1, =DMC_DDR_t_XP
80 str r1, [r0, #INDEX_DMC_T_XP]
81
82 ldr r1, =DMC_DDR_t_XSR
83 str r1, [r0, #INDEX_DMC_T_XSR]
84
85 ldr r1, =DMC_DDR_t_ESR
86 str r1, [r0, #INDEX_DMC_T_ESR]
87
88 ldr r1, =DMC1_MEM_CFG
89 str r1, [r0, #INDEX_DMC_MEMORY_CFG]
90
91 ldr r1, =DMC1_MEM_CFG2
92 str r1, [r0, #INDEX_DMC_MEMORY_CFG2]
93
94 ldr r1, =DMC1_CHIP0_CFG
95 str r1, [r0, #INDEX_DMC_CHIP_0_CFG]
96
97 ldr r1, =DMC_DDR_32_CFG
98 str r1, [r0, #INDEX_DMC_USER_CONFIG]
99
100 /* DMC0 DDR Chip 0 configuration direct command reg */
101 ldr r1, =DMC_NOP0
102 str r1, [r0, #INDEX_DMC_DIRECT_CMD]
103
104 /* Precharge All */
105 ldr r1, =DMC_PA0
106 str r1, [r0, #INDEX_DMC_DIRECT_CMD]
107
108 /* Auto Refresh 2 time */
109 ldr r1, =DMC_AR0
110 str r1, [r0, #INDEX_DMC_DIRECT_CMD]
111 str r1, [r0, #INDEX_DMC_DIRECT_CMD]
112
113 /* MRS */
114 ldr r1, =DMC_mDDR_EMR0
115 str r1, [r0, #INDEX_DMC_DIRECT_CMD]
116
117 /* Mode Reg */
118 ldr r1, =DMC_mDDR_MR0
119 str r1, [r0, #INDEX_DMC_DIRECT_CMD]
120
121 /* Enable DMC1 */
122 mov r1, #0x0
123 str r1, [r0, #INDEX_DMC_MEMC_CMD]
124
125check_dmc1_ready:
126 ldr r1, [r0, #INDEX_DMC_MEMC_STATUS]
127 mov r2, #0x3
128 and r1, r1, r2
129 cmp r1, #0x1
130 bne check_dmc1_ready
131 nop
132
133 mov pc, lr
134
135 .ltorg