wdenk | 0f8c976 | 2002-08-19 11:57:05 +0000 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2001 |
| 3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
| 4 | * |
| 5 | * See file CREDITS for list of people who contributed to this |
| 6 | * project. |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or |
| 9 | * modify it under the terms of the GNU General Public License as |
| 10 | * published by the Free Software Foundation; either version 2 of |
| 11 | * the License, or (at your option) any later version. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
| 17 | * |
| 18 | * You should have received a copy of the GNU General Public License |
| 19 | * along with this program; if not, write to the Free Software |
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 21 | * MA 02111-1307 USA |
| 22 | */ |
| 23 | |
| 24 | /* |
| 25 | * board/config.h - configuration options, board specific |
| 26 | */ |
| 27 | |
| 28 | #ifndef __CONFIG_H |
| 29 | #define __CONFIG_H |
| 30 | |
| 31 | #undef CFG_RAMBOOT |
| 32 | |
| 33 | /* |
| 34 | * High Level Configuration Options |
| 35 | * (easy to change) |
| 36 | */ |
| 37 | |
| 38 | #define CONFIG_MPC8260 1 /* This is a MPC8260 CPU */ |
| 39 | #define CONFIG_PM826 1 /* ...on a PM8260 module */ |
| 40 | |
wdenk | aacf9a4 | 2003-01-17 16:27:01 +0000 | [diff] [blame] | 41 | #undef CONFIG_DB_CR826_J30x_ON /* J30x jumpers on D.B. carrier */ |
| 42 | |
wdenk | 0f8c976 | 2002-08-19 11:57:05 +0000 | [diff] [blame] | 43 | #define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ |
| 44 | |
| 45 | #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ |
| 46 | |
| 47 | #define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" |
| 48 | |
| 49 | #undef CONFIG_BOOTARGS |
| 50 | #define CONFIG_BOOTCOMMAND \ |
| 51 | "bootp; " \ |
| 52 | "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \ |
| 53 | "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \ |
| 54 | "bootm" |
| 55 | |
| 56 | /* enable I2C and select the hardware/software driver */ |
| 57 | #undef CONFIG_HARD_I2C |
| 58 | #define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ |
| 59 | # define CFG_I2C_SPEED 50000 |
| 60 | # define CFG_I2C_SLAVE 0xFE |
| 61 | /* |
| 62 | * Software (bit-bang) I2C driver configuration |
| 63 | */ |
| 64 | #define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */ |
| 65 | #define I2C_ACTIVE (iop->pdir |= 0x00010000) |
| 66 | #define I2C_TRISTATE (iop->pdir &= ~0x00010000) |
| 67 | #define I2C_READ ((iop->pdat & 0x00010000) != 0) |
| 68 | #define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \ |
| 69 | else iop->pdat &= ~0x00010000 |
| 70 | #define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \ |
| 71 | else iop->pdat &= ~0x00020000 |
| 72 | #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ |
| 73 | |
| 74 | |
| 75 | #define CONFIG_RTC_PCF8563 |
| 76 | #define CFG_I2C_RTC_ADDR 0x51 |
| 77 | |
| 78 | /* |
| 79 | * select serial console configuration |
| 80 | * |
| 81 | * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then |
| 82 | * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 |
| 83 | * for SCC). |
| 84 | * |
| 85 | * if CONFIG_CONS_NONE is defined, then the serial console routines must |
| 86 | * defined elsewhere (for example, on the cogent platform, there are serial |
| 87 | * ports on the motherboard which are used for the serial console - see |
| 88 | * cogent/cma101/serial.[ch]). |
| 89 | */ |
| 90 | #define CONFIG_CONS_ON_SMC /* define if console on SMC */ |
| 91 | #undef CONFIG_CONS_ON_SCC /* define if console on SCC */ |
| 92 | #undef CONFIG_CONS_NONE /* define if console on something else*/ |
| 93 | #define CONFIG_CONS_INDEX 2 /* which serial channel for console */ |
| 94 | |
| 95 | /* |
| 96 | * select ethernet configuration |
| 97 | * |
wdenk | aacf9a4 | 2003-01-17 16:27:01 +0000 | [diff] [blame] | 98 | * if CONFIG_ETHER_ON_SCC is selected, then |
| 99 | * - CONFIG_ETHER_INDEX must be set to the channel number (1-4) |
| 100 | * - CONFIG_NET_MULTI must not be defined |
| 101 | * |
| 102 | * if CONFIG_ETHER_ON_FCC is selected, then |
| 103 | * - one or more CONFIG_ETHER_ON_FCCx (x=1,2,3) must also be selected |
| 104 | * - CONFIG_NET_MULTI must be defined |
wdenk | 0f8c976 | 2002-08-19 11:57:05 +0000 | [diff] [blame] | 105 | * |
| 106 | * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be |
| 107 | * defined elsewhere (as for the console), or CFG_CMD_NET must be removed |
| 108 | * from CONFIG_COMMANDS to remove support for networking. |
| 109 | */ |
wdenk | aacf9a4 | 2003-01-17 16:27:01 +0000 | [diff] [blame] | 110 | #define CONFIG_NET_MULTI |
wdenk | 0f8c976 | 2002-08-19 11:57:05 +0000 | [diff] [blame] | 111 | #undef CONFIG_ETHER_NONE /* define if ether on something else */ |
wdenk | 0f8c976 | 2002-08-19 11:57:05 +0000 | [diff] [blame] | 112 | |
wdenk | aacf9a4 | 2003-01-17 16:27:01 +0000 | [diff] [blame] | 113 | #undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */ |
| 114 | #define CONFIG_ETHER_INDEX 1 /* which SCC channel for ethernet */ |
| 115 | |
| 116 | #define CONFIG_ETHER_ON_FCC /* define if ether on FCC */ |
wdenk | 0f8c976 | 2002-08-19 11:57:05 +0000 | [diff] [blame] | 117 | /* |
| 118 | * - Rx-CLK is CLK11 |
| 119 | * - Tx-CLK is CLK10 |
wdenk | aacf9a4 | 2003-01-17 16:27:01 +0000 | [diff] [blame] | 120 | */ |
| 121 | #define CONFIG_ETHER_ON_FCC1 |
| 122 | # define CFG_CMXFCR_MASK1 (CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK) |
| 123 | #ifndef CONFIG_DB_CR826_J30x_ON |
| 124 | # define CFG_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK11|CMXFCR_TF1CS_CLK10) |
| 125 | #else |
| 126 | # define CFG_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK11|CMXFCR_TF1CS_CLK12) |
| 127 | #endif |
| 128 | /* |
| 129 | * - Rx-CLK is CLK15 |
| 130 | * - Tx-CLK is CLK14 |
| 131 | */ |
| 132 | #define CONFIG_ETHER_ON_FCC2 |
| 133 | # define CFG_CMXFCR_MASK2 (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK) |
| 134 | # define CFG_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14) |
| 135 | /* |
wdenk | 0f8c976 | 2002-08-19 11:57:05 +0000 | [diff] [blame] | 136 | * - RAM for BD/Buffers is on the 60x Bus (see 28-13) |
| 137 | * - Enable Full Duplex in FSMR |
| 138 | */ |
wdenk | 0f8c976 | 2002-08-19 11:57:05 +0000 | [diff] [blame] | 139 | # define CFG_CPMFCR_RAMTYPE 0 |
| 140 | # define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) |
| 141 | |
wdenk | 0f8c976 | 2002-08-19 11:57:05 +0000 | [diff] [blame] | 142 | /* system clock rate (CLKIN) - equal to the 60x and local bus speed */ |
| 143 | #define CONFIG_8260_CLKIN 64000000 /* in Hz */ |
| 144 | |
| 145 | #if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC) |
| 146 | #define CONFIG_BAUDRATE 230400 |
| 147 | #else |
| 148 | #define CONFIG_BAUDRATE 9600 |
| 149 | #endif |
| 150 | |
| 151 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
| 152 | #undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ |
| 153 | |
| 154 | #undef CONFIG_WATCHDOG /* watchdog disabled */ |
| 155 | |
| 156 | #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE) |
| 157 | |
| 158 | #define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ |
| 159 | CFG_CMD_BEDBUG | \ |
| 160 | CFG_CMD_DATE | \ |
wdenk | 3bac351 | 2003-03-12 10:41:04 +0000 | [diff] [blame] | 161 | CFG_CMD_DOC | \ |
wdenk | 0f8c976 | 2002-08-19 11:57:05 +0000 | [diff] [blame] | 162 | CFG_CMD_EEPROM | \ |
wdenk | 3bac351 | 2003-03-12 10:41:04 +0000 | [diff] [blame] | 163 | CFG_CMD_I2C ) |
wdenk | 0f8c976 | 2002-08-19 11:57:05 +0000 | [diff] [blame] | 164 | |
| 165 | /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ |
| 166 | #include <cmd_confdefs.h> |
| 167 | |
| 168 | /* |
| 169 | * Disk-On-Chip configuration |
| 170 | */ |
| 171 | |
| 172 | #define CFG_DOC_SHORT_TIMEOUT |
| 173 | #define CFG_MAX_DOC_DEVICE 1 /* Max number of DOC devices */ |
| 174 | |
| 175 | #define CFG_DOC_SUPPORT_2000 |
| 176 | #define CFG_DOC_SUPPORT_MILLENNIUM |
| 177 | |
| 178 | /* |
| 179 | * Miscellaneous configurable options |
| 180 | */ |
| 181 | #define CFG_LONGHELP /* undef to save memory */ |
| 182 | #define CFG_PROMPT "=> " /* Monitor Command Prompt */ |
| 183 | #if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
| 184 | #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
| 185 | #else |
| 186 | #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
| 187 | #endif |
| 188 | #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ |
| 189 | #define CFG_MAXARGS 16 /* max number of command args */ |
| 190 | #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ |
| 191 | |
| 192 | #define CFG_MEMTEST_START 0x0400000 /* memtest works on */ |
| 193 | #define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ |
| 194 | |
| 195 | #define CFG_LOAD_ADDR 0x100000 /* default load address */ |
| 196 | |
| 197 | #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ |
| 198 | |
| 199 | #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
| 200 | |
wdenk | ac6dbb8 | 2003-03-26 11:42:53 +0000 | [diff] [blame] | 201 | #define CFG_RESET_ADDRESS 0xFDFFFFFC /* "bad" address */ |
wdenk | 0f8c976 | 2002-08-19 11:57:05 +0000 | [diff] [blame] | 202 | |
| 203 | /* |
| 204 | * For booting Linux, the board info and command line data |
| 205 | * have to be in the first 8 MB of memory, since this is |
| 206 | * the maximum mapped by the Linux kernel during initialization. |
| 207 | */ |
| 208 | #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
| 209 | |
| 210 | /*----------------------------------------------------------------------- |
| 211 | * Flash and Boot ROM mapping |
| 212 | */ |
| 213 | |
wdenk | 3bac351 | 2003-03-12 10:41:04 +0000 | [diff] [blame] | 214 | #define CFG_BOOTROM_BASE 0xFF800000 |
wdenk | 0f8c976 | 2002-08-19 11:57:05 +0000 | [diff] [blame] | 215 | #define CFG_BOOTROM_SIZE 0x00080000 |
wdenk | 3bac351 | 2003-03-12 10:41:04 +0000 | [diff] [blame] | 216 | #define CFG_FLASH0_BASE 0xFF000000 |
wdenk | 0f8c976 | 2002-08-19 11:57:05 +0000 | [diff] [blame] | 217 | #define CFG_FLASH0_SIZE 0x02000000 |
wdenk | 3bac351 | 2003-03-12 10:41:04 +0000 | [diff] [blame] | 218 | #define CFG_DOC_BASE 0xFF800000 |
wdenk | 0f8c976 | 2002-08-19 11:57:05 +0000 | [diff] [blame] | 219 | #define CFG_DOC_SIZE 0x00100000 |
| 220 | |
| 221 | |
| 222 | /* Flash bank size (for preliminary settings) |
| 223 | */ |
| 224 | #define CFG_FLASH_SIZE CFG_FLASH0_SIZE |
| 225 | |
| 226 | /*----------------------------------------------------------------------- |
| 227 | * FLASH organization |
| 228 | */ |
| 229 | #define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */ |
| 230 | #define CFG_MAX_FLASH_SECT 128 /* max num of sects on one chip */ |
| 231 | |
| 232 | #define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ |
| 233 | #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ |
| 234 | |
| 235 | #if 0 |
| 236 | /* Start port with environment in flash; switch to EEPROM later */ |
| 237 | #define CFG_ENV_IS_IN_FLASH 1 |
| 238 | #define CFG_ENV_ADDR (CFG_FLASH_BASE+0x40000) |
| 239 | #define CFG_ENV_SIZE 0x40000 |
| 240 | #define CFG_ENV_SECT_SIZE 0x40000 |
| 241 | #else |
| 242 | /* Final version: environment in EEPROM */ |
| 243 | #define CFG_ENV_IS_IN_EEPROM 1 |
| 244 | #define CFG_I2C_EEPROM_ADDR 0x58 |
| 245 | #define CFG_I2C_EEPROM_ADDR_LEN 1 |
| 246 | #define CFG_EEPROM_PAGE_WRITE_BITS 4 |
| 247 | #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ |
wdenk | 3bac351 | 2003-03-12 10:41:04 +0000 | [diff] [blame] | 248 | #define CFG_ENV_OFFSET 512 |
| 249 | #define CFG_ENV_SIZE (2048 - 512) |
wdenk | 0f8c976 | 2002-08-19 11:57:05 +0000 | [diff] [blame] | 250 | #endif |
| 251 | |
| 252 | /*----------------------------------------------------------------------- |
| 253 | * Hard Reset Configuration Words |
| 254 | * |
| 255 | * if you change bits in the HRCW, you must also change the CFG_* |
| 256 | * defines for the various registers affected by the HRCW e.g. changing |
| 257 | * HRCW_DPPCxx requires you to also change CFG_SIUMCR. |
| 258 | */ |
| 259 | #if defined(CONFIG_BOOT_ROM) |
| 260 | #define CFG_HRCW_MASTER (HRCW_BPS01 | HRCW_CIP | HRCW_ISB100 | HRCW_BMS) |
| 261 | #else |
| 262 | #define CFG_HRCW_MASTER (HRCW_CIP | HRCW_ISB100 | HRCW_BMS) |
| 263 | #endif |
| 264 | |
| 265 | /* no slaves so just fill with zeros */ |
| 266 | #define CFG_HRCW_SLAVE1 0 |
| 267 | #define CFG_HRCW_SLAVE2 0 |
| 268 | #define CFG_HRCW_SLAVE3 0 |
| 269 | #define CFG_HRCW_SLAVE4 0 |
| 270 | #define CFG_HRCW_SLAVE5 0 |
| 271 | #define CFG_HRCW_SLAVE6 0 |
| 272 | #define CFG_HRCW_SLAVE7 0 |
| 273 | |
| 274 | /*----------------------------------------------------------------------- |
| 275 | * Internal Memory Mapped Register |
| 276 | */ |
| 277 | #define CFG_IMMR 0xF0000000 |
| 278 | |
| 279 | /*----------------------------------------------------------------------- |
| 280 | * Definitions for initial stack pointer and data area (in DPRAM) |
| 281 | */ |
| 282 | #define CFG_INIT_RAM_ADDR CFG_IMMR |
| 283 | #define CFG_INIT_RAM_END 0x4000 /* End of used area in DPRAM */ |
| 284 | #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data*/ |
| 285 | #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) |
| 286 | #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET |
| 287 | |
| 288 | /*----------------------------------------------------------------------- |
| 289 | * Start addresses for the final memory configuration |
| 290 | * (Set up by the startup code) |
| 291 | * Please note that CFG_SDRAM_BASE _must_ start at 0 |
| 292 | * |
| 293 | * 60x SDRAM is mapped at CFG_SDRAM_BASE, local SDRAM |
| 294 | * is mapped at SDRAM_BASE2_PRELIM. |
| 295 | */ |
| 296 | #define CFG_SDRAM_BASE 0x00000000 |
| 297 | #define CFG_FLASH_BASE CFG_FLASH0_BASE |
| 298 | #define CFG_MONITOR_BASE TEXT_BASE |
| 299 | #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ |
| 300 | #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/ |
| 301 | |
| 302 | #if (CFG_MONITOR_BASE < CFG_FLASH_BASE) |
| 303 | # define CFG_RAMBOOT |
| 304 | #endif |
| 305 | |
wdenk | 10f6701 | 2003-03-25 18:06:06 +0000 | [diff] [blame] | 306 | #ifdef CONFIG_PCI |
wdenk | 4d75a50 | 2003-03-25 16:50:56 +0000 | [diff] [blame] | 307 | #define CONFIG_PCI_PNP |
| 308 | #define CONFIG_EEPRO100 |
wdenk | 10f6701 | 2003-03-25 18:06:06 +0000 | [diff] [blame] | 309 | #endif |
wdenk | 4d75a50 | 2003-03-25 16:50:56 +0000 | [diff] [blame] | 310 | |
wdenk | 0f8c976 | 2002-08-19 11:57:05 +0000 | [diff] [blame] | 311 | /* |
| 312 | * Internal Definitions |
| 313 | * |
| 314 | * Boot Flags |
| 315 | */ |
| 316 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH*/ |
| 317 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ |
| 318 | |
| 319 | |
| 320 | /*----------------------------------------------------------------------- |
| 321 | * Cache Configuration |
| 322 | */ |
| 323 | #define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */ |
| 324 | #if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
| 325 | # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
| 326 | #endif |
| 327 | |
| 328 | /*----------------------------------------------------------------------- |
| 329 | * HIDx - Hardware Implementation-dependent Registers 2-11 |
| 330 | *----------------------------------------------------------------------- |
| 331 | * HID0 also contains cache control - initially enable both caches and |
| 332 | * invalidate contents, then the final state leaves only the instruction |
| 333 | * cache enabled. Note that Power-On and Hard reset invalidate the caches, |
| 334 | * but Soft reset does not. |
| 335 | * |
| 336 | * HID1 has only read-only information - nothing to set. |
| 337 | */ |
| 338 | #define CFG_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\ |
| 339 | HID0_IFEM|HID0_ABE) |
| 340 | #define CFG_HID0_FINAL (HID0_ICE|HID0_IFEM|HID0_ABE) |
| 341 | #define CFG_HID2 0 |
| 342 | |
| 343 | /*----------------------------------------------------------------------- |
| 344 | * RMR - Reset Mode Register 5-5 |
| 345 | *----------------------------------------------------------------------- |
| 346 | * turn on Checkstop Reset Enable |
| 347 | */ |
| 348 | #define CFG_RMR RMR_CSRE |
| 349 | |
| 350 | /*----------------------------------------------------------------------- |
| 351 | * BCR - Bus Configuration 4-25 |
| 352 | *----------------------------------------------------------------------- |
| 353 | */ |
| 354 | |
| 355 | #define BCR_APD01 0x10000000 |
| 356 | #define CFG_BCR (BCR_APD01|BCR_ETM|BCR_LETM) /* 8260 mode */ |
| 357 | |
| 358 | /*----------------------------------------------------------------------- |
| 359 | * SIUMCR - SIU Module Configuration 4-31 |
| 360 | *----------------------------------------------------------------------- |
| 361 | */ |
| 362 | #if 0 |
| 363 | #define CFG_SIUMCR (SIUMCR_DPPC00|SIUMCR_APPC10|SIUMCR_CS10PC01) |
| 364 | #else |
| 365 | #define CFG_SIUMCR (SIUMCR_DPPC10|SIUMCR_APPC10) |
| 366 | #endif |
| 367 | |
| 368 | |
| 369 | /*----------------------------------------------------------------------- |
| 370 | * SYPCR - System Protection Control 4-35 |
| 371 | * SYPCR can only be written once after reset! |
| 372 | *----------------------------------------------------------------------- |
| 373 | * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable |
| 374 | */ |
| 375 | #if defined(CONFIG_WATCHDOG) |
| 376 | #define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ |
| 377 | SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE) |
| 378 | #else |
| 379 | #define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ |
| 380 | SYPCR_SWRI|SYPCR_SWP) |
| 381 | #endif /* CONFIG_WATCHDOG */ |
| 382 | |
| 383 | /*----------------------------------------------------------------------- |
| 384 | * TMCNTSC - Time Counter Status and Control 4-40 |
| 385 | *----------------------------------------------------------------------- |
| 386 | * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, |
| 387 | * and enable Time Counter |
| 388 | */ |
| 389 | #define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) |
| 390 | |
| 391 | /*----------------------------------------------------------------------- |
| 392 | * PISCR - Periodic Interrupt Status and Control 4-42 |
| 393 | *----------------------------------------------------------------------- |
| 394 | * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable |
| 395 | * Periodic timer |
| 396 | */ |
| 397 | #define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) |
| 398 | |
| 399 | /*----------------------------------------------------------------------- |
| 400 | * SCCR - System Clock Control 9-8 |
| 401 | *----------------------------------------------------------------------- |
| 402 | */ |
| 403 | #define CFG_SCCR (SCCR_DFBRG01) |
| 404 | |
| 405 | /*----------------------------------------------------------------------- |
| 406 | * RCCR - RISC Controller Configuration 13-7 |
| 407 | *----------------------------------------------------------------------- |
| 408 | */ |
| 409 | #define CFG_RCCR 0 |
| 410 | |
| 411 | /* |
| 412 | * Init Memory Controller: |
| 413 | * |
| 414 | * Bank Bus Machine PortSz Device |
| 415 | * ---- --- ------- ------ ------ |
| 416 | * 0 60x GPCM 64 bit FLASH |
| 417 | * 1 60x SDRAM 64 bit SDRAM |
| 418 | * 2 Local SDRAM 32 bit SDRAM |
| 419 | * |
| 420 | */ |
| 421 | |
| 422 | /* Initialize SDRAM on local bus |
| 423 | */ |
| 424 | #define CFG_INIT_LOCAL_SDRAM |
| 425 | |
| 426 | |
| 427 | /* Minimum mask to separate preliminary |
| 428 | * address ranges for CS[0:2] |
| 429 | */ |
| 430 | #define CFG_MIN_AM_MASK 0xC0000000 |
| 431 | |
| 432 | #define CFG_MPTPR 0x1F00 |
| 433 | |
| 434 | #define CFG_MRS_OFFS 0x00000000 |
| 435 | |
| 436 | |
| 437 | #if defined(CONFIG_BOOT_ROM) |
| 438 | /* |
| 439 | * Bank 0 - Boot ROM (8 bit wide) |
| 440 | */ |
| 441 | #define CFG_BR0_PRELIM ((CFG_BOOTROM_BASE & BRx_BA_MSK)|\ |
| 442 | BRx_PS_8 |\ |
| 443 | BRx_MS_GPCM_P |\ |
| 444 | BRx_V) |
| 445 | |
| 446 | #define CFG_OR0_PRELIM (P2SZ_TO_AM(CFG_BOOTROM_SIZE) |\ |
| 447 | ORxG_CSNT |\ |
| 448 | ORxG_ACS_DIV1 |\ |
| 449 | ORxG_SCY_3_CLK |\ |
| 450 | ORxG_EHTR |\ |
| 451 | ORxG_TRLX) |
| 452 | |
| 453 | /* |
| 454 | * Bank 1 - Flash (64 bit wide) |
| 455 | */ |
| 456 | #define CFG_BR1_PRELIM ((CFG_FLASH_BASE & BRx_BA_MSK) |\ |
| 457 | BRx_PS_64 |\ |
| 458 | BRx_MS_GPCM_P |\ |
| 459 | BRx_V) |
| 460 | |
| 461 | #define CFG_OR1_PRELIM (P2SZ_TO_AM(CFG_FLASH_SIZE) |\ |
| 462 | ORxG_CSNT |\ |
| 463 | ORxG_ACS_DIV1 |\ |
| 464 | ORxG_SCY_3_CLK |\ |
| 465 | ORxG_EHTR |\ |
| 466 | ORxG_TRLX) |
| 467 | |
| 468 | #else /* ! CONFIG_BOOT_ROM */ |
| 469 | |
| 470 | /* |
| 471 | * Bank 0 - Flash (64 bit wide) |
| 472 | */ |
| 473 | #define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BRx_BA_MSK) |\ |
| 474 | BRx_PS_64 |\ |
| 475 | BRx_MS_GPCM_P |\ |
| 476 | BRx_V) |
| 477 | |
| 478 | #define CFG_OR0_PRELIM (P2SZ_TO_AM(CFG_FLASH_SIZE) |\ |
| 479 | ORxG_CSNT |\ |
| 480 | ORxG_ACS_DIV1 |\ |
| 481 | ORxG_SCY_3_CLK |\ |
| 482 | ORxG_EHTR |\ |
| 483 | ORxG_TRLX) |
| 484 | |
| 485 | /* |
| 486 | * Bank 1 - Disk-On-Chip |
| 487 | */ |
| 488 | #define CFG_BR1_PRELIM ((CFG_DOC_BASE & BRx_BA_MSK) |\ |
| 489 | BRx_PS_8 |\ |
| 490 | BRx_MS_GPCM_P |\ |
| 491 | BRx_V) |
| 492 | |
| 493 | #define CFG_OR1_PRELIM (P2SZ_TO_AM(CFG_DOC_SIZE) |\ |
| 494 | ORxG_CSNT |\ |
| 495 | ORxG_ACS_DIV1 |\ |
| 496 | ORxG_SCY_3_CLK |\ |
| 497 | ORxG_EHTR |\ |
| 498 | ORxG_TRLX) |
| 499 | |
| 500 | #endif /* CONFIG_BOOT_ROM */ |
| 501 | |
| 502 | /* Bank 2 - SDRAM |
| 503 | */ |
| 504 | #define CFG_PSRT 0x0F |
| 505 | #ifndef CFG_RAMBOOT |
| 506 | #define CFG_BR2_PRELIM ((CFG_SDRAM_BASE & BRx_BA_MSK) |\ |
| 507 | BRx_PS_64 |\ |
| 508 | BRx_MS_SDRAM_P |\ |
| 509 | BRx_V) |
| 510 | |
| 511 | /* SDRAM initialization values for 8-column chips |
| 512 | */ |
| 513 | #define CFG_OR2_8COL (CFG_MIN_AM_MASK |\ |
| 514 | ORxS_BPD_4 |\ |
| 515 | ORxS_ROWST_PBI0_A9 |\ |
| 516 | ORxS_NUMR_12) |
| 517 | |
| 518 | #define CFG_PSDMR_8COL (PSDMR_SDAM_A13_IS_A5 |\ |
| 519 | PSDMR_BSMA_A14_A16 |\ |
| 520 | PSDMR_SDA10_PBI0_A10 |\ |
| 521 | PSDMR_RFRC_7_CLK |\ |
| 522 | PSDMR_PRETOACT_2W |\ |
| 523 | PSDMR_ACTTORW_1W |\ |
| 524 | PSDMR_LDOTOPRE_1C |\ |
| 525 | PSDMR_WRC_1C |\ |
| 526 | PSDMR_CL_2) |
| 527 | |
| 528 | /* SDRAM initialization values for 9-column chips |
| 529 | */ |
| 530 | #define CFG_OR2_9COL (CFG_MIN_AM_MASK |\ |
| 531 | ORxS_BPD_4 |\ |
| 532 | ORxS_ROWST_PBI0_A7 |\ |
| 533 | ORxS_NUMR_13) |
| 534 | |
| 535 | #define CFG_PSDMR_9COL (PSDMR_SDAM_A14_IS_A5 |\ |
| 536 | PSDMR_BSMA_A13_A15 |\ |
| 537 | PSDMR_SDA10_PBI0_A9 |\ |
| 538 | PSDMR_RFRC_7_CLK |\ |
| 539 | PSDMR_PRETOACT_2W |\ |
| 540 | PSDMR_ACTTORW_1W |\ |
| 541 | PSDMR_LDOTOPRE_1C |\ |
| 542 | PSDMR_WRC_1C |\ |
| 543 | PSDMR_CL_2) |
| 544 | |
| 545 | #define CFG_OR2_PRELIM CFG_OR2_9COL |
| 546 | #define CFG_PSDMR CFG_PSDMR_9COL |
| 547 | |
| 548 | #endif /* CFG_RAMBOOT */ |
| 549 | |
| 550 | #endif /* __CONFIG_H */ |