blob: 19e0e30eef1cea5241a9d4c182a44c5ac6d8c4b8 [file] [log] [blame]
Kim Phillips5e918a92008-01-16 00:38:05 -06001/*
2 * Copyright (C) 2007 Freescale Semiconductor, Inc.
3 * Kevin Lam <kevin.lam@freescale.com>
4 * Joe D'Abbraccio <joe.d'abbraccio@freescale.com>
5 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02006 * SPDX-License-Identifier: GPL-2.0+
Kim Phillips5e918a92008-01-16 00:38:05 -06007 */
8
9#ifndef __CONFIG_H
10#define __CONFIG_H
11
12/*
13 * High Level Configuration Options
14 */
15#define CONFIG_E300 1 /* E300 family */
Peter Tyser2c7920a2009-05-22 17:23:25 -050016#define CONFIG_MPC837x 1 /* MPC837x CPU specific */
Kim Phillips5e918a92008-01-16 00:38:05 -060017#define CONFIG_MPC837XERDB 1
Sinan Akman77d52ed2015-01-17 02:09:13 -050018#define CONFIG_DISPLAY_BOARDINFO
19#define CONFIG_SYS_GENERIC_BOARD
Kim Phillips5e918a92008-01-16 00:38:05 -060020
Wolfgang Denk2ae18242010-10-06 09:05:45 +020021#define CONFIG_SYS_TEXT_BASE 0xFE000000
22
Kim Phillips5e918a92008-01-16 00:38:05 -060023#define CONFIG_PCI 1
24
Anton Vorontsov2bd74602008-03-24 17:40:43 +030025#define CONFIG_BOARD_EARLY_INIT_F
Timur Tabi89c77842008-02-08 13:15:55 -060026#define CONFIG_MISC_INIT_R
Anton Vorontsovc9646ed2009-06-10 00:25:30 +040027#define CONFIG_HWCONFIG
Timur Tabi89c77842008-02-08 13:15:55 -060028
29/*
30 * On-board devices
31 */
32#define CONFIG_TSEC_ENET /* TSEC Ethernet support */
33#define CONFIG_VSC7385_ENET
34
Kim Phillips5e918a92008-01-16 00:38:05 -060035/*
36 * System Clock Setup
37 */
38#ifdef CONFIG_PCISLAVE
39#define CONFIG_83XX_PCICLK 66666667 /* in HZ */
40#else
41#define CONFIG_83XX_CLKIN 66666667 /* in Hz */
Kim Phillipsbe9b56d2009-07-23 14:09:38 -050042#define CONFIG_PCIE
Kim Phillips5e918a92008-01-16 00:38:05 -060043#endif
44
45#ifndef CONFIG_SYS_CLK_FREQ
46#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
47#endif
48
49/*
50 * Hardware Reset Configuration Word
51 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020052#define CONFIG_SYS_HRCW_LOW (\
Kim Phillips5e918a92008-01-16 00:38:05 -060053 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
54 HRCWL_DDR_TO_SCB_CLK_1X1 |\
55 HRCWL_SVCOD_DIV_2 |\
56 HRCWL_CSB_TO_CLKIN_5X1 |\
57 HRCWL_CORE_TO_CSB_2X1)
58
59#ifdef CONFIG_PCISLAVE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020060#define CONFIG_SYS_HRCW_HIGH (\
Kim Phillips5e918a92008-01-16 00:38:05 -060061 HRCWH_PCI_AGENT |\
62 HRCWH_PCI1_ARBITER_DISABLE |\
63 HRCWH_CORE_ENABLE |\
64 HRCWH_FROM_0XFFF00100 |\
65 HRCWH_BOOTSEQ_DISABLE |\
66 HRCWH_SW_WATCHDOG_DISABLE |\
67 HRCWH_ROM_LOC_LOCAL_16BIT |\
68 HRCWH_RL_EXT_LEGACY |\
69 HRCWH_TSEC1M_IN_RGMII |\
70 HRCWH_TSEC2M_IN_RGMII |\
71 HRCWH_BIG_ENDIAN |\
72 HRCWH_LDP_CLEAR)
73#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020074#define CONFIG_SYS_HRCW_HIGH (\
Kim Phillips5e918a92008-01-16 00:38:05 -060075 HRCWH_PCI_HOST |\
76 HRCWH_PCI1_ARBITER_ENABLE |\
77 HRCWH_CORE_ENABLE |\
78 HRCWH_FROM_0X00000100 |\
79 HRCWH_BOOTSEQ_DISABLE |\
80 HRCWH_SW_WATCHDOG_DISABLE |\
81 HRCWH_ROM_LOC_LOCAL_16BIT |\
82 HRCWH_RL_EXT_LEGACY |\
83 HRCWH_TSEC1M_IN_RGMII |\
84 HRCWH_TSEC2M_IN_RGMII |\
85 HRCWH_BIG_ENDIAN |\
86 HRCWH_LDP_CLEAR)
87#endif
88
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020089/* System performance - define the value i.e. CONFIG_SYS_XXX
Kim Phillips5e918a92008-01-16 00:38:05 -060090*/
91
92/* Arbiter Configuration Register */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020093#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
Joe Hershberger5afe9722011-10-11 23:57:19 -050094#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
Kim Phillips5e918a92008-01-16 00:38:05 -060095
96/* System Priority Control Regsiter */
Joe Hershberger5afe9722011-10-11 23:57:19 -050097#define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC1&2 emergency priority (0-3) */
Kim Phillips5e918a92008-01-16 00:38:05 -060098
99/* System Clock Configuration Register */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200100#define CONFIG_SYS_SCCR_TSEC1CM 1 /* eTSEC1 clock mode (0-3) */
101#define CONFIG_SYS_SCCR_TSEC2CM 1 /* eTSEC2 clock mode (0-3) */
Joe Hershberger5afe9722011-10-11 23:57:19 -0500102#define CONFIG_SYS_SCCR_SATACM SCCR_SATACM_2 /* SATA1-4 clock mode (0-3) */
Kim Phillips5e918a92008-01-16 00:38:05 -0600103
104/*
105 * System IO Config
106 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200107#define CONFIG_SYS_SICRH 0x08200000
108#define CONFIG_SYS_SICRL 0x00000000
Kim Phillips5e918a92008-01-16 00:38:05 -0600109
110/*
111 * Output Buffer Impedance
112 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200113#define CONFIG_SYS_OBIR 0x30100000
Kim Phillips5e918a92008-01-16 00:38:05 -0600114
115/*
116 * IMMR new address
117 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200118#define CONFIG_SYS_IMMR 0xE0000000
Kim Phillips5e918a92008-01-16 00:38:05 -0600119
120/*
Timur Tabi89c77842008-02-08 13:15:55 -0600121 * Device configurations
122 */
123
124/* Vitesse 7385 */
125
126#ifdef CONFIG_VSC7385_ENET
127
128#define CONFIG_TSEC2
129
130/* The flash address and size of the VSC7385 firmware image */
131#define CONFIG_VSC7385_IMAGE 0xFE7FE000
132#define CONFIG_VSC7385_IMAGE_SIZE 8192
133
134#endif
135
136/*
Kim Phillips5e918a92008-01-16 00:38:05 -0600137 * DDR Setup
138 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200139#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
140#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
141#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
142#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL 0x03000000
143#define CONFIG_SYS_83XX_DDR_USES_CS0
Kim Phillips5e918a92008-01-16 00:38:05 -0600144
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200145#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_DHC_EN | DDRCDR_ODT | DDRCDR_Q_DRN)
Kim Phillips5e918a92008-01-16 00:38:05 -0600146
147#undef CONFIG_DDR_ECC /* support DDR ECC function */
148#undef CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */
149
150#undef CONFIG_NEVER_ASSERT_ODT_TO_CPU /* Never assert ODT to internal IOs */
151
152/*
153 * Manually set up DDR parameters
154 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200155#define CONFIG_SYS_DDR_SIZE 256 /* MB */
Joe Hershberger2fef4022011-10-11 23:57:29 -0500156#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f
157#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
158 | CSCONFIG_ODT_WR_ONLY_CURRENT \
159 | CSCONFIG_ROW_BIT_13 \
160 | CSCONFIG_COL_BIT_10)
Kim Phillips5e918a92008-01-16 00:38:05 -0600161
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200162#define CONFIG_SYS_DDR_TIMING_3 0x00000000
163#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
Kim Phillips5e918a92008-01-16 00:38:05 -0600164 | (0 << TIMING_CFG0_WRT_SHIFT) \
165 | (0 << TIMING_CFG0_RRT_SHIFT) \
166 | (0 << TIMING_CFG0_WWT_SHIFT) \
167 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
168 | (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
169 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
170 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
Kim Phillips5e918a92008-01-16 00:38:05 -0600171 /* 0x00260802 */ /* DDR400 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200172#define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
Kim Phillips5e918a92008-01-16 00:38:05 -0600173 | (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \
174 | (3 << TIMING_CFG1_ACTTORW_SHIFT) \
175 | (7 << TIMING_CFG1_CASLAT_SHIFT) \
176 | (13 << TIMING_CFG1_REFREC_SHIFT) \
177 | (3 << TIMING_CFG1_WRREC_SHIFT) \
178 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
179 | (2 << TIMING_CFG1_WRTORD_SHIFT))
Kim Phillips5e918a92008-01-16 00:38:05 -0600180 /* 0x3937d322 */
Joe Hershberger2fef4022011-10-11 23:57:29 -0500181#define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
182 | (5 << TIMING_CFG2_CPO_SHIFT) \
183 | (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
184 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
185 | (3 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
186 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
187 | (8 << TIMING_CFG2_FOUR_ACT_SHIFT))
188 /* 0x02984cc8 */
Kim Phillips5e918a92008-01-16 00:38:05 -0600189
Kim Phillips8eceeb72009-08-21 16:33:15 -0500190#define CONFIG_SYS_DDR_INTERVAL ((1024 << SDRAM_INTERVAL_REFINT_SHIFT) \
191 | (0 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
Kim Phillips5e918a92008-01-16 00:38:05 -0600192 /* 0x06090100 */
193
194#if defined(CONFIG_DDR_2T_TIMING)
Joe Hershberger5afe9722011-10-11 23:57:19 -0500195#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
Joe Hershberger2fef4022011-10-11 23:57:29 -0500196 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
197 | SDRAM_CFG_32_BE \
198 | SDRAM_CFG_2T_EN)
199 /* 0x43088000 */
Kim Phillips5e918a92008-01-16 00:38:05 -0600200#else
Joe Hershberger5afe9722011-10-11 23:57:19 -0500201#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
Joe Hershberger2fef4022011-10-11 23:57:29 -0500202 | SDRAM_CFG_SDRAM_TYPE_DDR2)
Joe Hershberger5afe9722011-10-11 23:57:19 -0500203 /* 0x43000000 */
Kim Phillips5e918a92008-01-16 00:38:05 -0600204#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200205#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00001000 /* 1 posted refresh */
Kim Phillips8eceeb72009-08-21 16:33:15 -0500206#define CONFIG_SYS_DDR_MODE ((0x0406 << SDRAM_MODE_ESD_SHIFT) \
Joe Hershberger5afe9722011-10-11 23:57:19 -0500207 | (0x0442 << SDRAM_MODE_SD_SHIFT))
208 /* 0x04400442 */ /* DDR400 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200209#define CONFIG_SYS_DDR_MODE2 0x00000000
Kim Phillips5e918a92008-01-16 00:38:05 -0600210
211/*
212 * Memory test
213 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200214#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
215#define CONFIG_SYS_MEMTEST_START 0x00040000 /* memtest region */
216#define CONFIG_SYS_MEMTEST_END 0x0ef70010
Kim Phillips5e918a92008-01-16 00:38:05 -0600217
218/*
219 * The reserved memory
220 */
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200221#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
Kim Phillips5e918a92008-01-16 00:38:05 -0600222
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200223#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
224#define CONFIG_SYS_RAMBOOT
Kim Phillips5e918a92008-01-16 00:38:05 -0600225#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200226#undef CONFIG_SYS_RAMBOOT
Kim Phillips5e918a92008-01-16 00:38:05 -0600227#endif
228
Joe Hershberger5afe9722011-10-11 23:57:19 -0500229#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
230#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
Kim Phillips5e918a92008-01-16 00:38:05 -0600231
232/*
233 * Initial RAM Base Address Setup
234 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200235#define CONFIG_SYS_INIT_RAM_LOCK 1
236#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200237#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
Joe Hershberger5afe9722011-10-11 23:57:19 -0500238#define CONFIG_SYS_GBL_DATA_OFFSET \
239 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Kim Phillips5e918a92008-01-16 00:38:05 -0600240
241/*
242 * Local Bus Configuration & Clock Setup
243 */
Kim Phillipsc7190f02009-09-25 18:19:44 -0500244#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
245#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_8
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200246#define CONFIG_SYS_LBC_LBCR 0x00000000
Becky Bruce0914f482010-06-17 11:37:18 -0500247#define CONFIG_FSL_ELBC 1
Kim Phillips5e918a92008-01-16 00:38:05 -0600248
249/*
250 * FLASH on the Local Bus
251 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200252#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200253#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200254#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
255#define CONFIG_SYS_FLASH_SIZE 8 /* max FLASH size is 32M */
Kim Phillips5e918a92008-01-16 00:38:05 -0600256
Joe Hershberger5afe9722011-10-11 23:57:19 -0500257#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
258#define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */
259#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* buffer up multiple bytes */
Kim Phillips5e918a92008-01-16 00:38:05 -0600260
Joe Hershberger5afe9722011-10-11 23:57:19 -0500261 /* Window base at flash base */
262#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200263#define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000016 /* 8 MB window size */
Kim Phillips5e918a92008-01-16 00:38:05 -0600264
Joe Hershberger5afe9722011-10-11 23:57:19 -0500265#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500266 | BR_PS_16 /* 16 bit port */ \
267 | BR_MS_GPCM /* MSEL = GPCM */ \
268 | BR_V) /* valid */
269#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
Kim Phillips5e918a92008-01-16 00:38:05 -0600270 | OR_GPCM_XACS \
271 | OR_GPCM_SCY_9 \
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500272 | OR_GPCM_EHTR_SET \
Kim Phillips5e918a92008-01-16 00:38:05 -0600273 | OR_GPCM_EAD)
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500274 /* 0xFF800191 */
Kim Phillips5e918a92008-01-16 00:38:05 -0600275
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200276#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
277#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */
Kim Phillips5e918a92008-01-16 00:38:05 -0600278
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200279#undef CONFIG_SYS_FLASH_CHECKSUM
280#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
281#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
Kim Phillips5e918a92008-01-16 00:38:05 -0600282
Anton Vorontsov46a3aee2008-03-24 17:40:23 +0300283/*
284 * NAND Flash on the Local Bus
285 */
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500286#define CONFIG_SYS_NAND_BASE 0xE0600000
Joe Hershberger5afe9722011-10-11 23:57:19 -0500287#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_NAND_BASE \
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500288 | BR_DECC_CHK_GEN /* Use HW ECC */ \
289 | BR_PS_8 /* 8 bit port */ \
290 | BR_MS_FCM /* MSEL = FCM */ \
Joe Hershberger5afe9722011-10-11 23:57:19 -0500291 | BR_V) /* valid */
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500292#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \
Joe Hershberger5afe9722011-10-11 23:57:19 -0500293 | OR_FCM_CSCT \
294 | OR_FCM_CST \
295 | OR_FCM_CHT \
296 | OR_FCM_SCY_1 \
297 | OR_FCM_TRLX \
298 | OR_FCM_EHTR)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200299#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500300#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
Anton Vorontsov46a3aee2008-03-24 17:40:23 +0300301
Timur Tabi89c77842008-02-08 13:15:55 -0600302/* Vitesse 7385 */
303
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200304#define CONFIG_SYS_VSC7385_BASE 0xF0000000
Kim Phillips5e918a92008-01-16 00:38:05 -0600305
Timur Tabi89c77842008-02-08 13:15:55 -0600306#ifdef CONFIG_VSC7385_ENET
307
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500308#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_VSC7385_BASE \
309 | BR_PS_8 \
310 | BR_MS_GPCM \
311 | BR_V)
312 /* 0xF0000801 */
313#define CONFIG_SYS_OR2_PRELIM (OR_AM_128KB \
314 | OR_GPCM_CSNT \
315 | OR_GPCM_XACS \
316 | OR_GPCM_SCY_15 \
317 | OR_GPCM_SETA \
318 | OR_GPCM_TRLX_SET \
319 | OR_GPCM_EHTR_SET \
320 | OR_GPCM_EAD)
321 /* 0xfffe09ff */
322
Joe Hershberger5afe9722011-10-11 23:57:19 -0500323 /* Access Base */
324#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VSC7385_BASE
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500325#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_128KB)
Kim Phillips5e918a92008-01-16 00:38:05 -0600326
Timur Tabi89c77842008-02-08 13:15:55 -0600327#endif
328
Kim Phillips5e918a92008-01-16 00:38:05 -0600329/*
330 * Serial Port
331 */
332#define CONFIG_CONS_INDEX 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200333#define CONFIG_SYS_NS16550
334#define CONFIG_SYS_NS16550_SERIAL
335#define CONFIG_SYS_NS16550_REG_SIZE 1
336#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
Kim Phillips5e918a92008-01-16 00:38:05 -0600337
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200338#define CONFIG_SYS_BAUDRATE_TABLE \
Joe Hershberger5afe9722011-10-11 23:57:19 -0500339 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
Kim Phillips5e918a92008-01-16 00:38:05 -0600340
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200341#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
342#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
Kim Phillips5e918a92008-01-16 00:38:05 -0600343
Anton Vorontsov2bd74602008-03-24 17:40:43 +0300344/* SERDES */
345#define CONFIG_FSL_SERDES
346#define CONFIG_FSL_SERDES1 0xe3000
347#define CONFIG_FSL_SERDES2 0xe3100
348
Kim Phillips5e918a92008-01-16 00:38:05 -0600349/* Use the HUSH parser */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200350#define CONFIG_SYS_HUSH_PARSER
Kim Phillips5e918a92008-01-16 00:38:05 -0600351
352/* Pass open firmware flat tree */
353#define CONFIG_OF_LIBFDT 1
354#define CONFIG_OF_BOARD_SETUP 1
Anton Vorontsovaabce7f2008-03-24 17:40:47 +0300355#define CONFIG_OF_STDOUT_VIA_ALIAS 1
Kim Phillips5e918a92008-01-16 00:38:05 -0600356
357/* I2C */
Heiko Schocher00f792e2012-10-24 13:48:22 +0200358#define CONFIG_SYS_I2C
359#define CONFIG_SYS_I2C_FSL
360#define CONFIG_SYS_FSL_I2C_SPEED 400000
361#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
362#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
363#define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} }
Kim Phillips5e918a92008-01-16 00:38:05 -0600364
365/*
366 * Config on-board RTC
367 */
368#define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200369#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
Kim Phillips5e918a92008-01-16 00:38:05 -0600370
371/*
372 * General PCI
373 * Addresses are mapped 1-1.
374 */
Joe Hershberger5afe9722011-10-11 23:57:19 -0500375#define CONFIG_SYS_PCI_MEM_BASE 0x80000000
376#define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE
377#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200378#define CONFIG_SYS_PCI_MMIO_BASE 0x90000000
379#define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE
380#define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */
381#define CONFIG_SYS_PCI_IO_BASE 0x00000000
382#define CONFIG_SYS_PCI_IO_PHYS 0xE0300000
383#define CONFIG_SYS_PCI_IO_SIZE 0x100000 /* 1M */
Kim Phillips5e918a92008-01-16 00:38:05 -0600384
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200385#define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE
386#define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000
387#define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000
Kim Phillips5e918a92008-01-16 00:38:05 -0600388
Anton Vorontsov7e915582009-02-19 18:20:52 +0300389#define CONFIG_SYS_PCIE1_BASE 0xA0000000
390#define CONFIG_SYS_PCIE1_CFG_BASE 0xA0000000
391#define CONFIG_SYS_PCIE1_CFG_SIZE 0x08000000
392#define CONFIG_SYS_PCIE1_MEM_BASE 0xA8000000
393#define CONFIG_SYS_PCIE1_MEM_PHYS 0xA8000000
394#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
395#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
396#define CONFIG_SYS_PCIE1_IO_PHYS 0xB8000000
397#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000
398
399#define CONFIG_SYS_PCIE2_BASE 0xC0000000
400#define CONFIG_SYS_PCIE2_CFG_BASE 0xC0000000
401#define CONFIG_SYS_PCIE2_CFG_SIZE 0x08000000
402#define CONFIG_SYS_PCIE2_MEM_BASE 0xC8000000
403#define CONFIG_SYS_PCIE2_MEM_PHYS 0xC8000000
404#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000
405#define CONFIG_SYS_PCIE2_IO_BASE 0x00000000
406#define CONFIG_SYS_PCIE2_IO_PHYS 0xD8000000
407#define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000
408
Kim Phillips5e918a92008-01-16 00:38:05 -0600409#ifdef CONFIG_PCI
Gabor Juhos842033e2013-05-30 07:06:12 +0000410#define CONFIG_PCI_INDIRECT_BRIDGE
Kim Phillips5e918a92008-01-16 00:38:05 -0600411#define CONFIG_PCI_PNP /* do pci plug-and-play */
412
Kim Phillips5e918a92008-01-16 00:38:05 -0600413#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200414#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
Kim Phillips5e918a92008-01-16 00:38:05 -0600415#endif /* CONFIG_PCI */
416
Kim Phillips5e918a92008-01-16 00:38:05 -0600417/*
418 * TSEC
419 */
Timur Tabi89c77842008-02-08 13:15:55 -0600420#ifdef CONFIG_TSEC_ENET
Kim Phillips5e918a92008-01-16 00:38:05 -0600421
Timur Tabi89c77842008-02-08 13:15:55 -0600422#define CONFIG_GMII /* MII PHY management */
423
424#define CONFIG_TSEC1
425
426#ifdef CONFIG_TSEC1
427#define CONFIG_HAS_ETH0
Kim Phillips5e918a92008-01-16 00:38:05 -0600428#define CONFIG_TSEC1_NAME "TSEC0"
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200429#define CONFIG_SYS_TSEC1_OFFSET 0x24000
Kim Phillips5e918a92008-01-16 00:38:05 -0600430#define TSEC1_PHY_ADDR 2
Kim Phillips5e918a92008-01-16 00:38:05 -0600431#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
Kim Phillips5e918a92008-01-16 00:38:05 -0600432#define TSEC1_PHYIDX 0
Timur Tabi89c77842008-02-08 13:15:55 -0600433#endif
Kim Phillips5e918a92008-01-16 00:38:05 -0600434
Timur Tabi89c77842008-02-08 13:15:55 -0600435#ifdef CONFIG_TSEC2
436#define CONFIG_HAS_ETH1
437#define CONFIG_TSEC2_NAME "TSEC1"
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200438#define CONFIG_SYS_TSEC2_OFFSET 0x25000
Timur Tabi89c77842008-02-08 13:15:55 -0600439#define TSEC2_PHY_ADDR 0x1c
440#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
441#define TSEC2_PHYIDX 0
442#endif
Kim Phillips5e918a92008-01-16 00:38:05 -0600443
444/* Options are: TSEC[0-1] */
445#define CONFIG_ETHPRIME "TSEC0"
446
Timur Tabi89c77842008-02-08 13:15:55 -0600447#endif
448
Kim Phillips5e918a92008-01-16 00:38:05 -0600449/*
Kim Phillips730e7922008-03-28 14:31:23 -0500450 * SATA
451 */
452#define CONFIG_LIBATA
453#define CONFIG_FSL_SATA
454
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200455#define CONFIG_SYS_SATA_MAX_DEVICE 2
Kim Phillips730e7922008-03-28 14:31:23 -0500456#define CONFIG_SATA1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200457#define CONFIG_SYS_SATA1_OFFSET 0x18000
Joe Hershberger5afe9722011-10-11 23:57:19 -0500458#define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET)
459#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
Kim Phillips730e7922008-03-28 14:31:23 -0500460#define CONFIG_SATA2
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200461#define CONFIG_SYS_SATA2_OFFSET 0x19000
Joe Hershberger5afe9722011-10-11 23:57:19 -0500462#define CONFIG_SYS_SATA2 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET)
463#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
Kim Phillips730e7922008-03-28 14:31:23 -0500464
465#ifdef CONFIG_FSL_SATA
466#define CONFIG_LBA48
467#define CONFIG_CMD_SATA
468#define CONFIG_DOS_PARTITION
469#define CONFIG_CMD_EXT2
470#endif
471
472/*
Kim Phillips5e918a92008-01-16 00:38:05 -0600473 * Environment
474 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200475#ifndef CONFIG_SYS_RAMBOOT
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200476 #define CONFIG_ENV_IS_IN_FLASH 1
Joe Hershberger5afe9722011-10-11 23:57:19 -0500477 #define CONFIG_ENV_ADDR \
478 (CONFIG_SYS_MONITOR_BASE+CONFIG_SYS_MONITOR_LEN)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200479 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) for env */
480 #define CONFIG_ENV_SIZE 0x4000
Kim Phillips5e918a92008-01-16 00:38:05 -0600481#else
Joe Hershberger5afe9722011-10-11 23:57:19 -0500482 #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
Jean-Christophe PLAGNIOL-VILLARD93f6d722008-09-10 22:48:00 +0200483 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200484 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-0x1000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200485 #define CONFIG_ENV_SIZE 0x2000
Kim Phillips5e918a92008-01-16 00:38:05 -0600486#endif
487
488#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200489#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
Kim Phillips5e918a92008-01-16 00:38:05 -0600490
491/*
492 * BOOTP options
493 */
494#define CONFIG_BOOTP_BOOTFILESIZE
495#define CONFIG_BOOTP_BOOTPATH
496#define CONFIG_BOOTP_GATEWAY
497#define CONFIG_BOOTP_HOSTNAME
498
499
500/*
501 * Command line configuration.
502 */
503#include <config_cmd_default.h>
504
505#define CONFIG_CMD_PING
506#define CONFIG_CMD_I2C
507#define CONFIG_CMD_MII
508#define CONFIG_CMD_DATE
509
510#if defined(CONFIG_PCI)
511#define CONFIG_CMD_PCI
512#endif
513
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200514#if defined(CONFIG_SYS_RAMBOOT)
Mike Frysingerbdab39d2009-01-28 19:08:14 -0500515#undef CONFIG_CMD_SAVEENV
Kim Phillips5e918a92008-01-16 00:38:05 -0600516#undef CONFIG_CMD_LOADS
517#endif
518
519#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
Joe Hershberger5afe9722011-10-11 23:57:19 -0500520#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
Kim Phillips5e918a92008-01-16 00:38:05 -0600521
522#undef CONFIG_WATCHDOG /* watchdog disabled */
523
Anton Vorontsovc9646ed2009-06-10 00:25:30 +0400524#define CONFIG_MMC 1
525
526#ifdef CONFIG_MMC
527#define CONFIG_FSL_ESDHC
Chenhui Zhaoa6da8b82011-01-04 17:23:05 +0800528#define CONFIG_FSL_ESDHC_PIN_MUX
Anton Vorontsovc9646ed2009-06-10 00:25:30 +0400529#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR
530#define CONFIG_CMD_MMC
531#define CONFIG_GENERIC_MMC
532#define CONFIG_CMD_EXT2
533#define CONFIG_CMD_FAT
534#define CONFIG_DOS_PARTITION
535#endif
536
Kim Phillips5e918a92008-01-16 00:38:05 -0600537/*
538 * Miscellaneous configurable options
539 */
Joe Hershberger5afe9722011-10-11 23:57:19 -0500540#define CONFIG_SYS_LONGHELP /* undef to save memory */
541#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Kim Phillips5e918a92008-01-16 00:38:05 -0600542
543#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200544 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Kim Phillips5e918a92008-01-16 00:38:05 -0600545#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200546 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Kim Phillips5e918a92008-01-16 00:38:05 -0600547#endif
548
Joe Hershberger5afe9722011-10-11 23:57:19 -0500549 /* Print Buffer Size */
550#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
551#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
552 /* Boot Argument Buffer Size */
553#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
Kim Phillips5e918a92008-01-16 00:38:05 -0600554
555/*
556 * For booting Linux, the board info and command line data
Ira W. Snyder9f530d52010-09-10 15:42:32 -0700557 * have to be in the first 256 MB of memory, since this is
Kim Phillips5e918a92008-01-16 00:38:05 -0600558 * the maximum mapped by the Linux kernel during initialization.
559 */
Joe Hershberger5afe9722011-10-11 23:57:19 -0500560#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
Kim Phillips5e918a92008-01-16 00:38:05 -0600561
562/*
563 * Core HID Setup
564 */
Kim Phillips1a2e2032010-04-20 19:37:54 -0500565#define CONFIG_SYS_HID0_INIT 0x000000000
Joe Hershberger5afe9722011-10-11 23:57:19 -0500566#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK \
567 | HID0_ENABLE_INSTRUCTION_CACHE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200568#define CONFIG_SYS_HID2 HID2_HBE
Kim Phillips5e918a92008-01-16 00:38:05 -0600569
570/*
571 * MMU Setup
572 */
573
Becky Bruce31d82672008-05-08 19:02:12 -0500574#define CONFIG_HIGH_BATS 1 /* High BATs supported */
575
Kim Phillips5e918a92008-01-16 00:38:05 -0600576/* DDR: cache cacheable */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200577#define CONFIG_SYS_SDRAM_LOWER CONFIG_SYS_SDRAM_BASE
578#define CONFIG_SYS_SDRAM_UPPER (CONFIG_SYS_SDRAM_BASE + 0x10000000)
Kim Phillips5e918a92008-01-16 00:38:05 -0600579
Joe Hershberger5afe9722011-10-11 23:57:19 -0500580#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_LOWER \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500581 | BATL_PP_RW \
Joe Hershberger5afe9722011-10-11 23:57:19 -0500582 | BATL_MEMCOHERENCE)
583#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_LOWER \
584 | BATU_BL_256M \
585 | BATU_VS \
586 | BATU_VP)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200587#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
588#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
Kim Phillips5e918a92008-01-16 00:38:05 -0600589
Joe Hershberger5afe9722011-10-11 23:57:19 -0500590#define CONFIG_SYS_IBAT1L (CONFIG_SYS_SDRAM_UPPER \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500591 | BATL_PP_RW \
Joe Hershberger5afe9722011-10-11 23:57:19 -0500592 | BATL_MEMCOHERENCE)
593#define CONFIG_SYS_IBAT1U (CONFIG_SYS_SDRAM_UPPER \
594 | BATU_BL_256M \
595 | BATU_VS \
596 | BATU_VP)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200597#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
598#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
Kim Phillips5e918a92008-01-16 00:38:05 -0600599
600/* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
Joe Hershberger5afe9722011-10-11 23:57:19 -0500601#define CONFIG_SYS_IBAT2L (CONFIG_SYS_IMMR \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500602 | BATL_PP_RW \
Joe Hershberger5afe9722011-10-11 23:57:19 -0500603 | BATL_CACHEINHIBIT \
604 | BATL_GUARDEDSTORAGE)
605#define CONFIG_SYS_IBAT2U (CONFIG_SYS_IMMR \
606 | BATU_BL_8M \
607 | BATU_VS \
608 | BATU_VP)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200609#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
610#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
Kim Phillips5e918a92008-01-16 00:38:05 -0600611
612/* L2 Switch: cache-inhibit and guarded */
Joe Hershberger5afe9722011-10-11 23:57:19 -0500613#define CONFIG_SYS_IBAT3L (CONFIG_SYS_VSC7385_BASE \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500614 | BATL_PP_RW \
Joe Hershberger5afe9722011-10-11 23:57:19 -0500615 | BATL_CACHEINHIBIT \
616 | BATL_GUARDEDSTORAGE)
617#define CONFIG_SYS_IBAT3U (CONFIG_SYS_VSC7385_BASE \
618 | BATU_BL_128K \
619 | BATU_VS \
620 | BATU_VP)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200621#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
622#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
Kim Phillips5e918a92008-01-16 00:38:05 -0600623
624/* FLASH: icache cacheable, but dcache-inhibit and guarded */
Joe Hershberger5afe9722011-10-11 23:57:19 -0500625#define CONFIG_SYS_IBAT4L (CONFIG_SYS_FLASH_BASE \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500626 | BATL_PP_RW \
Joe Hershberger5afe9722011-10-11 23:57:19 -0500627 | BATL_MEMCOHERENCE)
628#define CONFIG_SYS_IBAT4U (CONFIG_SYS_FLASH_BASE \
629 | BATU_BL_32M \
630 | BATU_VS \
631 | BATU_VP)
632#define CONFIG_SYS_DBAT4L (CONFIG_SYS_FLASH_BASE \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500633 | BATL_PP_RW \
Joe Hershberger5afe9722011-10-11 23:57:19 -0500634 | BATL_CACHEINHIBIT \
635 | BATL_GUARDEDSTORAGE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200636#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
Kim Phillips5e918a92008-01-16 00:38:05 -0600637
638/* Stack in dcache: cacheable, no memory coherence */
Joe Hershberger72cd4082011-10-11 23:57:28 -0500639#define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
Joe Hershberger5afe9722011-10-11 23:57:19 -0500640#define CONFIG_SYS_IBAT5U (CONFIG_SYS_INIT_RAM_ADDR \
641 | BATU_BL_128K \
642 | BATU_VS \
643 | BATU_VP)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200644#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
645#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
Kim Phillips5e918a92008-01-16 00:38:05 -0600646
647#ifdef CONFIG_PCI
648/* PCI MEM space: cacheable */
Joe Hershberger5afe9722011-10-11 23:57:19 -0500649#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI_MEM_PHYS \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500650 | BATL_PP_RW \
Joe Hershberger5afe9722011-10-11 23:57:19 -0500651 | BATL_MEMCOHERENCE)
652#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI_MEM_PHYS \
653 | BATU_BL_256M \
654 | BATU_VS \
655 | BATU_VP)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200656#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
657#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
Kim Phillips5e918a92008-01-16 00:38:05 -0600658/* PCI MMIO space: cache-inhibit and guarded */
Joe Hershberger5afe9722011-10-11 23:57:19 -0500659#define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI_MMIO_PHYS \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500660 | BATL_PP_RW \
Joe Hershberger5afe9722011-10-11 23:57:19 -0500661 | BATL_CACHEINHIBIT \
662 | BATL_GUARDEDSTORAGE)
663#define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI_MMIO_PHYS \
664 | BATU_BL_256M \
665 | BATU_VS \
666 | BATU_VP)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200667#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
668#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
Kim Phillips5e918a92008-01-16 00:38:05 -0600669#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200670#define CONFIG_SYS_IBAT6L (0)
671#define CONFIG_SYS_IBAT6U (0)
672#define CONFIG_SYS_IBAT7L (0)
673#define CONFIG_SYS_IBAT7U (0)
674#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
675#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
676#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
677#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
Kim Phillips5e918a92008-01-16 00:38:05 -0600678#endif
679
Kim Phillips5e918a92008-01-16 00:38:05 -0600680#if defined(CONFIG_CMD_KGDB)
681#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
Kim Phillips5e918a92008-01-16 00:38:05 -0600682#endif
683
684/*
685 * Environment Configuration
686 */
687#define CONFIG_ENV_OVERWRITE
688
Anton Vorontsov18e69a32008-03-14 23:20:18 +0300689#define CONFIG_HAS_FSL_DR_USB
Nikhil Badola6c3c5752014-10-20 16:31:01 +0530690#define CONFIG_CMD_USB
691#define CONFIG_USB_STORAGE
692#define CONFIG_USB_EHCI
693#define CONFIG_USB_EHCI_FSL
694#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
Anton Vorontsov18e69a32008-03-14 23:20:18 +0300695
Joe Hershberger5afe9722011-10-11 23:57:19 -0500696#define CONFIG_NETDEV "eth1"
Kim Phillips5e918a92008-01-16 00:38:05 -0600697
698#define CONFIG_HOSTNAME mpc837x_rdb
Joe Hershberger8b3637c2011-10-13 13:03:47 +0000699#define CONFIG_ROOTPATH "/nfsroot"
Joe Hershberger5afe9722011-10-11 23:57:19 -0500700#define CONFIG_RAMDISKFILE "rootfs.ext2.gz.uboot"
Joe Hershbergerb3f44c22011-10-13 13:03:48 +0000701#define CONFIG_BOOTFILE "uImage"
Joe Hershberger5afe9722011-10-11 23:57:19 -0500702 /* U-Boot image on TFTP server */
703#define CONFIG_UBOOTPATH "u-boot.bin"
704#define CONFIG_FDTFILE "mpc8379_rdb.dtb"
Kim Phillips5e918a92008-01-16 00:38:05 -0600705
Joe Hershberger5afe9722011-10-11 23:57:19 -0500706 /* default location for tftp and bootm */
707#define CONFIG_LOADADDR 800000
Kim Phillips7fd0bea2008-09-24 08:46:25 -0500708#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
Kim Phillips5e918a92008-01-16 00:38:05 -0600709#define CONFIG_BAUDRATE 115200
710
Kim Phillips5e918a92008-01-16 00:38:05 -0600711#define CONFIG_EXTRA_ENV_SETTINGS \
Joe Hershberger5afe9722011-10-11 23:57:19 -0500712 "netdev=" CONFIG_NETDEV "\0" \
713 "uboot=" CONFIG_UBOOTPATH "\0" \
Kim Phillips5e918a92008-01-16 00:38:05 -0600714 "tftpflash=tftp $loadaddr $uboot;" \
Marek Vasut5368c552012-09-23 17:41:24 +0200715 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
716 " +$filesize; " \
717 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
718 " +$filesize; " \
719 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
720 " $filesize; " \
721 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
722 " +$filesize; " \
723 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
724 " $filesize\0" \
Kim Phillips79f516b2009-08-21 16:34:38 -0500725 "fdtaddr=780000\0" \
Joe Hershberger5afe9722011-10-11 23:57:19 -0500726 "fdtfile=" CONFIG_FDTFILE "\0" \
Kim Phillips5e918a92008-01-16 00:38:05 -0600727 "ramdiskaddr=1000000\0" \
Joe Hershberger5afe9722011-10-11 23:57:19 -0500728 "ramdiskfile=" CONFIG_RAMDISKFILE "\0" \
Kim Phillips5e918a92008-01-16 00:38:05 -0600729 "console=ttyS0\0" \
730 "setbootargs=setenv bootargs " \
731 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
732 "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \
Joe Hershberger5afe9722011-10-11 23:57:19 -0500733 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
734 "$netdev:off " \
Kim Phillips5e918a92008-01-16 00:38:05 -0600735 "root=$rootdev rw console=$console,$baudrate $othbootargs\0"
736
737#define CONFIG_NFSBOOTCOMMAND \
738 "setenv rootdev /dev/nfs;" \
739 "run setbootargs;" \
740 "run setipargs;" \
741 "tftp $loadaddr $bootfile;" \
742 "tftp $fdtaddr $fdtfile;" \
743 "bootm $loadaddr - $fdtaddr"
744
745#define CONFIG_RAMBOOTCOMMAND \
746 "setenv rootdev /dev/ram;" \
747 "run setbootargs;" \
748 "tftp $ramdiskaddr $ramdiskfile;" \
749 "tftp $loadaddr $bootfile;" \
750 "tftp $fdtaddr $fdtfile;" \
751 "bootm $loadaddr $ramdiskaddr $fdtaddr"
752
Kim Phillips5e918a92008-01-16 00:38:05 -0600753#endif /* __CONFIG_H */