blob: cdea4a854656aeabf1c70e6cf67306d66b86942d [file] [log] [blame]
Heiko Schocherf7264c32011-11-29 02:33:47 +00001/*
2 * (C) Copyright 2011
3 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
4 *
5 * Based on:
6 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
7 *
8 * Based on davinci_dvevm.h. Original Copyrights follow:
9 *
10 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
11 *
Wolfgang Denk1a459662013-07-08 09:37:19 +020012 * SPDX-License-Identifier: GPL-2.0+
Heiko Schocherf7264c32011-11-29 02:33:47 +000013 */
14
15#ifndef __CONFIG_H
16#define __CONFIG_H
17
18/*
19 * Board
20 */
21#define CONFIG_DRIVER_TI_EMAC
22#define CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT 7
23#define CONFIG_USE_NAND
24
25/*
26 * SoC Configuration
27 */
Heiko Schocherf7264c32011-11-29 02:33:47 +000028#define CONFIG_SOC_DA8XX /* TI DA8xx SoC */
29#define CONFIG_SOC_DA850 /* TI DA850 SoC */
Christian Rieschb67d8812012-02-02 00:44:39 +000030#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
Heiko Schocherf7264c32011-11-29 02:33:47 +000031#define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID)
32#define CONFIG_SYS_OSCIN_FREQ 24000000
33#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
34#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
Heiko Schocherf7264c32011-11-29 02:33:47 +000035#define CONFIG_DA850_LOWLEVEL
36#define CONFIG_ARCH_CPU_INIT
Sughosh Ganu6b873dc2012-02-02 00:44:41 +000037#define CONFIG_SYS_DA850_PLL_INIT
38#define CONFIG_SYS_DA850_DDR_INIT
Heiko Schocherf7264c32011-11-29 02:33:47 +000039#define CONFIG_DA8XX_GPIO
40#define CONFIG_HOSTNAME enbw_cmc
Heiko Schocherf7264c32011-11-29 02:33:47 +000041
42#define MACH_TYPE_ENBW_CMC 3585
43#define CONFIG_MACH_TYPE MACH_TYPE_ENBW_CMC
44
45/*
46 * Memory Info
47 */
48#define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */
49#define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
50#define PHYS_SDRAM_1_SIZE (64 << 20) /* SDRAM size 64MB */
51#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
52
53/* memtest start addr */
54#define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000)
55
56/* memtest will be run on 16MB */
57#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 0x2000000 + 16*1024*1024)
58
59#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
Heiko Schocherf7264c32011-11-29 02:33:47 +000060
61/*
62 * Serial Driver info
63 */
64#define CONFIG_SYS_NS16550
65#define CONFIG_SYS_NS16550_SERIAL
66#define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */
67#define CONFIG_SYS_NS16550_COM1 DAVINCI_UART2_BASE /* Base address of UART2 */
68#define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID)
69#define CONFIG_CONS_INDEX 1 /* use UART0 for console */
70#define CONFIG_BAUDRATE 115200 /* Default baud rate */
Sughosh Ganu6b873dc2012-02-02 00:44:41 +000071
Heiko Schocherf7264c32011-11-29 02:33:47 +000072/*
73 * I2C Configuration
74 */
Vitaly Andrianove8459dc2014-04-04 13:16:52 -040075#define CONFIG_SYS_I2C
76#define CONFIG_SYS_I2C_DAVINCI
77#define CONFIG_SYS_DAVINCI_I2C_SPEED 80000
78#define CONFIG_SYS_DAVINCI_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */
Heiko Schocherf7264c32011-11-29 02:33:47 +000079#define CONFIG_SYS_I2C_EXPANDER_ADDR 0x20
80#define CONFIG_CMD_I2C
81
82#define CONFIG_CMD_DTT
83#define CONFIG_DTT_LM75
84#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
85#define CONFIG_SYS_DTT_MAX_TEMP 70
86#define CONFIG_SYS_DTT_LOW_TEMP -30
87#define CONFIG_SYS_DTT_HYSTERESIS 3
88
89/*
Heiko Schocher14b9f162012-05-14 20:24:14 +000090 * SPI Configuration
91 */
92#define CONFIG_DAVINCI_SPI
93#define CONFIG_SYS_SPI_BASE DAVINCI_SPI1_BASE
94#define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID)
95#define CONFIG_CMD_SPI
96
97/*
Heiko Schocherf7264c32011-11-29 02:33:47 +000098 * Flash & Environment
99 */
100#ifdef CONFIG_USE_NAND
101#define CONFIG_NAND_DAVINCI
102#define CONFIG_SYS_NAND_USE_FLASH_BBT
103#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
104#define CONFIG_SYS_NAND_PAGE_2K
105#define CONFIG_SYS_NAND_CS 3
106#define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
Eric Benard34fa0702013-04-22 05:55:00 +0000107#define CONFIG_SYS_NAND_MASK_CLE 0x10
108#define CONFIG_SYS_NAND_MASK_ALE 0x8
Heiko Schocherf7264c32011-11-29 02:33:47 +0000109#undef CONFIG_SYS_NAND_HW_ECC
110#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
Heiko Schocherf7264c32011-11-29 02:33:47 +0000111
112#define MTDIDS_DEFAULT "nor0=physmap-flash.0,nand0=davinci_nand.1"
113#define MTDPARTS_DEFAULT \
114 "mtdparts=" \
115 "physmap-flash.0:" \
116 "512k(U-Boot)," \
117 "64k(env1)," \
118 "64k(env2)," \
119 "-(rest);" \
120 "davinci_nand.1:" \
121 "128k(dtb)," \
122 "3m(kernel)," \
123 "4m(rootfs)," \
124 "-(userfs)"
125
126
127#define CONFIG_CMD_MTDPARTS
128
129#endif
130
131/*
132 * Network & Ethernet Configuration
133 */
134#ifdef CONFIG_DRIVER_TI_EMAC
135#define CONFIG_MII
Heiko Schocherf7264c32011-11-29 02:33:47 +0000136#define CONFIG_BOOTP_DNS
137#define CONFIG_BOOTP_DNS2
138#define CONFIG_BOOTP_SEND_HOSTNAME
139#define CONFIG_NET_RETRY_COUNT 10
Heiko Schocherf7264c32011-11-29 02:33:47 +0000140#endif
141
142/*
143 * Flash configuration
144 */
145#define CONFIG_SYS_FLASH_CFI
146#define CONFIG_FLASH_CFI_DRIVER
147#define CONFIG_FLASH_CFI_MTD
148#define CONFIG_SYS_FLASH_BASE 0x60000000
149#define CONFIG_SYS_FLASH_SIZE 0x01000000
150#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
151#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
152#define CONFIG_SYS_MAX_FLASH_SECT 128
153#define CONFIG_FLASH_16BIT /* Flash is 16-bit */
154
155#define CONFIG_CMD_FLASH
156
157#define CONFIG_ENV_IS_IN_FLASH
158#define CONFIG_SYS_MONITOR_LEN 0x80000
159#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + \
160 CONFIG_SYS_MONITOR_LEN)
161#define CONFIG_ENV_SECT_SIZE (64 << 10)
162#define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */
163#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + \
164 CONFIG_ENV_SECT_SIZE)
165#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
166#undef CONFIG_ENV_IS_IN_NAND
167#define CONFIG_DEFAULT_SETTINGS_ADDR (CONFIG_ENV_ADDR_REDUND + \
168 CONFIG_ENV_SECT_SIZE)
169
Heiko Schocherf7264c32011-11-29 02:33:47 +0000170#define CONFIG_EXTRA_ENV_SETTINGS \
171 "u-boot_addr_r=c0000000\0" \
Marek Vasut93ea89f2012-09-23 17:41:23 +0200172 "u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.bin\0" \
Heiko Schocherf7264c32011-11-29 02:33:47 +0000173 "load=tftp ${u-boot_addr_r} ${u-boot}\0" \
Marek Vasut93ea89f2012-09-23 17:41:23 +0200174 "update=protect off " __stringify(CONFIG_SYS_FLASH_BASE) " +${filesize};"\
175 "erase " __stringify(CONFIG_SYS_FLASH_BASE) " +${filesize};" \
176 "cp.b ${u-boot_addr_r} " __stringify(CONFIG_SYS_FLASH_BASE) \
Heiko Schocherf7264c32011-11-29 02:33:47 +0000177 " ${filesize};" \
Marek Vasut93ea89f2012-09-23 17:41:23 +0200178 "protect on " __stringify(CONFIG_SYS_FLASH_BASE) " +${filesize}\0"\
Heiko Schocherf7264c32011-11-29 02:33:47 +0000179 "netdev=eth0\0" \
180 "rootpath=/opt/eldk-arm/arm\0" \
181 "nfsargs=setenv bootargs root=/dev/nfs rw " \
182 "nfsroot=${serverip}:${rootpath}\0" \
183 "ramargs=setenv bootargs root=/dev/ram rw\0" \
184 "addip=setenv bootargs ${bootargs} " \
185 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
186 ":${hostname}:${netdev}:off panic=1\0" \
187 "kernel_addr_r=c0700000\0" \
188 "fdt_addr_r=c0600000\0" \
189 "ramdisk_addr_r=c0b00000\0" \
Marek Vasut93ea89f2012-09-23 17:41:23 +0200190 "fdt_file=" __stringify(CONFIG_HOSTNAME) "/" \
191 __stringify(CONFIG_HOSTNAME) ".dtb\0" \
192 "kernel_file=" __stringify(CONFIG_HOSTNAME) "/uImage \0" \
Heiko Schocherf7264c32011-11-29 02:33:47 +0000193 "nand_ld_ramdsk=nand read ${ramdisk_addr_r} 320000 400000\0" \
194 "nand_ld_kernel=nand read ${kernel_addr_r} 20000 300000\0" \
195 "nand_ld_fdt=nand read ${fdt_addr_r} 0 2000\0" \
196 "load_kernel=tftp ${kernel_addr_r} ${kernel_file}\0" \
197 "load_fdt=tftp ${fdt_addr_r} ${fdt_file}\0" \
198 "load_nand=run nand_ld_ramdsk nand_ld_kernel nand_ld_fdt\0" \
199 "addcon=setenv bootargs ${bootargs} console=ttyS2," \
200 "${baudrate}n8\0" \
201 "net_nfs=run load_fdt load_kernel; " \
202 "run nfsargs addip addcon addmtd addmisc;" \
203 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
204 "nand_selfnand=run load_nand ramargs addip addcon addmisc;bootm "\
205 "${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0" \
206 "bootcmd=run net_nfs\0" \
207 "machid=e01\0" \
208 "key_cmd_0=echo key: 0\0" \
209 "key_cmd_1=echo key: 1\0" \
210 "key_cmd_2=echo key: 2\0" \
211 "key_cmd_3=echo key: 3\0" \
212 "key_magic_0=0\0" \
213 "key_magic_1=1\0" \
214 "key_magic_2=2\0" \
215 "key_magic_3=3\0" \
216 "magic_keys=0123\0" \
Heiko Schocher14b9f162012-05-14 20:24:14 +0000217 "hwconfig=switch:lan=on,pwl=off,config=0x60100000\0" \
Heiko Schocherf7264c32011-11-29 02:33:47 +0000218 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
Heiko Schocher14b9f162012-05-14 20:24:14 +0000219 "addmisc=setenv bootargs ${bootargs}\0" \
Heiko Schocherf7264c32011-11-29 02:33:47 +0000220 "mtdids=" MTDIDS_DEFAULT "\0" \
221 "mtdparts=" MTDPARTS_DEFAULT "\0" \
222 "logversion=2\0" \
223 "\0"
224
225/*
226 * U-Boot general configuration
227 */
228#define CONFIG_BOOTFILE "uImage" /* Boot file name */
Heiko Schocherf7264c32011-11-29 02:33:47 +0000229#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
230#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
231#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
232#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
233#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000)
234#define CONFIG_VERSION_VARIABLE
235#define CONFIG_AUTO_COMPLETE
236#define CONFIG_SYS_HUSH_PARSER
Heiko Schocherf7264c32011-11-29 02:33:47 +0000237#define CONFIG_CMDLINE_EDITING
238#define CONFIG_SYS_LONGHELP
239#define CONFIG_CRC32_VERIFY
240#define CONFIG_MX_CYCLIC
241#define CONFIG_BOOTDELAY 3
242#define CONFIG_HWCONFIG
243#define CONFIG_SHOW_BOOT_PROGRESS
244#define CONFIG_BOARD_LATE_INIT
245
246/*
247 * U-Boot commands
248 */
249#include <config_cmd_default.h>
250#define CONFIG_CMD_ENV
251#define CONFIG_CMD_ASKENV
252#define CONFIG_CMD_DHCP
253#define CONFIG_CMD_DIAG
254#define CONFIG_CMD_MII
255#define CONFIG_CMD_PING
256#define CONFIG_CMD_SAVES
257#define CONFIG_CMD_MEMORY
258#define CONFIG_CMD_CACHE
259
Hadli, Manjunath8f5d4682012-02-06 00:30:44 +0000260#ifdef CONFIG_CMD_BDI
261#define CONFIG_CLOCKS
262#endif
263
Heiko Schocherf7264c32011-11-29 02:33:47 +0000264#ifndef CONFIG_DRIVER_TI_EMAC
265#undef CONFIG_CMD_NET
266#undef CONFIG_CMD_DHCP
267#undef CONFIG_CMD_MII
268#undef CONFIG_CMD_PING
269#endif
270
271#ifdef CONFIG_USE_NAND
272#undef CONFIG_CMD_IMLS
273#define CONFIG_CMD_NAND
274
275#define CONFIG_CMD_MTDPARTS
276#define CONFIG_MTD_DEVICE
277#define CONFIG_MTD_PARTITIONS
278#define CONFIG_LZO
279#define CONFIG_RBTREE
280#define CONFIG_CMD_UBI
281#define CONFIG_CMD_UBIFS
282#endif
283
284#if !defined(CONFIG_USE_NAND) && \
285 !defined(CONFIG_USE_NOR) && \
286 !defined(CONFIG_USE_SPIFLASH)
287#define CONFIG_ENV_IS_NOWHERE
288#define CONFIG_SYS_NO_FLASH
289#define CONFIG_ENV_SIZE (16 << 10)
290#undef CONFIG_CMD_IMLS
291#undef CONFIG_CMD_ENV
292#endif
293
294#define CONFIG_SYS_TEXT_BASE 0x60000000
295#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
296#define CONFIG_SYS_SDRAM_BASE 0xc0000000
297#define CONFIG_SYS_INIT_SP_ADDR (0x8001ff00)
298
299#define CONFIG_VERSION_VARIABLE
300#define CONFIG_ENV_OVERWRITE
301
302#define CONFIG_PREBOOT "echo;" \
303 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
304 "echo"
305#define CONFIG_MISC_INIT_R
306
307#define CONFIG_CMC_RESET_PIN 0x04000000
308#define CONFIG_CMC_RESET_TIMEOUT 3
309
310#define CONFIG_HW_WATCHDOG
311#define CONFIG_SYS_WDTTIMERBASE DAVINCI_TIMER1_BASE
312#define CONFIG_SYS_WDT_PERIOD_LOW 0x0c000000
313#define CONFIG_SYS_WDT_PERIOD_HIGH 0x0
314
315#define CONFIG_CMD_DATE
316#define CONFIG_RTC_DAVINCI
317
318/* SD/MMC */
319#define CONFIG_MMC
320#define CONFIG_GENERIC_MMC
321#define CONFIG_DAVINCI_MMC
322#define CONFIG_MMC_MBLOCK
323#define CONFIG_DOS_PARTITION
324#define CONFIG_CMD_FAT
325#define CONFIG_CMD_MMC
326
Heiko Schocher14b9f162012-05-14 20:24:14 +0000327/* GPIO */
328#define CONFIG_ENBW_CMC_BOARD_TYPE 57
329#define CONFIG_ENBW_CMC_HW_ID_BIT0 39
330#define CONFIG_ENBW_CMC_HW_ID_BIT1 38
331#define CONFIG_ENBW_CMC_HW_ID_BIT2 35
Heiko Schocherf7264c32011-11-29 02:33:47 +0000332
333/* FDT support */
334#define CONFIG_OF_LIBFDT
335
336/* LowLevel Init */
337/* PLL */
338#define CONFIG_SYS_DV_CLKMODE 0
339#define CONFIG_SYS_DA850_PLL0_POSTDIV 0
340#define CONFIG_SYS_DA850_PLL0_PLLDIV1 0x8000
341#define CONFIG_SYS_DA850_PLL0_PLLDIV2 0x8001
342#define CONFIG_SYS_DA850_PLL0_PLLDIV3 0x8002 /* 150MHz */
343#define CONFIG_SYS_DA850_PLL0_PLLDIV4 0x8003
344#define CONFIG_SYS_DA850_PLL0_PLLDIV5 0x8002
345#define CONFIG_SYS_DA850_PLL0_PLLDIV6 CONFIG_SYS_DA850_PLL0_PLLDIV1
346#define CONFIG_SYS_DA850_PLL0_PLLDIV7 0x8005
347
348#define CONFIG_SYS_DA850_PLL1_POSTDIV 1
349#define CONFIG_SYS_DA850_PLL1_PLLDIV1 0x8000
350#define CONFIG_SYS_DA850_PLL1_PLLDIV2 0x8001
351#define CONFIG_SYS_DA850_PLL1_PLLDIV3 0x8002
352
353#define CONFIG_SYS_DA850_PLL0_PLLM 18 /* PLL0 -> 456 MHz */
354#define CONFIG_SYS_DA850_PLL1_PLLM 24 /* PLL1 -> 300 MHz */
355
356/* DDR RAM */
357#define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \
358 DV_DDR_PHY_EXT_STRBEN | \
359 (0x4 << DV_DDR_PHY_RD_LATENCY_SHIFT))
360
361#define CONFIG_SYS_DA850_DDR2_SDBCR (0 | \
362 (0 << DV_DDR_SDCR_DDR2TERM1_SHIFT) | \
363 (0 << DV_DDR_SDCR_MSDRAMEN_SHIFT) | \
364 (1 << DV_DDR_SDCR_DDR2EN_SHIFT) | \
365 (0x1 << DV_DDR_SDCR_DDREN_SHIFT) | \
366 (0x1 << DV_DDR_SDCR_SDRAMEN_SHIFT) | \
367 (0x1 << DV_DDR_SDCR_TIMUNLOCK_SHIFT) | \
368 (0x1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) | \
369 (0x3 << DV_DDR_SDCR_CL_SHIFT) | \
370 (0x2 << DV_DDR_SDCR_IBANK_SHIFT) | \
371 (0x2 << DV_DDR_SDCR_PAGESIZE_SHIFT))
372
373#define CONFIG_SYS_DA850_DDR2_SDBCR2 4 /* 13 row address bits */
374
375/*
376 * freq = 150MHz -> t = 7ns
377 */
378#define CONFIG_SYS_DA850_DDR2_SDTIMR (0 | \
379 (0x0d << DV_DDR_SDTMR1_RFC_SHIFT) | \
380 (1 << DV_DDR_SDTMR1_RP_SHIFT) | \
381 (1 << DV_DDR_SDTMR1_RCD_SHIFT) | \
382 (1 << DV_DDR_SDTMR1_WR_SHIFT) | \
383 (5 << DV_DDR_SDTMR1_RAS_SHIFT) | \
384 (7 << DV_DDR_SDTMR1_RC_SHIFT) | \
385 (1 << DV_DDR_SDTMR1_RRD_SHIFT) | \
386 (readl(&dv_ddr2_regs_ctrl->sdtimr) & 0x4) | /* Reserved */ \
387 ((2 - 1) << DV_DDR_SDTMR1_WTR_SHIFT))
388
389/*
390 * freq = 150MHz -> t=7ns
391 */
392#define CONFIG_SYS_DA850_DDR2_SDTIMR2 (0 | \
393 (readl(&dv_ddr2_regs_ctrl->sdtimr2) & 0x80000000) | /* Reserved */ \
394 (8 << DV_DDR_SDTMR2_RASMAX_SHIFT) | \
395 (2 << DV_DDR_SDTMR2_XP_SHIFT) | \
396 (0 << DV_DDR_SDTMR2_ODT_SHIFT) | \
397 (15 << DV_DDR_SDTMR2_XSNR_SHIFT) | \
398 (27 << DV_DDR_SDTMR2_XSRD_SHIFT) | \
399 (0 << DV_DDR_SDTMR2_RTP_SHIFT) | \
400 (2 << DV_DDR_SDTMR2_CKE_SHIFT))
401
402#define CONFIG_SYS_DA850_DDR2_SDRCR 0x00000407
403#define CONFIG_SYS_DA850_DDR2_PBBPR 0x30
404#define CONFIG_SYS_DA850_SYSCFG_SUSPSRC (DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \
405 DAVINCI_SYSCFG_SUSPSRC_SPI1 | \
406 DAVINCI_SYSCFG_SUSPSRC_UART2 | \
407 DAVINCI_SYSCFG_SUSPSRC_EMAC |\
408 DAVINCI_SYSCFG_SUSPSRC_I2C)
409
410#define CONFIG_SYS_DA850_CS2CFG (DAVINCI_ABCR_WSETUP(2) | \
411 DAVINCI_ABCR_WSTROBE(6) | \
412 DAVINCI_ABCR_WHOLD(1) | \
413 DAVINCI_ABCR_RSETUP(2) | \
414 DAVINCI_ABCR_RSTROBE(6) | \
415 DAVINCI_ABCR_RHOLD(1) | \
416 DAVINCI_ABCR_ASIZE_16BIT)
417
418#define CONFIG_SYS_DA850_CS3CFG (DAVINCI_ABCR_WSETUP(1) | \
419 DAVINCI_ABCR_WSTROBE(2) | \
420 DAVINCI_ABCR_WHOLD(1) | \
421 DAVINCI_ABCR_RSETUP(1) | \
422 DAVINCI_ABCR_RSTROBE(6) | \
423 DAVINCI_ABCR_RHOLD(1) | \
424 DAVINCI_ABCR_ASIZE_8BIT)
425
426/*
427 * NOR Bootconfiguration word:
428 * Method: Direc boot
429 * EMIFA access mode: 16 Bit
430 */
431#define CONFIG_SYS_DV_NOR_BOOT_CFG (0x11)
432
433#define CONFIG_POST (CONFIG_SYS_POST_MEMORY)
Heiko Schocher14b9f162012-05-14 20:24:14 +0000434#define CONFIG_POST_EXTERNAL_WORD_FUNCS
435#define CONFIG_SYS_POST_WORD_ADDR DAVINCI_RTC_BASE
Heiko Schocherf7264c32011-11-29 02:33:47 +0000436#define CONFIG_LOGBUFFER
437#define CONFIG_SYS_CONSOLE_IS_IN_ENV
438
439#define CONFIG_BOOTCOUNT_LIMIT
440#define CONFIG_SYS_BOOTCOUNT_ADDR DAVINCI_RTC_BASE
Stefan Roese0044c422012-08-16 17:55:41 +0000441#define CONFIG_SYS_BOOTCOUNT_BE
Heiko Schocherf7264c32011-11-29 02:33:47 +0000442
443#define CONFIG_SYS_NAND_U_BOOT_DST 0xc0080000
444#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x60004000
445#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x70000
446#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
447#endif /* __CONFIG_H */