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Julien May5c374c92008-06-23 13:57:52 +02001/*
2 * Copyright (C) 2008 Miromico AG
3 *
4 * Configuration settings for the Miromico Hammerhead AVR32 board
5 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02006 * SPDX-License-Identifier: GPL-2.0+
Julien May5c374c92008-06-23 13:57:52 +02007 */
8#ifndef __CONFIG_H
9#define __CONFIG_H
10
Andreas Bießmannbf018332011-04-18 04:12:41 +000011#define CONFIG_AT32AP
12#define CONFIG_AT32AP7000
13#define CONFIG_HAMMERHEAD
Julien May5c374c92008-06-23 13:57:52 +020014
Julien May5c374c92008-06-23 13:57:52 +020015/*
16 * Set up the PLL to run at 125 MHz, the CPU to run at the PLL
17 * frequency, the HSB and PBB busses to run at 1/2 the PLL frequency
18 * and the PBA bus to run at 1/4 the PLL frequency.
19 */
Andreas Bießmannbf018332011-04-18 04:12:41 +000020#define CONFIG_PLL
21#define CONFIG_SYS_POWER_MANAGER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020022#define CONFIG_SYS_OSC0_HZ 25000000
23#define CONFIG_SYS_PLL0_DIV 1
24#define CONFIG_SYS_PLL0_MUL 5
25#define CONFIG_SYS_PLL0_SUPPRESS_CYCLES 16
26#define CONFIG_SYS_CLKDIV_CPU 0
27#define CONFIG_SYS_CLKDIV_HSB 1
28#define CONFIG_SYS_CLKDIV_PBA 2
29#define CONFIG_SYS_CLKDIV_PBB 1
Julien May5c374c92008-06-23 13:57:52 +020030
Haavard Skinnemoen1f36f732010-08-12 13:52:54 +070031/* Reserve VM regions for SDRAM and NOR flash */
32#define CONFIG_SYS_NR_VM_REGIONS 2
33
Julien May5c374c92008-06-23 13:57:52 +020034/*
35 * The PLLOPT register controls the PLL like this:
36 * icp = PLLOPT<2>
37 * ivco = PLLOPT<1:0>
38 *
39 * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz).
40 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020041#define CONFIG_SYS_PLL0_OPT 0x04
Julien May5c374c92008-06-23 13:57:52 +020042
Andreas Bießmannf4278b72010-11-04 23:15:31 +000043#define CONFIG_USART_BASE ATMEL_BASE_USART1
44#define CONFIG_USART_ID 1
Julien May5c374c92008-06-23 13:57:52 +020045
46#define CONFIG_HOSTNAME hammerhead
47
48/* User serviceable stuff */
Andreas Bießmannbf018332011-04-18 04:12:41 +000049#define CONFIG_DOS_PARTITION
Julien May5c374c92008-06-23 13:57:52 +020050
Andreas Bießmannbf018332011-04-18 04:12:41 +000051#define CONFIG_CMDLINE_TAG
52#define CONFIG_SETUP_MEMORY_TAGS
53#define CONFIG_INITRD_TAG
Julien May5c374c92008-06-23 13:57:52 +020054
55#define CONFIG_STACKSIZE (2048)
56
57#define CONFIG_BAUDRATE 115200
58#define CONFIG_BOOTARGS \
59 "console=ttyS0 root=mtd1 rootfstype=jffs2"
60#define CONFIG_BOOTCOMMAND \
61 "fsload; bootm"
62
63/*
64 * Only interrupt autoboot if <space> is pressed. Otherwise, garbage
65 * data on the serial line may interrupt the boot sequence.
66 */
67#define CONFIG_BOOTDELAY 1
Andreas Bießmannbf018332011-04-18 04:12:41 +000068#define CONFIG_AUTOBOOT
69#define CONFIG_AUTOBOOT_KEYED
Julien May5c374c92008-06-23 13:57:52 +020070#define CONFIG_AUTOBOOT_PROMPT \
Haavard Skinnemoen33eac2b2008-08-20 09:28:36 +020071 "Press SPACE to abort autoboot in %d seconds\n", bootdelay
Julien May5c374c92008-06-23 13:57:52 +020072#define CONFIG_AUTOBOOT_DELAY_STR "d"
73#define CONFIG_AUTOBOOT_STOP_STR " "
74
75/*
76 * After booting the board for the first time, new ethernet address
77 * should be generated and assigned to the environment variables
78 * "ethaddr". This is normally done during production.
79 */
Andreas Bießmannbf018332011-04-18 04:12:41 +000080#define CONFIG_OVERWRITE_ETHADDR_ONCE
Julien May5c374c92008-06-23 13:57:52 +020081
82/*
83 * BOOTP/DHCP options
84 */
85#define CONFIG_BOOTP_SUBNETMASK
86#define CONFIG_BOOTP_GATEWAY
87
88/*
89 * Command line configuration.
90 */
91#include <config_cmd_default.h>
92
93#define CONFIG_CMD_ASKENV
94#define CONFIG_CMD_DHCP
95#define CONFIG_CMD_EXT2
96#define CONFIG_CMD_FAT
97#define CONFIG_CMD_JFFS2
98#define CONFIG_CMD_MMC
99#undef CONFIG_CMD_FPGA
100#undef CONFIG_CMD_SETGETDCR
101
Andreas Bießmannbf018332011-04-18 04:12:41 +0000102#define CONFIG_ATMEL_USART
103#define CONFIG_MACB
104#define CONFIG_PORTMUX_PIO
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200105#define CONFIG_SYS_NR_PIOS 5
Andreas Bießmannbf018332011-04-18 04:12:41 +0000106#define CONFIG_SYS_HSDRAMC
107#define CONFIG_MMC
Sven Schnelle72fa4672011-10-21 14:49:25 +0200108#define CONFIG_GENERIC_ATMEL_MCI
109#define CONFIG_GENERIC_MMC
Julien May5c374c92008-06-23 13:57:52 +0200110
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200111#define CONFIG_SYS_DCACHE_LINESZ 32
112#define CONFIG_SYS_ICACHE_LINESZ 32
Julien May5c374c92008-06-23 13:57:52 +0200113
114#define CONFIG_NR_DRAM_BANKS 1
115
Andreas Bießmannbf018332011-04-18 04:12:41 +0000116#define CONFIG_SYS_FLASH_CFI
117#define CONFIG_FLASH_CFI_DRIVER
Julien May5c374c92008-06-23 13:57:52 +0200118
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200119#define CONFIG_SYS_FLASH_BASE 0x00000000
120#define CONFIG_SYS_FLASH_SIZE 0x800000
121#define CONFIG_SYS_MAX_FLASH_BANKS 1
122#define CONFIG_SYS_MAX_FLASH_SECT 135
Julien May5c374c92008-06-23 13:57:52 +0200123
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200124#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
Andreas Bießmann15cc55a2011-04-18 04:12:47 +0000125#define CONFIG_SYS_TEXT_BASE 0x00000000
Julien May5c374c92008-06-23 13:57:52 +0200126
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200127#define CONFIG_SYS_INTRAM_BASE 0x24000000
128#define CONFIG_SYS_INTRAM_SIZE 0x8000
Julien May5c374c92008-06-23 13:57:52 +0200129
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200130#define CONFIG_SYS_SDRAM_BASE 0x10000000
Julien May5c374c92008-06-23 13:57:52 +0200131
Andreas Bießmannbf018332011-04-18 04:12:41 +0000132#define CONFIG_ENV_IS_IN_FLASH
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200133#define CONFIG_ENV_SIZE 65536
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200134#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - CONFIG_ENV_SIZE)
Julien May5c374c92008-06-23 13:57:52 +0200135
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200136#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INTRAM_BASE + CONFIG_SYS_INTRAM_SIZE)
Julien May5c374c92008-06-23 13:57:52 +0200137
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200138#define CONFIG_SYS_MALLOC_LEN (256*1024)
Julien May5c374c92008-06-23 13:57:52 +0200139
Julien May5c374c92008-06-23 13:57:52 +0200140
141/* Allow 4MB for the kernel run-time image */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200142#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x00400000)
143#define CONFIG_SYS_BOOTPARAMS_LEN (16 * 1024)
Julien May5c374c92008-06-23 13:57:52 +0200144
145/* Other configuration settings that shouldn't have to change all that often */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200146#define CONFIG_SYS_PROMPT "Hammerhead> "
147#define CONFIG_SYS_CBSIZE 256
148#define CONFIG_SYS_MAXARGS 16
149#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
Andreas Bießmannbf018332011-04-18 04:12:41 +0000150#define CONFIG_SYS_LONGHELP
Julien May5c374c92008-06-23 13:57:52 +0200151
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200152#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
153#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x1f00000)
Julien May5c374c92008-06-23 13:57:52 +0200154
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200155#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 }
Julien May5c374c92008-06-23 13:57:52 +0200156
157#endif /* __CONFIG_H */