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Andy Fleming67431052007-04-23 02:54:25 -05001/*
Kumar Gala6525d512010-07-08 22:37:44 -05002 * Copyright 2007,2009-2010 Freescale Semiconductor, Inc.
Andy Fleming67431052007-04-23 02:54:25 -05003 *
4 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25#include <common.h>
26#include <pci.h>
27#include <asm/processor.h>
Jon Loeligere6f5b352008-03-18 13:51:05 -050028#include <asm/mmu.h>
Andy Fleming67431052007-04-23 02:54:25 -050029#include <asm/immap_85xx.h>
Kumar Galac8514622009-04-02 13:22:48 -050030#include <asm/fsl_pci.h>
Jon Loeligere6f5b352008-03-18 13:51:05 -050031#include <asm/fsl_ddr_sdram.h>
Jon Loeligera30a5492008-03-04 10:03:03 -060032#include <spd_sdram.h>
Haiying Wangc59e4092007-06-19 14:18:34 -040033#include <i2c.h>
Andy Flemingda9d4612007-08-14 00:14:25 -050034#include <ioports.h>
Kumar Galac4808612007-11-29 01:06:19 -060035#include <libfdt.h>
36#include <fdt_support.h>
Haiying Wang1563f562007-11-14 15:52:06 -050037
Andy Fleming67431052007-04-23 02:54:25 -050038#include "bcsr.h"
39
Andy Flemingda9d4612007-08-14 00:14:25 -050040const qe_iop_conf_t qe_iop_conf_tab[] = {
41 /* GETH1 */
42 {4, 10, 1, 0, 2}, /* TxD0 */
43 {4, 9, 1, 0, 2}, /* TxD1 */
44 {4, 8, 1, 0, 2}, /* TxD2 */
45 {4, 7, 1, 0, 2}, /* TxD3 */
46 {4, 23, 1, 0, 2}, /* TxD4 */
47 {4, 22, 1, 0, 2}, /* TxD5 */
48 {4, 21, 1, 0, 2}, /* TxD6 */
49 {4, 20, 1, 0, 2}, /* TxD7 */
50 {4, 15, 2, 0, 2}, /* RxD0 */
51 {4, 14, 2, 0, 2}, /* RxD1 */
52 {4, 13, 2, 0, 2}, /* RxD2 */
53 {4, 12, 2, 0, 2}, /* RxD3 */
54 {4, 29, 2, 0, 2}, /* RxD4 */
55 {4, 28, 2, 0, 2}, /* RxD5 */
56 {4, 27, 2, 0, 2}, /* RxD6 */
57 {4, 26, 2, 0, 2}, /* RxD7 */
58 {4, 11, 1, 0, 2}, /* TX_EN */
59 {4, 24, 1, 0, 2}, /* TX_ER */
60 {4, 16, 2, 0, 2}, /* RX_DV */
61 {4, 30, 2, 0, 2}, /* RX_ER */
62 {4, 17, 2, 0, 2}, /* RX_CLK */
63 {4, 19, 1, 0, 2}, /* GTX_CLK */
64 {1, 31, 2, 0, 3}, /* GTX125 */
65
66 /* GETH2 */
67 {5, 10, 1, 0, 2}, /* TxD0 */
68 {5, 9, 1, 0, 2}, /* TxD1 */
69 {5, 8, 1, 0, 2}, /* TxD2 */
70 {5, 7, 1, 0, 2}, /* TxD3 */
71 {5, 23, 1, 0, 2}, /* TxD4 */
72 {5, 22, 1, 0, 2}, /* TxD5 */
73 {5, 21, 1, 0, 2}, /* TxD6 */
74 {5, 20, 1, 0, 2}, /* TxD7 */
75 {5, 15, 2, 0, 2}, /* RxD0 */
76 {5, 14, 2, 0, 2}, /* RxD1 */
77 {5, 13, 2, 0, 2}, /* RxD2 */
78 {5, 12, 2, 0, 2}, /* RxD3 */
79 {5, 29, 2, 0, 2}, /* RxD4 */
80 {5, 28, 2, 0, 2}, /* RxD5 */
81 {5, 27, 2, 0, 3}, /* RxD6 */
82 {5, 26, 2, 0, 2}, /* RxD7 */
83 {5, 11, 1, 0, 2}, /* TX_EN */
84 {5, 24, 1, 0, 2}, /* TX_ER */
85 {5, 16, 2, 0, 2}, /* RX_DV */
86 {5, 30, 2, 0, 2}, /* RX_ER */
87 {5, 17, 2, 0, 2}, /* RX_CLK */
88 {5, 19, 1, 0, 2}, /* GTX_CLK */
89 {1, 31, 2, 0, 3}, /* GTX125 */
90 {4, 6, 3, 0, 2}, /* MDIO */
91 {4, 5, 1, 0, 2}, /* MDC */
Anton Vorontsov64d4bcb2007-10-22 19:58:19 +040092
93 /* UART1 */
94 {2, 0, 1, 0, 2}, /* UART_SOUT1 */
95 {2, 1, 1, 0, 2}, /* UART_RTS1 */
96 {2, 2, 2, 0, 2}, /* UART_CTS1 */
97 {2, 3, 2, 0, 2}, /* UART_SIN1 */
98
Andy Flemingda9d4612007-08-14 00:14:25 -050099 {0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */
100};
101
Andy Fleming67431052007-04-23 02:54:25 -0500102void local_bus_init(void);
103void sdram_init(void);
104
105int board_early_init_f (void)
106{
107 /*
108 * Initialize local bus.
109 */
110 local_bus_init ();
111
112 enable_8568mds_duart();
113 enable_8568mds_flash_write();
Anton Vorontsovad162242007-10-22 18:12:46 +0400114#if defined(CONFIG_UEC_ETH1) || defined(CONFIG_UEC_ETH2)
115 reset_8568mds_uccs();
116#endif
Andy Flemingda9d4612007-08-14 00:14:25 -0500117#if defined(CONFIG_QE) && !defined(CONFIG_eTSEC_MDIO_BUS)
118 enable_8568mds_qe_mdio();
119#endif
Andy Fleming67431052007-04-23 02:54:25 -0500120
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200121#ifdef CONFIG_SYS_I2C2_OFFSET
Haiying Wangc59e4092007-06-19 14:18:34 -0400122 /* Enable I2C2_SCL and I2C2_SDA */
123 volatile struct par_io *port_c;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200124 port_c = (struct par_io*)(CONFIG_SYS_IMMR + 0xe0140);
Haiying Wangc59e4092007-06-19 14:18:34 -0400125 port_c->cpdir2 |= 0x0f000000;
126 port_c->cppar2 &= ~0x0f000000;
127 port_c->cppar2 |= 0x0a000000;
128#endif
129
Andy Fleming67431052007-04-23 02:54:25 -0500130 return 0;
131}
132
133int checkboard (void)
134{
135 printf ("Board: 8568 MDS\n");
136
137 return 0;
138}
139
Becky Bruce9973e3c2008-06-09 16:03:40 -0500140phys_size_t
Andy Fleming67431052007-04-23 02:54:25 -0500141initdram(int board_type)
142{
143 long dram_size = 0;
Andy Fleming67431052007-04-23 02:54:25 -0500144
145 puts("Initializing\n");
146
147#if defined(CONFIG_DDR_DLL)
148 {
149 /*
150 * Work around to stabilize DDR DLL MSYNC_IN.
151 * Errata DDR9 seems to have been fixed.
152 * This is now the workaround for Errata DDR11:
153 * Override DLL = 1, Course Adj = 1, Tap Select = 0
154 */
155
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200156 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
Andy Fleming67431052007-04-23 02:54:25 -0500157
158 gur->ddrdllcr = 0x81000000;
159 asm("sync;isync;msync");
160 udelay(200);
161 }
162#endif
Jon Loeligere6f5b352008-03-18 13:51:05 -0500163
164 dram_size = fsl_ddr_sdram();
165 dram_size = setup_ddr_tlbs(dram_size / 0x100000);
166 dram_size *= 0x100000;
Andy Fleming67431052007-04-23 02:54:25 -0500167
Andy Fleming67431052007-04-23 02:54:25 -0500168 /*
169 * SDRAM Initialization
170 */
171 sdram_init();
172
173 puts(" DDR: ");
174 return dram_size;
175}
176
177/*
178 * Initialize Local Bus
179 */
180void
181local_bus_init(void)
182{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200183 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
Becky Brucef51cdaf2010-06-17 11:37:20 -0500184 volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
Andy Fleming67431052007-04-23 02:54:25 -0500185
186 uint clkdiv;
187 uint lbc_hz;
188 sys_info_t sysinfo;
189
190 get_sys_info(&sysinfo);
Trent Piephoa5d212a2008-12-03 15:16:34 -0800191 clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2;
Andy Fleming67431052007-04-23 02:54:25 -0500192 lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
193
194 gur->lbiuiplldcr1 = 0x00078080;
195 if (clkdiv == 16) {
196 gur->lbiuiplldcr0 = 0x7c0f1bf0;
197 } else if (clkdiv == 8) {
198 gur->lbiuiplldcr0 = 0x6c0f1bf0;
199 } else if (clkdiv == 4) {
200 gur->lbiuiplldcr0 = 0x5c0f1bf0;
201 }
202
203 lbc->lcrr |= 0x00030000;
204
205 asm("sync;isync;msync");
206}
207
208/*
209 * Initialize SDRAM memory on the Local Bus.
210 */
211void
212sdram_init(void)
213{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200214#if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
Andy Fleming67431052007-04-23 02:54:25 -0500215
216 uint idx;
Becky Brucef51cdaf2010-06-17 11:37:20 -0500217 volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200218 uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
Andy Fleming67431052007-04-23 02:54:25 -0500219 uint lsdmr_common;
220
221 puts(" SDRAM: ");
222
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200223 print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
Andy Fleming67431052007-04-23 02:54:25 -0500224
225 /*
226 * Setup SDRAM Base and Option Registers
227 */
Becky Brucef51cdaf2010-06-17 11:37:20 -0500228 set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
229 set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
Andy Fleming67431052007-04-23 02:54:25 -0500230 asm("msync");
231
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200232 lbc->lbcr = CONFIG_SYS_LBC_LBCR;
Andy Fleming67431052007-04-23 02:54:25 -0500233 asm("msync");
234
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200235 lbc->lsrt = CONFIG_SYS_LBC_LSRT;
236 lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
Andy Fleming67431052007-04-23 02:54:25 -0500237 asm("msync");
238
239 /*
240 * MPC8568 uses "new" 15-16 style addressing.
241 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200242 lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON;
Kumar Galab0fe93ed2009-03-26 01:34:38 -0500243 lsdmr_common |= LSDMR_BSMA1516;
Andy Fleming67431052007-04-23 02:54:25 -0500244
245 /*
246 * Issue PRECHARGE ALL command.
247 */
Kumar Galab0fe93ed2009-03-26 01:34:38 -0500248 lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL;
Andy Fleming67431052007-04-23 02:54:25 -0500249 asm("sync;msync");
250 *sdram_addr = 0xff;
251 ppcDcbf((unsigned long) sdram_addr);
252 udelay(100);
253
254 /*
255 * Issue 8 AUTO REFRESH commands.
256 */
257 for (idx = 0; idx < 8; idx++) {
Kumar Galab0fe93ed2009-03-26 01:34:38 -0500258 lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH;
Andy Fleming67431052007-04-23 02:54:25 -0500259 asm("sync;msync");
260 *sdram_addr = 0xff;
261 ppcDcbf((unsigned long) sdram_addr);
262 udelay(100);
263 }
264
265 /*
266 * Issue 8 MODE-set command.
267 */
Kumar Galab0fe93ed2009-03-26 01:34:38 -0500268 lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW;
Andy Fleming67431052007-04-23 02:54:25 -0500269 asm("sync;msync");
270 *sdram_addr = 0xff;
271 ppcDcbf((unsigned long) sdram_addr);
272 udelay(100);
273
274 /*
275 * Issue NORMAL OP command.
276 */
Kumar Galab0fe93ed2009-03-26 01:34:38 -0500277 lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
Andy Fleming67431052007-04-23 02:54:25 -0500278 asm("sync;msync");
279 *sdram_addr = 0xff;
280 ppcDcbf((unsigned long) sdram_addr);
281 udelay(200); /* Overkill. Must wait > 200 bus cycles */
282
283#endif /* enable SDRAM init */
284}
285
Andy Fleming67431052007-04-23 02:54:25 -0500286#if defined(CONFIG_PCI)
287#ifndef CONFIG_PCI_PNP
288static struct pci_config_table pci_mpc8568mds_config_table[] = {
289 {
290 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
291 pci_cfgfunc_config_device,
292 {PCI_ENET0_IOADDR,
293 PCI_ENET0_MEMADDR,
294 PCI_COMMON_MEMORY | PCI_COMMAND_MASTER}
295 },
296 {}
297};
298#endif
299
Haiying Wang1563f562007-11-14 15:52:06 -0500300static struct pci_controller pci1_hose = {
Andy Fleming67431052007-04-23 02:54:25 -0500301#ifndef CONFIG_PCI_PNP
Haiying Wangc59e4092007-06-19 14:18:34 -0400302 config_table: pci_mpc8568mds_config_table,
Andy Fleming67431052007-04-23 02:54:25 -0500303#endif
Andy Fleming67431052007-04-23 02:54:25 -0500304};
Andy Fleming67431052007-04-23 02:54:25 -0500305#endif /* CONFIG_PCI */
306
Haiying Wang1563f562007-11-14 15:52:06 -0500307#ifdef CONFIG_PCIE1
308static struct pci_controller pcie1_hose;
309#endif /* CONFIG_PCIE1 */
310
Haiying Wangc59e4092007-06-19 14:18:34 -0400311/*
312 * pib_init() -- Initialize the PCA9555 IO expander on the PIB board
313 */
314void
315pib_init(void)
316{
317 u8 val8, orig_i2c_bus;
318 /*
319 * Assign PIB PMC2/3 to PCI bus
320 */
321
322 /*switch temporarily to I2C bus #2 */
323 orig_i2c_bus = i2c_get_bus_num();
324 i2c_set_bus_num(1);
325
326 val8 = 0x00;
327 i2c_write(0x23, 0x6, 1, &val8, 1);
328 i2c_write(0x23, 0x7, 1, &val8, 1);
329 val8 = 0xff;
330 i2c_write(0x23, 0x2, 1, &val8, 1);
331 i2c_write(0x23, 0x3, 1, &val8, 1);
332
333 val8 = 0x00;
334 i2c_write(0x26, 0x6, 1, &val8, 1);
335 val8 = 0x34;
336 i2c_write(0x26, 0x7, 1, &val8, 1);
337 val8 = 0xf9;
338 i2c_write(0x26, 0x2, 1, &val8, 1);
339 val8 = 0xff;
340 i2c_write(0x26, 0x3, 1, &val8, 1);
341
342 val8 = 0x00;
343 i2c_write(0x27, 0x6, 1, &val8, 1);
344 i2c_write(0x27, 0x7, 1, &val8, 1);
345 val8 = 0xff;
346 i2c_write(0x27, 0x2, 1, &val8, 1);
347 val8 = 0xef;
348 i2c_write(0x27, 0x3, 1, &val8, 1);
349
350 asm("eieio");
351}
352
Haiying Wang1563f562007-11-14 15:52:06 -0500353#ifdef CONFIG_PCI
Kumar Gala46814572009-11-04 10:31:53 -0600354void pci_init_board(void)
Andy Fleming67431052007-04-23 02:54:25 -0500355{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200356 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
Kumar Gala46814572009-11-04 10:31:53 -0600357 struct fsl_pci_info pci_info[2];
358 u32 devdisr, pordevsr, io_sel;
359 u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel;
360 int first_free_busno = 0;
361 int num = 0;
362
363 int pcie_ep, pcie_configured;
364
365 devdisr = in_be32(&gur->devdisr);
366 pordevsr = in_be32(&gur->pordevsr);
367 porpllsr = in_be32(&gur->porpllsr);
368 io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
369
370 debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel);
Haiying Wang1563f562007-11-14 15:52:06 -0500371
372#ifdef CONFIG_PCI1
Kumar Gala46814572009-11-04 10:31:53 -0600373 pci_speed = 66666000;
374 pci_32 = 1;
375 pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
376 pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
Haiying Wang1563f562007-11-14 15:52:06 -0500377
Kumar Gala46814572009-11-04 10:31:53 -0600378 if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
379 SET_STD_PCI_INFO(pci_info[num], 1);
380 pci_agent = fsl_setup_hose(&pci1_hose, pci_info[num].regs);
Peter Tyser8ca78f22010-10-29 17:59:24 -0500381 printf("PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
Haiying Wang1563f562007-11-14 15:52:06 -0500382 (pci_32) ? 32 : 64,
383 (pci_speed == 33333000) ? "33" :
384 (pci_speed == 66666000) ? "66" : "unknown",
385 pci_clk_sel ? "sync" : "async",
386 pci_agent ? "agent" : "host",
Kumar Gala46814572009-11-04 10:31:53 -0600387 pci_arb ? "arbiter" : "external-arbiter",
388 pci_info[num].regs);
Haiying Wang1563f562007-11-14 15:52:06 -0500389
Kumar Gala46814572009-11-04 10:31:53 -0600390 first_free_busno = fsl_pci_init_port(&pci_info[num++],
391 &pci1_hose, first_free_busno);
Haiying Wang1563f562007-11-14 15:52:06 -0500392 } else {
Peter Tyser8ca78f22010-10-29 17:59:24 -0500393 printf("PCI: disabled\n");
Haiying Wang1563f562007-11-14 15:52:06 -0500394 }
Kumar Gala46814572009-11-04 10:31:53 -0600395
396 puts("\n");
Haiying Wang1563f562007-11-14 15:52:06 -0500397#else
Kumar Gala46814572009-11-04 10:31:53 -0600398 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */
Haiying Wang1563f562007-11-14 15:52:06 -0500399#endif
400
401#ifdef CONFIG_PCIE1
Kumar Gala46814572009-11-04 10:31:53 -0600402 pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);
Haiying Wang1563f562007-11-14 15:52:06 -0500403
Kumar Gala46814572009-11-04 10:31:53 -0600404 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
405 SET_STD_PCIE_INFO(pci_info[num], 1);
406 pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
Peter Tyser8ca78f22010-10-29 17:59:24 -0500407 printf("PCIE1: connected to Slot as %s (base addr %lx)\n",
Peter Tyser64917ca2010-01-17 15:38:26 -0600408 pcie_ep ? "Endpoint" : "Root Complex",
Kumar Gala46814572009-11-04 10:31:53 -0600409 pci_info[num].regs);
Haiying Wang1563f562007-11-14 15:52:06 -0500410
Kumar Gala46814572009-11-04 10:31:53 -0600411 first_free_busno = fsl_pci_init_port(&pci_info[num++],
412 &pcie1_hose, first_free_busno);
Haiying Wang1563f562007-11-14 15:52:06 -0500413 } else {
Peter Tyser8ca78f22010-10-29 17:59:24 -0500414 printf("PCIE1: disabled\n");
Haiying Wang1563f562007-11-14 15:52:06 -0500415 }
Kumar Gala46814572009-11-04 10:31:53 -0600416
417 puts("\n");
Haiying Wang1563f562007-11-14 15:52:06 -0500418#else
Kumar Gala46814572009-11-04 10:31:53 -0600419 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */
Andy Fleming67431052007-04-23 02:54:25 -0500420#endif
421}
Haiying Wang1563f562007-11-14 15:52:06 -0500422#endif /* CONFIG_PCI */
423
Kumar Galac4808612007-11-29 01:06:19 -0600424#if defined(CONFIG_OF_BOARD_SETUP)
Kumar Gala2dba0de2008-10-21 08:28:33 -0500425void ft_board_setup(void *blob, bd_t *bd)
426{
Haiying Wang1563f562007-11-14 15:52:06 -0500427 ft_cpu_setup(blob, bd);
Haiying Wang1563f562007-11-14 15:52:06 -0500428
Kumar Gala6525d512010-07-08 22:37:44 -0500429 FT_FSL_PCI_SETUP;
Haiying Wang1563f562007-11-14 15:52:06 -0500430}
431#endif