Andy Fleming | 6743105 | 2007-04-23 02:54:25 -0500 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2007 Freescale Semiconductor. |
| 3 | * |
| 4 | * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com> |
| 5 | * |
| 6 | * See file CREDITS for list of people who contributed to this |
| 7 | * project. |
| 8 | * |
| 9 | * This program is free software; you can redistribute it and/or |
| 10 | * modify it under the terms of the GNU General Public License as |
| 11 | * published by the Free Software Foundation; either version 2 of |
| 12 | * the License, or (at your option) any later version. |
| 13 | * |
| 14 | * This program is distributed in the hope that it will be useful, |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | * GNU General Public License for more details. |
| 18 | * |
| 19 | * You should have received a copy of the GNU General Public License |
| 20 | * along with this program; if not, write to the Free Software |
| 21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 22 | * MA 02111-1307 USA |
| 23 | */ |
| 24 | |
| 25 | #include <common.h> |
| 26 | #include <pci.h> |
| 27 | #include <asm/processor.h> |
| 28 | #include <asm/immap_85xx.h> |
| 29 | #include <spd.h> |
Haiying Wang | c59e409 | 2007-06-19 14:18:34 -0400 | [diff] [blame^] | 30 | #include <i2c.h> |
Andy Fleming | 6743105 | 2007-04-23 02:54:25 -0500 | [diff] [blame] | 31 | |
| 32 | #include "bcsr.h" |
| 33 | |
| 34 | |
| 35 | #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) |
| 36 | extern void ddr_enable_ecc(unsigned int dram_size); |
| 37 | #endif |
| 38 | |
| 39 | extern long int spd_sdram(void); |
| 40 | |
| 41 | void local_bus_init(void); |
| 42 | void sdram_init(void); |
| 43 | |
| 44 | int board_early_init_f (void) |
| 45 | { |
| 46 | /* |
| 47 | * Initialize local bus. |
| 48 | */ |
| 49 | local_bus_init (); |
| 50 | |
| 51 | enable_8568mds_duart(); |
| 52 | enable_8568mds_flash_write(); |
| 53 | |
Haiying Wang | c59e409 | 2007-06-19 14:18:34 -0400 | [diff] [blame^] | 54 | #ifdef CFG_I2C2_OFFSET |
| 55 | /* Enable I2C2_SCL and I2C2_SDA */ |
| 56 | volatile struct par_io *port_c; |
| 57 | port_c = (struct par_io*)(CFG_IMMR + 0xe0140); |
| 58 | port_c->cpdir2 |= 0x0f000000; |
| 59 | port_c->cppar2 &= ~0x0f000000; |
| 60 | port_c->cppar2 |= 0x0a000000; |
| 61 | #endif |
| 62 | |
Andy Fleming | 6743105 | 2007-04-23 02:54:25 -0500 | [diff] [blame] | 63 | return 0; |
| 64 | } |
| 65 | |
| 66 | int checkboard (void) |
| 67 | { |
| 68 | printf ("Board: 8568 MDS\n"); |
| 69 | |
| 70 | return 0; |
| 71 | } |
| 72 | |
| 73 | long int |
| 74 | initdram(int board_type) |
| 75 | { |
| 76 | long dram_size = 0; |
| 77 | volatile immap_t *immap = (immap_t *)CFG_IMMR; |
| 78 | |
| 79 | puts("Initializing\n"); |
| 80 | |
| 81 | #if defined(CONFIG_DDR_DLL) |
| 82 | { |
| 83 | /* |
| 84 | * Work around to stabilize DDR DLL MSYNC_IN. |
| 85 | * Errata DDR9 seems to have been fixed. |
| 86 | * This is now the workaround for Errata DDR11: |
| 87 | * Override DLL = 1, Course Adj = 1, Tap Select = 0 |
| 88 | */ |
| 89 | |
| 90 | volatile ccsr_gur_t *gur= &immap->im_gur; |
| 91 | |
| 92 | gur->ddrdllcr = 0x81000000; |
| 93 | asm("sync;isync;msync"); |
| 94 | udelay(200); |
| 95 | } |
| 96 | #endif |
| 97 | dram_size = spd_sdram(); |
| 98 | |
| 99 | #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) |
| 100 | /* |
| 101 | * Initialize and enable DDR ECC. |
| 102 | */ |
| 103 | ddr_enable_ecc(dram_size); |
| 104 | #endif |
| 105 | /* |
| 106 | * SDRAM Initialization |
| 107 | */ |
| 108 | sdram_init(); |
| 109 | |
| 110 | puts(" DDR: "); |
| 111 | return dram_size; |
| 112 | } |
| 113 | |
| 114 | /* |
| 115 | * Initialize Local Bus |
| 116 | */ |
| 117 | void |
| 118 | local_bus_init(void) |
| 119 | { |
| 120 | volatile immap_t *immap = (immap_t *)CFG_IMMR; |
| 121 | volatile ccsr_gur_t *gur = &immap->im_gur; |
| 122 | volatile ccsr_lbc_t *lbc = &immap->im_lbc; |
| 123 | |
| 124 | uint clkdiv; |
| 125 | uint lbc_hz; |
| 126 | sys_info_t sysinfo; |
| 127 | |
| 128 | get_sys_info(&sysinfo); |
| 129 | clkdiv = (lbc->lcrr & 0x0f) * 2; |
| 130 | lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; |
| 131 | |
| 132 | gur->lbiuiplldcr1 = 0x00078080; |
| 133 | if (clkdiv == 16) { |
| 134 | gur->lbiuiplldcr0 = 0x7c0f1bf0; |
| 135 | } else if (clkdiv == 8) { |
| 136 | gur->lbiuiplldcr0 = 0x6c0f1bf0; |
| 137 | } else if (clkdiv == 4) { |
| 138 | gur->lbiuiplldcr0 = 0x5c0f1bf0; |
| 139 | } |
| 140 | |
| 141 | lbc->lcrr |= 0x00030000; |
| 142 | |
| 143 | asm("sync;isync;msync"); |
| 144 | } |
| 145 | |
| 146 | /* |
| 147 | * Initialize SDRAM memory on the Local Bus. |
| 148 | */ |
| 149 | void |
| 150 | sdram_init(void) |
| 151 | { |
| 152 | #if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM) |
| 153 | |
| 154 | uint idx; |
| 155 | volatile immap_t *immap = (immap_t *)CFG_IMMR; |
| 156 | volatile ccsr_lbc_t *lbc = &immap->im_lbc; |
| 157 | uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE; |
| 158 | uint lsdmr_common; |
| 159 | |
| 160 | puts(" SDRAM: "); |
| 161 | |
| 162 | print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n"); |
| 163 | |
| 164 | /* |
| 165 | * Setup SDRAM Base and Option Registers |
| 166 | */ |
| 167 | lbc->or2 = CFG_OR2_PRELIM; |
| 168 | asm("msync"); |
| 169 | |
| 170 | lbc->br2 = CFG_BR2_PRELIM; |
| 171 | asm("msync"); |
| 172 | |
| 173 | lbc->lbcr = CFG_LBC_LBCR; |
| 174 | asm("msync"); |
| 175 | |
| 176 | |
| 177 | lbc->lsrt = CFG_LBC_LSRT; |
| 178 | lbc->mrtpr = CFG_LBC_MRTPR; |
| 179 | asm("msync"); |
| 180 | |
| 181 | /* |
| 182 | * MPC8568 uses "new" 15-16 style addressing. |
| 183 | */ |
| 184 | lsdmr_common = CFG_LBC_LSDMR_COMMON; |
| 185 | lsdmr_common |= CFG_LBC_LSDMR_BSMA1516; |
| 186 | |
| 187 | /* |
| 188 | * Issue PRECHARGE ALL command. |
| 189 | */ |
| 190 | lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_PCHALL; |
| 191 | asm("sync;msync"); |
| 192 | *sdram_addr = 0xff; |
| 193 | ppcDcbf((unsigned long) sdram_addr); |
| 194 | udelay(100); |
| 195 | |
| 196 | /* |
| 197 | * Issue 8 AUTO REFRESH commands. |
| 198 | */ |
| 199 | for (idx = 0; idx < 8; idx++) { |
| 200 | lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_ARFRSH; |
| 201 | asm("sync;msync"); |
| 202 | *sdram_addr = 0xff; |
| 203 | ppcDcbf((unsigned long) sdram_addr); |
| 204 | udelay(100); |
| 205 | } |
| 206 | |
| 207 | /* |
| 208 | * Issue 8 MODE-set command. |
| 209 | */ |
| 210 | lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_MRW; |
| 211 | asm("sync;msync"); |
| 212 | *sdram_addr = 0xff; |
| 213 | ppcDcbf((unsigned long) sdram_addr); |
| 214 | udelay(100); |
| 215 | |
| 216 | /* |
| 217 | * Issue NORMAL OP command. |
| 218 | */ |
| 219 | lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_NORMAL; |
| 220 | asm("sync;msync"); |
| 221 | *sdram_addr = 0xff; |
| 222 | ppcDcbf((unsigned long) sdram_addr); |
| 223 | udelay(200); /* Overkill. Must wait > 200 bus cycles */ |
| 224 | |
| 225 | #endif /* enable SDRAM init */ |
| 226 | } |
| 227 | |
| 228 | #if defined(CFG_DRAM_TEST) |
| 229 | int |
| 230 | testdram(void) |
| 231 | { |
| 232 | uint *pstart = (uint *) CFG_MEMTEST_START; |
| 233 | uint *pend = (uint *) CFG_MEMTEST_END; |
| 234 | uint *p; |
| 235 | |
| 236 | printf("Testing DRAM from 0x%08x to 0x%08x\n", |
| 237 | CFG_MEMTEST_START, |
| 238 | CFG_MEMTEST_END); |
| 239 | |
| 240 | printf("DRAM test phase 1:\n"); |
| 241 | for (p = pstart; p < pend; p++) |
| 242 | *p = 0xaaaaaaaa; |
| 243 | |
| 244 | for (p = pstart; p < pend; p++) { |
| 245 | if (*p != 0xaaaaaaaa) { |
| 246 | printf ("DRAM test fails at: %08x\n", (uint) p); |
| 247 | return 1; |
| 248 | } |
| 249 | } |
| 250 | |
| 251 | printf("DRAM test phase 2:\n"); |
| 252 | for (p = pstart; p < pend; p++) |
| 253 | *p = 0x55555555; |
| 254 | |
| 255 | for (p = pstart; p < pend; p++) { |
| 256 | if (*p != 0x55555555) { |
| 257 | printf ("DRAM test fails at: %08x\n", (uint) p); |
| 258 | return 1; |
| 259 | } |
| 260 | } |
| 261 | |
| 262 | printf("DRAM test passed.\n"); |
| 263 | return 0; |
| 264 | } |
| 265 | #endif |
| 266 | |
| 267 | #if defined(CONFIG_PCI) |
| 268 | #ifndef CONFIG_PCI_PNP |
| 269 | static struct pci_config_table pci_mpc8568mds_config_table[] = { |
| 270 | { |
| 271 | PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, |
| 272 | pci_cfgfunc_config_device, |
| 273 | {PCI_ENET0_IOADDR, |
| 274 | PCI_ENET0_MEMADDR, |
| 275 | PCI_COMMON_MEMORY | PCI_COMMAND_MASTER} |
| 276 | }, |
| 277 | {} |
| 278 | }; |
| 279 | #endif |
| 280 | |
| 281 | static struct pci_controller hose[] = { |
Haiying Wang | c59e409 | 2007-06-19 14:18:34 -0400 | [diff] [blame^] | 282 | { |
Andy Fleming | 6743105 | 2007-04-23 02:54:25 -0500 | [diff] [blame] | 283 | #ifndef CONFIG_PCI_PNP |
Haiying Wang | c59e409 | 2007-06-19 14:18:34 -0400 | [diff] [blame^] | 284 | config_table: pci_mpc8568mds_config_table, |
Andy Fleming | 6743105 | 2007-04-23 02:54:25 -0500 | [diff] [blame] | 285 | #endif |
Haiying Wang | c59e409 | 2007-06-19 14:18:34 -0400 | [diff] [blame^] | 286 | } |
Andy Fleming | 6743105 | 2007-04-23 02:54:25 -0500 | [diff] [blame] | 287 | }; |
| 288 | |
| 289 | #endif /* CONFIG_PCI */ |
| 290 | |
Haiying Wang | c59e409 | 2007-06-19 14:18:34 -0400 | [diff] [blame^] | 291 | /* |
| 292 | * pib_init() -- Initialize the PCA9555 IO expander on the PIB board |
| 293 | */ |
| 294 | void |
| 295 | pib_init(void) |
| 296 | { |
| 297 | u8 val8, orig_i2c_bus; |
| 298 | /* |
| 299 | * Assign PIB PMC2/3 to PCI bus |
| 300 | */ |
| 301 | |
| 302 | /*switch temporarily to I2C bus #2 */ |
| 303 | orig_i2c_bus = i2c_get_bus_num(); |
| 304 | i2c_set_bus_num(1); |
| 305 | |
| 306 | val8 = 0x00; |
| 307 | i2c_write(0x23, 0x6, 1, &val8, 1); |
| 308 | i2c_write(0x23, 0x7, 1, &val8, 1); |
| 309 | val8 = 0xff; |
| 310 | i2c_write(0x23, 0x2, 1, &val8, 1); |
| 311 | i2c_write(0x23, 0x3, 1, &val8, 1); |
| 312 | |
| 313 | val8 = 0x00; |
| 314 | i2c_write(0x26, 0x6, 1, &val8, 1); |
| 315 | val8 = 0x34; |
| 316 | i2c_write(0x26, 0x7, 1, &val8, 1); |
| 317 | val8 = 0xf9; |
| 318 | i2c_write(0x26, 0x2, 1, &val8, 1); |
| 319 | val8 = 0xff; |
| 320 | i2c_write(0x26, 0x3, 1, &val8, 1); |
| 321 | |
| 322 | val8 = 0x00; |
| 323 | i2c_write(0x27, 0x6, 1, &val8, 1); |
| 324 | i2c_write(0x27, 0x7, 1, &val8, 1); |
| 325 | val8 = 0xff; |
| 326 | i2c_write(0x27, 0x2, 1, &val8, 1); |
| 327 | val8 = 0xef; |
| 328 | i2c_write(0x27, 0x3, 1, &val8, 1); |
| 329 | |
| 330 | asm("eieio"); |
| 331 | } |
| 332 | |
Andy Fleming | 6743105 | 2007-04-23 02:54:25 -0500 | [diff] [blame] | 333 | void |
| 334 | pci_init_board(void) |
| 335 | { |
| 336 | #ifdef CONFIG_PCI |
Haiying Wang | c59e409 | 2007-06-19 14:18:34 -0400 | [diff] [blame^] | 337 | pib_init(); |
Andy Fleming | 6743105 | 2007-04-23 02:54:25 -0500 | [diff] [blame] | 338 | pci_mpc85xx_init(&hose); |
| 339 | #endif |
| 340 | } |