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wdenka562e1b2005-01-09 18:21:42 +00001/*
2 * Configuation settings for the Sentec Cobra Board.
3 *
4 * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
5 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02006 * SPDX-License-Identifier: GPL-2.0+
wdenka562e1b2005-01-09 18:21:42 +00007 */
8
9/* ---
Bin Menga1875592016-02-05 19:30:11 -080010 * Version: U-Boot 1.0.0 - initial release for Sentec COBRA5272 board
wdenka562e1b2005-01-09 18:21:42 +000011 * Date: 2004-03-29
12 * Author: Florian Schlote
13 *
14 * For a description of configuration options please refer also to the
15 * general u-boot-1.x.x/README file
16 * ---
17 */
18
19/* ---
20 * board/config.h - configuration options, board specific
21 * ---
22 */
23
24#ifndef _CONFIG_COBRA5272_H
25#define _CONFIG_COBRA5272_H
26
27/* ---
wdenka562e1b2005-01-09 18:21:42 +000028 * Defines processor clock - important for correct timings concerning serial
29 * interface etc.
wdenka562e1b2005-01-09 18:21:42 +000030 * ---
31 */
32
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020033#define CONFIG_SYS_CLK 66000000
34#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
wdenka562e1b2005-01-09 18:21:42 +000035
36/* ---
37 * Enable use of Ethernet
38 * ---
39 */
TsiChungLiew67064242007-08-15 19:41:06 -050040#define CONFIG_MCFFEC
wdenka562e1b2005-01-09 18:21:42 +000041
TsiChungLiew67064242007-08-15 19:41:06 -050042/* Enable Dma Timer */
43#define CONFIG_MCFTMR
wdenka562e1b2005-01-09 18:21:42 +000044
45/* ---
46 * Define baudrate for UART1 (console output, tftp, ...)
47 * default value of CONFIG_BAUDRATE for Sentec board: 19200 baud
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020048 * CONFIG_SYS_BAUDRATE_TABLE defines values that can be selected in u-boot command
wdenka562e1b2005-01-09 18:21:42 +000049 * interface
50 * ---
51 */
52
TsiChungLiew67064242007-08-15 19:41:06 -050053#define CONFIG_MCFUART
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020054#define CONFIG_SYS_UART_PORT (0)
wdenka562e1b2005-01-09 18:21:42 +000055#define CONFIG_BAUDRATE 19200
wdenka562e1b2005-01-09 18:21:42 +000056
57/* ---
58 * set "#if 0" to "#if 1" if (Hardware)-WATCHDOG should be enabled & change
59 * timeout acc. to your needs
60 * #define CONFIG_WATCHDOG_TIMEOUT x , x is timeout in milliseconds, e. g. 10000
61 * for 10 sec
62 * ---
63 */
64
65#if 0
66#define CONFIG_WATCHDOG
67#define CONFIG_WATCHDOG_TIMEOUT 10000 /* timeout in milliseconds */
68#endif
69
70/* ---
71 * CONFIG_MONITOR_IS_IN_RAM defines if u-boot is started from a different
72 * bootloader residing in flash ('chainloading'); if you want to use
73 * chainloading or want to compile a u-boot binary that can be loaded into
74 * RAM via BDM set
Wolfgang Denk53677ef2008-05-20 16:00:29 +020075 * "#if 0" to "#if 1"
wdenka562e1b2005-01-09 18:21:42 +000076 * You will need a first stage bootloader then, e. g. colilo or a working BDM
77 * cable (Background Debug Mode)
78 *
79 * Setting #if 0: u-boot will start from flash and relocate itself to RAM
80 *
Wolfgang Denk14d0a022010-10-07 21:51:12 +020081 * Please do not forget to modify the setting of CONFIG_SYS_TEXT_BASE
wdenka562e1b2005-01-09 18:21:42 +000082 * in board/cobra5272/config.mk accordingly (#if 0: 0xffe00000; #if 1: 0x20000)
83 *
84 * ---
85 */
86
87#if 0
88#define CONFIG_MONITOR_IS_IN_RAM /* monitor is started from a preloader */
89#endif
90
91/* ---
92 * Configuration for environment
93 * Environment is embedded in u-boot in the second sector of the flash
94 * ---
95 */
96
97#ifndef CONFIG_MONITOR_IS_IN_RAM
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +020098#define CONFIG_ENV_OFFSET 0x4000
99#define CONFIG_ENV_SECT_SIZE 0x2000
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200100#define CONFIG_ENV_IS_IN_FLASH 1
wdenka562e1b2005-01-09 18:21:42 +0000101#else
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200102#define CONFIG_ENV_ADDR 0xffe04000
103#define CONFIG_ENV_SECT_SIZE 0x2000
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200104#define CONFIG_ENV_IS_IN_FLASH 1
wdenka562e1b2005-01-09 18:21:42 +0000105#endif
106
angelo@sysam.it5296cb12015-03-29 22:54:16 +0200107#define LDS_BOARD_TEXT \
108 . = DEFINED(env_offset) ? env_offset : .; \
109 common/env_embedded.o (.text);
Jon Loeliger37e4f242007-07-04 22:31:56 -0500110
111/*
Jon Loeliger80ff4f92007-07-10 09:29:01 -0500112 * BOOTP options
113 */
114#define CONFIG_BOOTP_BOOTFILESIZE
115#define CONFIG_BOOTP_BOOTPATH
116#define CONFIG_BOOTP_GATEWAY
117#define CONFIG_BOOTP_HOSTNAME
118
Jon Loeliger80ff4f92007-07-10 09:29:01 -0500119/*
Jon Loeliger37e4f242007-07-04 22:31:56 -0500120 * Command line configuration.
wdenka562e1b2005-01-09 18:21:42 +0000121 */
wdenka562e1b2005-01-09 18:21:42 +0000122
TsiChungLiew67064242007-08-15 19:41:06 -0500123#ifdef CONFIG_MCFFEC
TsiChungLiew67064242007-08-15 19:41:06 -0500124# define CONFIG_MII 1
TsiChung Liew0f3ba7e2008-03-30 01:22:13 -0500125# define CONFIG_MII_INIT 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200126# define CONFIG_SYS_DISCOVER_PHY
127# define CONFIG_SYS_RX_ETH_BUFFER 8
128# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
TsiChungLiew67064242007-08-15 19:41:06 -0500129
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200130# define CONFIG_SYS_FEC0_PINMUX 0
131# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200132# define MCFFEC_TOUT_LOOP 50000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200133/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
134# ifndef CONFIG_SYS_DISCOVER_PHY
TsiChungLiew67064242007-08-15 19:41:06 -0500135# define FECDUPLEX FULL
136# define FECSPEED _100BASET
137# else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200138# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
139# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
TsiChungLiew67064242007-08-15 19:41:06 -0500140# endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200141# endif /* CONFIG_SYS_DISCOVER_PHY */
TsiChungLiew67064242007-08-15 19:41:06 -0500142#endif
wdenka562e1b2005-01-09 18:21:42 +0000143
144/*
145 *-----------------------------------------------------------------------------
146 * Define user parameters that have to be customized most likely
147 *-----------------------------------------------------------------------------
148 */
149
150/*AUTOBOOT settings - booting images automatically by u-boot after power on*/
151
wdenka562e1b2005-01-09 18:21:42 +0000152/* The following settings will be contained in the environment block ; if you
153want to use a neutral environment all those settings can be manually set in
154u-boot: 'set' command */
155
156#if 0
157
158#define CONFIG_BOOTCOMMAND "bootm 0xffe80000" /*Autoboto command, please
159enter a valid image address in flash */
160
161#define CONFIG_BOOTARGS " " /* default bootargs that are
162considered during boot */
163
164/* User network settings */
165
wdenka562e1b2005-01-09 18:21:42 +0000166#define CONFIG_IPADDR 192.168.100.2 /* default board IP address */
167#define CONFIG_SERVERIP 192.168.100.1 /* default tftp server IP address */
168
169#endif
170
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200171#define CONFIG_SYS_LOAD_ADDR 0x20000 /*Defines default RAM address
wdenka562e1b2005-01-09 18:21:42 +0000172from which user programs will be started */
173
174/*---*/
175
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200176#define CONFIG_SYS_LONGHELP /* undef to save memory */
wdenka562e1b2005-01-09 18:21:42 +0000177
Jon Loeliger37e4f242007-07-04 22:31:56 -0500178#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200179#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenka562e1b2005-01-09 18:21:42 +0000180#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200181#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenka562e1b2005-01-09 18:21:42 +0000182#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200183#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
184#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
185#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenka562e1b2005-01-09 18:21:42 +0000186
187/*
188 *-----------------------------------------------------------------------------
189 * End of user parameters to be customized
190 *-----------------------------------------------------------------------------
191 */
192
193/* ---
194 * Defines memory range for test
195 * ---
196 */
197
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200198#define CONFIG_SYS_MEMTEST_START 0x400
199#define CONFIG_SYS_MEMTEST_END 0x380000
wdenka562e1b2005-01-09 18:21:42 +0000200
201/* ---
202 * Low Level Configuration Settings
203 * (address mappings, register initial values, etc.)
204 * You should know what you are doing if you make changes here.
205 * ---
206 */
207
208/* ---
209 * Base register address
210 * ---
211 */
212
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200213#define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */
wdenka562e1b2005-01-09 18:21:42 +0000214
215/* ---
216 * System Conf. Reg. & System Protection Reg.
217 * ---
218 */
219
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200220#define CONFIG_SYS_SCR 0x0003
221#define CONFIG_SYS_SPR 0xffff
wdenka562e1b2005-01-09 18:21:42 +0000222
223/* ---
224 * Ethernet settings
225 * ---
226 */
227
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200228#define CONFIG_SYS_DISCOVER_PHY
229#define CONFIG_SYS_ENET_BD_BASE 0x780000
wdenka562e1b2005-01-09 18:21:42 +0000230
231/*-----------------------------------------------------------------------
232 * Definitions for initial stack pointer and data area (in internal SRAM)
233 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200234#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
Wolfgang Denk553f0982010-10-26 13:32:32 +0200235#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200236#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200237#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenka562e1b2005-01-09 18:21:42 +0000238
239/*-----------------------------------------------------------------------
240 * Start addresses for the final memory configuration
241 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200242 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenka562e1b2005-01-09 18:21:42 +0000243 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200244#define CONFIG_SYS_SDRAM_BASE 0x00000000
wdenka562e1b2005-01-09 18:21:42 +0000245
246/*
247 *-------------------------------------------------------------------------
248 * RAM SIZE (is defined above)
249 *-----------------------------------------------------------------------
250 */
251
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200252/* #define CONFIG_SYS_SDRAM_SIZE 16 */
wdenka562e1b2005-01-09 18:21:42 +0000253
254/*
255 *-----------------------------------------------------------------------
256 */
257
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200258#define CONFIG_SYS_FLASH_BASE 0xffe00000
wdenka562e1b2005-01-09 18:21:42 +0000259
260#ifdef CONFIG_MONITOR_IS_IN_RAM
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200261#define CONFIG_SYS_MONITOR_BASE 0x20000
wdenka562e1b2005-01-09 18:21:42 +0000262#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200263#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
wdenka562e1b2005-01-09 18:21:42 +0000264#endif
265
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200266#define CONFIG_SYS_MONITOR_LEN 0x20000
267#define CONFIG_SYS_MALLOC_LEN (256 << 10)
268#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
wdenka562e1b2005-01-09 18:21:42 +0000269
270/*
271 * For booting Linux, the board info and command line data
272 * have to be in the first 8 MB of memory, since this is
273 * the maximum mapped by the Linux kernel during initialization ??
274 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200275#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenka562e1b2005-01-09 18:21:42 +0000276
277/*-----------------------------------------------------------------------
278 * FLASH organization
279 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200280#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
281#define CONFIG_SYS_MAX_FLASH_SECT 11 /* max number of sectors on one chip */
282#define CONFIG_SYS_FLASH_ERASE_TOUT 1000 /* flash timeout */
wdenka562e1b2005-01-09 18:21:42 +0000283
284/*-----------------------------------------------------------------------
285 * Cache Configuration
286 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200287#define CONFIG_SYS_CACHELINE_SIZE 16
wdenka562e1b2005-01-09 18:21:42 +0000288
TsiChung Liewdd9f0542010-03-11 22:12:53 -0600289#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
Wolfgang Denk553f0982010-10-26 13:32:32 +0200290 CONFIG_SYS_INIT_RAM_SIZE - 8)
TsiChung Liewdd9f0542010-03-11 22:12:53 -0600291#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
Wolfgang Denk553f0982010-10-26 13:32:32 +0200292 CONFIG_SYS_INIT_RAM_SIZE - 4)
TsiChung Liewdd9f0542010-03-11 22:12:53 -0600293#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI)
294#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
295 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
296 CF_ACR_EN | CF_ACR_SM_ALL)
297#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \
298 CF_CACR_DISD | CF_CACR_INVI | \
299 CF_CACR_CEIB | CF_CACR_DCM | \
300 CF_CACR_EUSP)
301
wdenka562e1b2005-01-09 18:21:42 +0000302/*-----------------------------------------------------------------------
303 * Memory bank definitions
304 *
305 * Please refer also to Motorola Coldfire user manual - Chapter XXX
306 * <http://e-www.motorola.com/files/dsp/doc/ref_manual/MCF5272UM.pdf>
307 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200308#define CONFIG_SYS_BR0_PRELIM 0xFFE00201
309#define CONFIG_SYS_OR0_PRELIM 0xFFE00014
wdenka562e1b2005-01-09 18:21:42 +0000310
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200311#define CONFIG_SYS_BR1_PRELIM 0
312#define CONFIG_SYS_OR1_PRELIM 0
wdenka562e1b2005-01-09 18:21:42 +0000313
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200314#define CONFIG_SYS_BR2_PRELIM 0
315#define CONFIG_SYS_OR2_PRELIM 0
wdenka562e1b2005-01-09 18:21:42 +0000316
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200317#define CONFIG_SYS_BR3_PRELIM 0
318#define CONFIG_SYS_OR3_PRELIM 0
wdenka562e1b2005-01-09 18:21:42 +0000319
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200320#define CONFIG_SYS_BR4_PRELIM 0
321#define CONFIG_SYS_OR4_PRELIM 0
wdenka562e1b2005-01-09 18:21:42 +0000322
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200323#define CONFIG_SYS_BR5_PRELIM 0
324#define CONFIG_SYS_OR5_PRELIM 0
wdenka562e1b2005-01-09 18:21:42 +0000325
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200326#define CONFIG_SYS_BR6_PRELIM 0
327#define CONFIG_SYS_OR6_PRELIM 0
wdenka562e1b2005-01-09 18:21:42 +0000328
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200329#define CONFIG_SYS_BR7_PRELIM 0x00000701
330#define CONFIG_SYS_OR7_PRELIM 0xFF00007C
wdenka562e1b2005-01-09 18:21:42 +0000331
332/*-----------------------------------------------------------------------
333 * LED config
334 */
335#define LED_STAT_0 0xffff /*all LEDs off*/
336#define LED_STAT_1 0xfffe
337#define LED_STAT_2 0xfffd
338#define LED_STAT_3 0xfffb
339#define LED_STAT_4 0xfff7
340#define LED_STAT_5 0xffef
341#define LED_STAT_6 0xffdf
342#define LED_STAT_7 0xff00 /*all LEDs on*/
343
344/*-----------------------------------------------------------------------
345 * Port configuration (GPIO)
346 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200347#define CONFIG_SYS_PACNT 0x00000000 /* PortA control reg.: All pins are external
wdenka562e1b2005-01-09 18:21:42 +0000348GPIO*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200349#define CONFIG_SYS_PADDR 0x00FF /* PortA direction reg.: PA7 to PA0 are outputs
wdenka562e1b2005-01-09 18:21:42 +0000350(1^=output, 0^=input) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200351#define CONFIG_SYS_PADAT LED_STAT_0 /* PortA value reg.: Turn all LED off */
352#define CONFIG_SYS_PBCNT 0x55554155 /* PortB control reg.: Ethernet/UART
wdenka562e1b2005-01-09 18:21:42 +0000353configuration */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200354#define CONFIG_SYS_PBDDR 0x0000 /* PortB direction: All pins configured as inputs */
355#define CONFIG_SYS_PBDAT 0x0000 /* PortB value reg. */
356#define CONFIG_SYS_PDCNT 0x00000000 /* PortD control reg. */
wdenka562e1b2005-01-09 18:21:42 +0000357
358#endif /* _CONFIG_COBRA5272_H */