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Liu Hui-R6434394391fb2011-01-03 22:27:42 +00001/*
2 * (C) Copyright 2010 Freescale Semiconductor, Inc.
3 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02004 * SPDX-License-Identifier: GPL-2.0+
Liu Hui-R6434394391fb2011-01-03 22:27:42 +00005 */
6
7#include <common.h>
8#include <asm/io.h>
9#include <asm/arch/imx-regs.h>
Liu Hui-R6434394391fb2011-01-03 22:27:42 +000010#include <asm/arch/sys_proto.h>
11#include <asm/arch/crm_regs.h>
Benoît Thébaudeaua2ac1b32012-10-01 08:36:25 +000012#include <asm/arch/clock.h>
Benoît Thébaudeau58f07642013-05-03 10:32:33 +000013#include <asm/arch/iomux-mx53.h>
Liu Hui-R6434394391fb2011-01-03 22:27:42 +000014#include <asm/errno.h>
Troy Kisky0aff3842012-08-15 10:31:22 +000015#include <asm/imx-common/boot_mode.h>
Liu Hui-R6434394391fb2011-01-03 22:27:42 +000016#include <netdev.h>
17#include <i2c.h>
18#include <mmc.h>
19#include <fsl_esdhc.h>
Łukasz Majewskic7336812012-11-13 03:21:55 +000020#include <power/pmic.h>
Liu Hui-R6434394391fb2011-01-03 22:27:42 +000021#include <fsl_pmic.h>
Stefano Babicf7a36472011-08-21 10:58:22 +020022#include <asm/gpio.h>
Liu Hui-R6434394391fb2011-01-03 22:27:42 +000023#include <mc13892.h>
24
25DECLARE_GLOBAL_DATA_PTR;
26
Liu Hui-R6434394391fb2011-01-03 22:27:42 +000027int dram_init(void)
28{
29 /* dram_init must store complete ramsize in gd->ram_size */
Albert ARIBAUDa55d23c2011-07-03 05:55:33 +000030 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
Liu Hui-R6434394391fb2011-01-03 22:27:42 +000031 PHYS_SDRAM_1_SIZE);
32 return 0;
33}
34
Benoît Thébaudeau58f07642013-05-03 10:32:33 +000035#define UART_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
36 PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
37
Liu Hui-R6434394391fb2011-01-03 22:27:42 +000038static void setup_iomux_uart(void)
39{
Benoît Thébaudeau58f07642013-05-03 10:32:33 +000040 static const iomux_v3_cfg_t uart_pads[] = {
41 NEW_PAD_CTRL(MX53_PAD_CSI0_DAT11__UART1_RXD_MUX, UART_PAD_CTRL),
42 NEW_PAD_CTRL(MX53_PAD_CSI0_DAT10__UART1_TXD_MUX, UART_PAD_CTRL),
43 };
Liu Hui-R6434394391fb2011-01-03 22:27:42 +000044
Benoît Thébaudeau58f07642013-05-03 10:32:33 +000045 imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
Liu Hui-R6434394391fb2011-01-03 22:27:42 +000046}
47
Benoît Thébaudeau58f07642013-05-03 10:32:33 +000048#define I2C_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \
49 PAD_CTL_HYS | PAD_CTL_ODE)
50
Liu Hui-R6434394391fb2011-01-03 22:27:42 +000051static void setup_i2c(unsigned int port_number)
52{
Benoît Thébaudeau58f07642013-05-03 10:32:33 +000053 static const iomux_v3_cfg_t i2c1_pads[] = {
54 NEW_PAD_CTRL(MX53_PAD_CSI0_DAT8__I2C1_SDA, I2C_PAD_CTRL),
55 NEW_PAD_CTRL(MX53_PAD_CSI0_DAT9__I2C1_SCL, I2C_PAD_CTRL),
56 };
57
58 static const iomux_v3_cfg_t i2c2_pads[] = {
59 NEW_PAD_CTRL(MX53_PAD_KEY_ROW3__I2C2_SDA, I2C_PAD_CTRL),
60 NEW_PAD_CTRL(MX53_PAD_KEY_COL3__I2C2_SCL, I2C_PAD_CTRL),
61 };
62
Liu Hui-R6434394391fb2011-01-03 22:27:42 +000063 switch (port_number) {
64 case 0:
Benoît Thébaudeau58f07642013-05-03 10:32:33 +000065 imx_iomux_v3_setup_multiple_pads(i2c1_pads,
66 ARRAY_SIZE(i2c1_pads));
Liu Hui-R6434394391fb2011-01-03 22:27:42 +000067 break;
68 case 1:
Benoît Thébaudeau58f07642013-05-03 10:32:33 +000069 imx_iomux_v3_setup_multiple_pads(i2c2_pads,
70 ARRAY_SIZE(i2c2_pads));
Liu Hui-R6434394391fb2011-01-03 22:27:42 +000071 break;
72 default:
73 printf("Warning: Wrong I2C port number\n");
74 break;
75 }
76}
77
78void power_init(void)
79{
80 unsigned int val;
Stefano Babicbba1b6c2011-10-08 11:00:22 +020081 struct pmic *p;
Łukasz Majewskic7336812012-11-13 03:21:55 +000082 int ret;
Stefano Babicbba1b6c2011-10-08 11:00:22 +020083
Fabio Estevam570aa2f2013-11-20 21:17:36 -020084 ret = pmic_init(I2C_0);
Łukasz Majewskic7336812012-11-13 03:21:55 +000085 if (ret)
86 return;
87
88 p = pmic_get("FSL_PMIC");
89 if (!p)
90 return;
Liu Hui-R6434394391fb2011-01-03 22:27:42 +000091
92 /* Set VDDA to 1.25V */
Stefano Babicbba1b6c2011-10-08 11:00:22 +020093 pmic_reg_read(p, REG_SW_2, &val);
Liu Hui-R6434394391fb2011-01-03 22:27:42 +000094 val &= ~SWX_OUT_MASK;
95 val |= SWX_OUT_1_25;
Stefano Babicbba1b6c2011-10-08 11:00:22 +020096 pmic_reg_write(p, REG_SW_2, val);
Liu Hui-R6434394391fb2011-01-03 22:27:42 +000097
98 /*
99 * Need increase VCC and VDDA to 1.3V
100 * according to MX53 IC TO2 datasheet.
101 */
102 if (is_soc_rev(CHIP_REV_2_0) == 0) {
103 /* Set VCC to 1.3V for TO2 */
Stefano Babicbba1b6c2011-10-08 11:00:22 +0200104 pmic_reg_read(p, REG_SW_1, &val);
Liu Hui-R6434394391fb2011-01-03 22:27:42 +0000105 val &= ~SWX_OUT_MASK;
106 val |= SWX_OUT_1_30;
Stefano Babicbba1b6c2011-10-08 11:00:22 +0200107 pmic_reg_write(p, REG_SW_1, val);
Liu Hui-R6434394391fb2011-01-03 22:27:42 +0000108
109 /* Set VDDA to 1.3V for TO2 */
Stefano Babicbba1b6c2011-10-08 11:00:22 +0200110 pmic_reg_read(p, REG_SW_2, &val);
Liu Hui-R6434394391fb2011-01-03 22:27:42 +0000111 val &= ~SWX_OUT_MASK;
112 val |= SWX_OUT_1_30;
Stefano Babicbba1b6c2011-10-08 11:00:22 +0200113 pmic_reg_write(p, REG_SW_2, val);
Liu Hui-R6434394391fb2011-01-03 22:27:42 +0000114 }
115}
116
117static void setup_iomux_fec(void)
118{
Benoît Thébaudeau58f07642013-05-03 10:32:33 +0000119 static const iomux_v3_cfg_t fec_pads[] = {
120 NEW_PAD_CTRL(MX53_PAD_FEC_MDIO__FEC_MDIO, PAD_CTL_HYS |
121 PAD_CTL_DSE_HIGH | PAD_CTL_PUS_22K_UP | PAD_CTL_ODE),
122 NEW_PAD_CTRL(MX53_PAD_FEC_MDC__FEC_MDC, PAD_CTL_DSE_HIGH),
123 NEW_PAD_CTRL(MX53_PAD_FEC_RXD1__FEC_RDATA_1,
124 PAD_CTL_HYS | PAD_CTL_PKE),
125 NEW_PAD_CTRL(MX53_PAD_FEC_RXD0__FEC_RDATA_0,
126 PAD_CTL_HYS | PAD_CTL_PKE),
127 NEW_PAD_CTRL(MX53_PAD_FEC_TXD1__FEC_TDATA_1, PAD_CTL_DSE_HIGH),
128 NEW_PAD_CTRL(MX53_PAD_FEC_TXD0__FEC_TDATA_0, PAD_CTL_DSE_HIGH),
129 NEW_PAD_CTRL(MX53_PAD_FEC_TX_EN__FEC_TX_EN, PAD_CTL_DSE_HIGH),
130 NEW_PAD_CTRL(MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
131 PAD_CTL_HYS | PAD_CTL_PKE),
132 NEW_PAD_CTRL(MX53_PAD_FEC_RX_ER__FEC_RX_ER,
133 PAD_CTL_HYS | PAD_CTL_PKE),
134 NEW_PAD_CTRL(MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
135 PAD_CTL_HYS | PAD_CTL_PKE),
136 };
Liu Hui-R6434394391fb2011-01-03 22:27:42 +0000137
Benoît Thébaudeau58f07642013-05-03 10:32:33 +0000138 imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
Liu Hui-R6434394391fb2011-01-03 22:27:42 +0000139}
140
141#ifdef CONFIG_FSL_ESDHC
142struct fsl_esdhc_cfg esdhc_cfg[2] = {
Benoît Thébaudeau16e43f32012-08-13 07:28:16 +0000143 {MMC_SDHC1_BASE_ADDR},
144 {MMC_SDHC3_BASE_ADDR},
Liu Hui-R6434394391fb2011-01-03 22:27:42 +0000145};
146
Thierry Reding314284b2012-01-02 01:15:36 +0000147int board_mmc_getcd(struct mmc *mmc)
Liu Hui-R6434394391fb2011-01-03 22:27:42 +0000148{
149 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
Thierry Reding314284b2012-01-02 01:15:36 +0000150 int ret;
Liu Hui-R6434394391fb2011-01-03 22:27:42 +0000151
Benoît Thébaudeau58f07642013-05-03 10:32:33 +0000152 imx_iomux_v3_setup_pad(MX53_PAD_EIM_DA11__GPIO3_11);
Ashok Kumar Reddy92550702012-08-28 07:39:38 +0530153 gpio_direction_input(IMX_GPIO_NR(3, 11));
Benoît Thébaudeau58f07642013-05-03 10:32:33 +0000154 imx_iomux_v3_setup_pad(MX53_PAD_EIM_DA13__GPIO3_13);
Ashok Kumar Reddy92550702012-08-28 07:39:38 +0530155 gpio_direction_input(IMX_GPIO_NR(3, 13));
Fabio Estevama146dca2011-11-15 05:51:31 +0000156
Liu Hui-R6434394391fb2011-01-03 22:27:42 +0000157 if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
Ashok Kumar Reddy92550702012-08-28 07:39:38 +0530158 ret = !gpio_get_value(IMX_GPIO_NR(3, 13));
Liu Hui-R6434394391fb2011-01-03 22:27:42 +0000159 else
Ashok Kumar Reddy92550702012-08-28 07:39:38 +0530160 ret = !gpio_get_value(IMX_GPIO_NR(3, 11));
Liu Hui-R6434394391fb2011-01-03 22:27:42 +0000161
Thierry Reding314284b2012-01-02 01:15:36 +0000162 return ret;
Liu Hui-R6434394391fb2011-01-03 22:27:42 +0000163}
164
Benoît Thébaudeau58f07642013-05-03 10:32:33 +0000165#define SD_CMD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
166 PAD_CTL_PUS_100K_UP)
167#define SD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \
168 PAD_CTL_DSE_HIGH)
169
Liu Hui-R6434394391fb2011-01-03 22:27:42 +0000170int board_mmc_init(bd_t *bis)
171{
Benoît Thébaudeau58f07642013-05-03 10:32:33 +0000172 static const iomux_v3_cfg_t sd1_pads[] = {
173 NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL),
174 NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, SD_PAD_CTRL),
175 NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, SD_PAD_CTRL),
176 NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, SD_PAD_CTRL),
177 NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, SD_PAD_CTRL),
178 NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, SD_PAD_CTRL),
179 MX53_PAD_EIM_DA13__GPIO3_13,
180 };
181
182 static const iomux_v3_cfg_t sd2_pads[] = {
183 NEW_PAD_CTRL(MX53_PAD_PATA_RESET_B__ESDHC3_CMD,
184 SD_CMD_PAD_CTRL),
185 NEW_PAD_CTRL(MX53_PAD_PATA_IORDY__ESDHC3_CLK, SD_PAD_CTRL),
186 NEW_PAD_CTRL(MX53_PAD_PATA_DATA8__ESDHC3_DAT0, SD_PAD_CTRL),
187 NEW_PAD_CTRL(MX53_PAD_PATA_DATA9__ESDHC3_DAT1, SD_PAD_CTRL),
188 NEW_PAD_CTRL(MX53_PAD_PATA_DATA10__ESDHC3_DAT2, SD_PAD_CTRL),
189 NEW_PAD_CTRL(MX53_PAD_PATA_DATA11__ESDHC3_DAT3, SD_PAD_CTRL),
190 NEW_PAD_CTRL(MX53_PAD_PATA_DATA0__ESDHC3_DAT4, SD_PAD_CTRL),
191 NEW_PAD_CTRL(MX53_PAD_PATA_DATA1__ESDHC3_DAT5, SD_PAD_CTRL),
192 NEW_PAD_CTRL(MX53_PAD_PATA_DATA2__ESDHC3_DAT6, SD_PAD_CTRL),
193 NEW_PAD_CTRL(MX53_PAD_PATA_DATA3__ESDHC3_DAT7, SD_PAD_CTRL),
194 MX53_PAD_EIM_DA11__GPIO3_11,
195 };
196
Liu Hui-R6434394391fb2011-01-03 22:27:42 +0000197 u32 index;
Fabio Estevam1abd7142014-11-20 16:35:19 -0200198 int ret;
Liu Hui-R6434394391fb2011-01-03 22:27:42 +0000199
Benoît Thébaudeaua2ac1b32012-10-01 08:36:25 +0000200 esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
201 esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
202
Liu Hui-R6434394391fb2011-01-03 22:27:42 +0000203 for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) {
204 switch (index) {
205 case 0:
Benoît Thébaudeau58f07642013-05-03 10:32:33 +0000206 imx_iomux_v3_setup_multiple_pads(sd1_pads,
207 ARRAY_SIZE(sd1_pads));
Liu Hui-R6434394391fb2011-01-03 22:27:42 +0000208 break;
209 case 1:
Benoît Thébaudeau58f07642013-05-03 10:32:33 +0000210 imx_iomux_v3_setup_multiple_pads(sd2_pads,
211 ARRAY_SIZE(sd2_pads));
Liu Hui-R6434394391fb2011-01-03 22:27:42 +0000212 break;
213 default:
214 printf("Warning: you configured more ESDHC controller"
215 "(%d) as supported by the board(2)\n",
216 CONFIG_SYS_FSL_ESDHC_NUM);
Fabio Estevam1abd7142014-11-20 16:35:19 -0200217 return -EINVAL;
Liu Hui-R6434394391fb2011-01-03 22:27:42 +0000218 }
Fabio Estevam1abd7142014-11-20 16:35:19 -0200219 ret = fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
220 if (ret)
221 return ret;
Liu Hui-R6434394391fb2011-01-03 22:27:42 +0000222 }
223
Fabio Estevam1abd7142014-11-20 16:35:19 -0200224 return 0;
Liu Hui-R6434394391fb2011-01-03 22:27:42 +0000225}
226#endif
227
228int board_early_init_f(void)
229{
230 setup_iomux_uart();
231 setup_iomux_fec();
232
233 return 0;
234}
235
236int board_init(void)
237{
Liu Hui-R6434394391fb2011-01-03 22:27:42 +0000238 /* address of boot parameters */
239 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
240
241 return 0;
242}
243
Troy Kisky0aff3842012-08-15 10:31:22 +0000244#ifdef CONFIG_CMD_BMODE
245static const struct boot_mode board_boot_modes[] = {
246 /* 4 bit bus width */
247 {"mmc0", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x12)},
248 {"mmc1", MAKE_CFGVAL(0x40, 0x20, 0x08, 0x12)},
249 {NULL, 0},
250};
251#endif
252
Liu Hui-R6434394391fb2011-01-03 22:27:42 +0000253int board_late_init(void)
254{
255 setup_i2c(1);
256 power_init();
257
Troy Kisky0aff3842012-08-15 10:31:22 +0000258#ifdef CONFIG_CMD_BMODE
259 add_board_boot_modes(board_boot_modes);
260#endif
Liu Hui-R6434394391fb2011-01-03 22:27:42 +0000261 return 0;
262}
263
264int checkboard(void)
265{
Jason Liu51958902011-04-22 02:55:42 +0000266 puts("Board: MX53EVK\n");
Liu Hui-R6434394391fb2011-01-03 22:27:42 +0000267
Liu Hui-R6434394391fb2011-01-03 22:27:42 +0000268 return 0;
269}