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Minkyu Kang8bc4ee92009-10-01 17:20:40 +09001/*
2 * Copyright (C) 2009 Samsung Electronics
3 * Kyungmin Park <kyungmin.park@samsung.com>
4 * Minkyu Kang <mk7.kang@samsung.com>
5 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02006 * SPDX-License-Identifier: GPL-2.0+
Minkyu Kang8bc4ee92009-10-01 17:20:40 +09007 */
8
9#include <config.h>
Minkyu Kang8bc4ee92009-10-01 17:20:40 +090010#include <asm/arch/cpu.h>
11#include <asm/arch/power.h>
12
13/*
14 * Register usages:
15 *
16 * r5 has zero always
17 */
18
Minkyu Kang8bc4ee92009-10-01 17:20:40 +090019 .globl lowlevel_init
20lowlevel_init:
21 mov r9, lr
22
23 /* r5 has always zero */
24 mov r5, #0
25
26 ldr r8, =S5PC100_GPIO_BASE
27
28 /* Disable Watchdog */
29 ldr r0, =S5PC100_WATCHDOG_BASE @0xEA200000
30 orr r0, r0, #0x0
31 str r5, [r0]
32
Minkyu Kang8bc4ee92009-10-01 17:20:40 +090033 /* setting SRAM */
34 ldr r0, =S5PC100_SROMC_BASE
35 ldr r1, =0x9
36 str r1, [r0]
Minkyu Kang8bc4ee92009-10-01 17:20:40 +090037
38 /* S5PC100 has 3 groups of interrupt sources */
39 ldr r0, =S5PC100_VIC0_BASE @0xE4000000
40 ldr r1, =S5PC100_VIC1_BASE @0xE4000000
41 ldr r2, =S5PC100_VIC2_BASE @0xE4000000
42
43 /* Disable all interrupts (VIC0, VIC1 and VIC2) */
44 mvn r3, #0x0
45 str r3, [r0, #0x14] @INTENCLEAR
46 str r3, [r1, #0x14] @INTENCLEAR
47 str r3, [r2, #0x14] @INTENCLEAR
48
Minkyu Kang8bc4ee92009-10-01 17:20:40 +090049 /* Set all interrupts as IRQ */
50 str r5, [r0, #0xc] @INTSELECT
51 str r5, [r1, #0xc] @INTSELECT
52 str r5, [r2, #0xc] @INTSELECT
53
54 /* Pending Interrupt Clear */
55 str r5, [r0, #0xf00] @INTADDRESS
56 str r5, [r1, #0xf00] @INTADDRESS
57 str r5, [r2, #0xf00] @INTADDRESS
Minkyu Kang8bc4ee92009-10-01 17:20:40 +090058
Minkyu Kang8bc4ee92009-10-01 17:20:40 +090059 /* for UART */
60 bl uart_asm_init
61
62 /* for TZPC */
63 bl tzpc_asm_init
Minkyu Kang8bc4ee92009-10-01 17:20:40 +090064
651:
66 mov lr, r9
67 mov pc, lr
68
Minkyu Kang8bc4ee92009-10-01 17:20:40 +090069/*
70 * system_clock_init: Initialize core clock and bus clock.
71 * void system_clock_init(void)
72 */
73system_clock_init:
Minkyu Kangd93d0f02010-08-13 16:07:35 +090074 ldr r8, =S5PC100_CLOCK_BASE @ 0xE0100000
Minkyu Kang8bc4ee92009-10-01 17:20:40 +090075
76 /* Set Clock divider */
77 ldr r1, =0x00011110
78 str r1, [r8, #0x304]
79 ldr r1, =0x1
80 str r1, [r8, #0x308]
81 ldr r1, =0x00011301
82 str r1, [r8, #0x300]
83
84 /* Set Lock Time */
85 ldr r1, =0xe10 @ Locktime : 0xe10 = 3600
86 str r1, [r8, #0x000] @ APLL_LOCK
87 str r1, [r8, #0x004] @ MPLL_LOCK
88 str r1, [r8, #0x008] @ EPLL_LOCK
89 str r1, [r8, #0x00C] @ HPLL_LOCK
90
91 /* APLL_CON */
92 ldr r1, =0x81bc0400 @ SDIV 0, PDIV 4, MDIV 444 (1332MHz)
93 str r1, [r8, #0x100]
94 /* MPLL_CON */
95 ldr r1, =0x80590201 @ SDIV 1, PDIV 2, MDIV 89 (267MHz)
96 str r1, [r8, #0x104]
97 /* EPLL_CON */
98 ldr r1, =0x80870303 @ SDIV 3, PDIV 3, MDIV 135 (67.5MHz)
99 str r1, [r8, #0x108]
100 /* HPLL_CON */
101 ldr r1, =0x80600603
102 str r1, [r8, #0x10C]
103
104 /* Set Source Clock */
105 ldr r1, =0x1111 @ A, M, E, HPLL Muxing
106 str r1, [r8, #0x200] @ CLK_SRC0
107
108 ldr r1, =0x1000001 @ Uart Clock & CLK48M Muxing
109 str r1, [r8, #0x204] @ CLK_SRC1
110
111 ldr r1, =0x9000 @ ARMCLK/4
112 str r1, [r8, #0x400] @ CLK_OUT
113
114 /* wait at least 200us to stablize all clock */
115 mov r2, #0x10000
1161: subs r2, r2, #1
117 bne 1b
118
119 mov pc, lr
120
Minkyu Kang8bc4ee92009-10-01 17:20:40 +0900121/*
122 * uart_asm_init: Initialize UART's pins
123 */
124uart_asm_init:
125 mov r0, r8
126 ldr r1, =0x22222222
127 str r1, [r0, #0x0] @ GPA0_CON
128 ldr r1, =0x00022222
129 str r1, [r0, #0x20] @ GPA1_CON
130
131 mov pc, lr
132
133/*
134 * tzpc_asm_init: Initialize TZPC
135 */
136tzpc_asm_init:
137 ldr r0, =0xE3800000
138 mov r1, #0x0
139 str r1, [r0]
140 mov r1, #0xff
141 str r1, [r0, #0x804]
142 str r1, [r0, #0x810]
143
144 ldr r0, =0xE2800000
145 str r1, [r0, #0x804]
146 str r1, [r0, #0x810]
147 str r1, [r0, #0x81C]
148
149 ldr r0, =0xE2900000
150 str r1, [r0, #0x804]
151 str r1, [r0, #0x810]
152
153 mov pc, lr