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York Sunb5b06fb2012-12-23 19:25:27 +00001/*
2 * Copyright 2011-2012 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * Version 2 or later as published by the Free Software Foundation.
7 */
8
9#include <common.h>
10#include <i2c.h>
11#include <hwconfig.h>
12#include <asm/mmu.h>
13#include <asm/fsl_ddr_sdram.h>
14#include <asm/fsl_ddr_dimm_params.h>
15#include <asm/fsl_law.h>
York Sun43104792013-03-25 07:39:36 +000016#include <../arch/powerpc/cpu/mpc8xxx/ddr/ddr.h>
York Sunb5b06fb2012-12-23 19:25:27 +000017
18DECLARE_GLOBAL_DATA_PTR;
19
20dimm_params_t ddr_raw_timing = {
21 .n_ranks = 2,
22 .rank_density = 2147483648u,
23 .capacity = 4294967296u,
24 .primary_sdram_width = 64,
25 .ec_sdram_width = 8,
26 .registered_dimm = 0,
27 .mirrored_dimm = 1,
28 .n_row_addr = 15,
29 .n_col_addr = 10,
30 .n_banks_per_sdram_device = 8,
31 .edc_config = 2, /* ECC */
32 .burst_lengths_bitmask = 0x0c,
33
34 .tCKmin_X_ps = 1071,
35 .caslat_X = 0x2fe << 4, /* 5,6,7,8,9,10,11,13 */
36 .tAA_ps = 13910,
37 .tWR_ps = 15000,
38 .tRCD_ps = 13910,
39 .tRRD_ps = 6000,
40 .tRP_ps = 13910,
41 .tRAS_ps = 34000,
42 .tRC_ps = 48910,
43 .tRFC_ps = 260000,
44 .tWTR_ps = 7500,
45 .tRTP_ps = 7500,
46 .refresh_rate_ps = 7800000,
47 .tFAW_ps = 35000,
48};
49
50int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
51 unsigned int controller_number,
52 unsigned int dimm_number)
53{
54 const char dimm_model[] = "RAW timing DDR";
55
56 if ((controller_number == 0) && (dimm_number == 0)) {
57 memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
58 memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
59 memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
60 }
61
62 return 0;
63}
64
65struct board_specific_parameters {
66 u32 n_ranks;
67 u32 datarate_mhz_high;
68 u32 clk_adjust;
69 u32 wrlvl_start;
70 u32 wrlvl_ctl_2;
71 u32 wrlvl_ctl_3;
72 u32 cpo;
73 u32 write_data_delay;
74 u32 force_2T;
75};
76
77/*
78 * This table contains all valid speeds we want to override with board
79 * specific parameters. datarate_mhz_high values need to be in ascending order
80 * for each n_ranks group.
81 */
82static const struct board_specific_parameters udimm0[] = {
83 /*
84 * memory controller 0
85 * num| hi| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T
86 * ranks| mhz|adjst| start | ctl2 | ctl3 | |delay |
87 */
88 {2, 1350, 4, 7, 0x09080807, 0x07060607, 0xff, 2, 0},
89 {2, 1666, 4, 7, 0x09080806, 0x06050607, 0xff, 2, 0},
90 {2, 1900, 3, 7, 0x08070706, 0x06040507, 0xff, 2, 0},
91 {1, 1350, 4, 7, 0x09080807, 0x07060607, 0xff, 2, 0},
92 {1, 1700, 4, 7, 0x09080806, 0x06050607, 0xff, 2, 0},
93 {1, 1900, 3, 7, 0x08070706, 0x06040507, 0xff, 2, 0},
94 {}
95};
96
97static const struct board_specific_parameters *udimms[] = {
98 udimm0,
99};
100
101void fsl_ddr_board_options(memctl_options_t *popts,
102 dimm_params_t *pdimm,
103 unsigned int ctrl_num)
104{
105 const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
106 ulong ddr_freq;
107
108 if (ctrl_num > 2) {
109 printf("Not supported controller number %d\n", ctrl_num);
110 return;
111 }
112 if (!pdimm->n_ranks)
113 return;
114
115 pbsp = udimms[0];
116
117
118 /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
119 * freqency and n_banks specified in board_specific_parameters table.
120 */
121 ddr_freq = get_ddr_freq(0) / 1000000;
122 while (pbsp->datarate_mhz_high) {
123 if (pbsp->n_ranks == pdimm->n_ranks) {
124 if (ddr_freq <= pbsp->datarate_mhz_high) {
125 popts->cpo_override = pbsp->cpo;
126 popts->write_data_delay =
127 pbsp->write_data_delay;
128 popts->clk_adjust = pbsp->clk_adjust;
129 popts->wrlvl_start = pbsp->wrlvl_start;
130 popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
131 popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
132 popts->twoT_en = pbsp->force_2T;
133 goto found;
134 }
135 pbsp_highest = pbsp;
136 }
137 pbsp++;
138 }
139
140 if (pbsp_highest) {
141 printf("Error: board specific timing not found "
142 "for data rate %lu MT/s\n"
143 "Trying to use the highest speed (%u) parameters\n",
144 ddr_freq, pbsp_highest->datarate_mhz_high);
145 popts->cpo_override = pbsp_highest->cpo;
146 popts->write_data_delay = pbsp_highest->write_data_delay;
147 popts->clk_adjust = pbsp_highest->clk_adjust;
148 popts->wrlvl_start = pbsp_highest->wrlvl_start;
149 popts->twoT_en = pbsp_highest->force_2T;
150 } else {
151 panic("DIMM is not supported by this board");
152 }
153found:
154 /*
155 * Factors to consider for half-strength driver enable:
156 * - number of DIMMs installed
157 */
158 popts->half_strength_driver_enable = 0;
159 /*
160 * Write leveling override
161 */
162 popts->wrlvl_override = 1;
163 popts->wrlvl_sample = 0xf;
164
165 /*
166 * Rtt and Rtt_WR override
167 */
168 popts->rtt_override = 0;
169
170 /* Enable ZQ calibration */
171 popts->zq_en = 1;
172
173 /* DHC_EN =1, ODT = 75 Ohm */
174 popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
175 popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
176}
177
178phys_size_t initdram(int board_type)
179{
180 phys_size_t dram_size;
181
182 puts("Initializing....using SPD\n");
183
184 dram_size = fsl_ddr_sdram();
185
186 dram_size = setup_ddr_tlbs(dram_size / 0x100000);
187 dram_size *= 0x100000;
188
189 puts(" DDR: ");
190 return dram_size;
191}
York Sun43104792013-03-25 07:39:36 +0000192
193unsigned long long step_assign_addresses(fsl_ddr_info_t *pinfo,
194 unsigned int dbw_cap_adj[])
195{
196 int i, j;
197 unsigned long long total_mem, current_mem_base, total_ctlr_mem;
198 unsigned long long rank_density, ctlr_density = 0;
199
200 current_mem_base = 0ull;
201 total_mem = 0;
202 /*
203 * This board has soldered DDR chips. DDRC1 has two rank.
204 * DDRC2 has only one rank.
205 * Assigning DDRC2 to lower address and DDRC1 to higher address.
206 */
207 if (pinfo->memctl_opts[0].memctl_interleaving) {
208 rank_density = pinfo->dimm_params[0][0].rank_density >>
209 dbw_cap_adj[0];
210 ctlr_density = rank_density;
211
212 debug("rank density is 0x%llx, ctlr density is 0x%llx\n",
213 rank_density, ctlr_density);
214 for (i = CONFIG_NUM_DDR_CONTROLLERS - 1; i >= 0; i--) {
215 switch (pinfo->memctl_opts[i].memctl_interleaving_mode) {
216 case FSL_DDR_CACHE_LINE_INTERLEAVING:
217 case FSL_DDR_PAGE_INTERLEAVING:
218 case FSL_DDR_BANK_INTERLEAVING:
219 case FSL_DDR_SUPERBANK_INTERLEAVING:
220 total_ctlr_mem = 2 * ctlr_density;
221 break;
222 default:
223 panic("Unknown interleaving mode");
224 }
225 pinfo->common_timing_params[i].base_address =
226 current_mem_base;
227 pinfo->common_timing_params[i].total_mem =
228 total_ctlr_mem;
229 total_mem = current_mem_base + total_ctlr_mem;
230 debug("ctrl %d base 0x%llx\n", i, current_mem_base);
231 debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem);
232 }
233 } else {
234 /*
235 * Simple linear assignment if memory
236 * controllers are not interleaved.
237 */
238 for (i = CONFIG_NUM_DDR_CONTROLLERS - 1; i >= 0; i--) {
239 total_ctlr_mem = 0;
240 pinfo->common_timing_params[i].base_address =
241 current_mem_base;
242 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
243 /* Compute DIMM base addresses. */
244 unsigned long long cap =
245 pinfo->dimm_params[i][j].capacity;
246 pinfo->dimm_params[i][j].base_address =
247 current_mem_base;
248 debug("ctrl %d dimm %d base 0x%llx\n",
249 i, j, current_mem_base);
250 current_mem_base += cap;
251 total_ctlr_mem += cap;
252 }
253 debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem);
254 pinfo->common_timing_params[i].total_mem =
255 total_ctlr_mem;
256 total_mem += total_ctlr_mem;
257 }
258 }
259 debug("Total mem by %s is 0x%llx\n", __func__, total_mem);
260
261 return total_mem;
262}