blob: 32e05af8ab7628906e2ac9ff8d76df6bcc79ae93 [file] [log] [blame]
Dave Liu24c3aca2006-12-07 21:13:15 +08001/*
2 * Copyright (C) 2006 Freescale Semiconductor, Inc.
3 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02004 * SPDX-License-Identifier: GPL-2.0+
Dave Liu24c3aca2006-12-07 21:13:15 +08005 */
6
7#ifndef __CONFIG_H
8#define __CONFIG_H
9
Dave Liu24c3aca2006-12-07 21:13:15 +080010/*
11 * High Level Configuration Options
12 */
13#define CONFIG_E300 1 /* E300 family */
14#define CONFIG_QE 1 /* Has QE */
Peter Tyser0f898602009-05-22 17:23:24 -050015#define CONFIG_MPC83xx 1 /* MPC83xx family */
Peter Tyser2c7920a2009-05-22 17:23:25 -050016#define CONFIG_MPC832x 1 /* MPC832x CPU specific */
Dave Liu24c3aca2006-12-07 21:13:15 +080017#define CONFIG_MPC832XEMDS 1 /* MPC832XEMDS board specific */
Wolfgang Denk2ae18242010-10-06 09:05:45 +020018
19#define CONFIG_SYS_TEXT_BASE 0xFE000000
Dave Liu24c3aca2006-12-07 21:13:15 +080020
21/*
22 * System Clock Setup
23 */
24#ifdef CONFIG_PCISLAVE
25#define CONFIG_83XX_PCICLK 66000000 /* in HZ */
26#else
27#define CONFIG_83XX_CLKIN 66000000 /* in Hz */
28#endif
29
30#ifndef CONFIG_SYS_CLK_FREQ
31#define CONFIG_SYS_CLK_FREQ 66000000
32#endif
33
34/*
35 * Hardware Reset Configuration Word
36 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020037#define CONFIG_SYS_HRCW_LOW (\
Dave Liu24c3aca2006-12-07 21:13:15 +080038 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
39 HRCWL_DDR_TO_SCB_CLK_2X1 |\
40 HRCWL_VCO_1X2 |\
41 HRCWL_CSB_TO_CLKIN_2X1 |\
42 HRCWL_CORE_TO_CSB_2X1 |\
43 HRCWL_CE_PLL_VCO_DIV_2 |\
44 HRCWL_CE_PLL_DIV_1X1 |\
45 HRCWL_CE_TO_PLL_1X3)
46
47#ifdef CONFIG_PCISLAVE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020048#define CONFIG_SYS_HRCW_HIGH (\
Dave Liu24c3aca2006-12-07 21:13:15 +080049 HRCWH_PCI_AGENT |\
50 HRCWH_PCI1_ARBITER_DISABLE |\
51 HRCWH_CORE_ENABLE |\
52 HRCWH_FROM_0XFFF00100 |\
53 HRCWH_BOOTSEQ_DISABLE |\
54 HRCWH_SW_WATCHDOG_DISABLE |\
55 HRCWH_ROM_LOC_LOCAL_16BIT |\
56 HRCWH_BIG_ENDIAN |\
57 HRCWH_LALE_NORMAL)
58#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020059#define CONFIG_SYS_HRCW_HIGH (\
Dave Liu24c3aca2006-12-07 21:13:15 +080060 HRCWH_PCI_HOST |\
61 HRCWH_PCI1_ARBITER_ENABLE |\
62 HRCWH_CORE_ENABLE |\
63 HRCWH_FROM_0X00000100 |\
64 HRCWH_BOOTSEQ_DISABLE |\
65 HRCWH_SW_WATCHDOG_DISABLE |\
66 HRCWH_ROM_LOC_LOCAL_16BIT |\
67 HRCWH_BIG_ENDIAN |\
68 HRCWH_LALE_NORMAL)
69#endif
70
71/*
72 * System IO Config
73 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020074#define CONFIG_SYS_SICRL 0x00000000
Dave Liu24c3aca2006-12-07 21:13:15 +080075
76#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
Tony Li14778582007-08-17 10:35:59 +080077#define CONFIG_BOARD_EARLY_INIT_R
Dave Liu24c3aca2006-12-07 21:13:15 +080078
79/*
80 * IMMR new address
81 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020082#define CONFIG_SYS_IMMR 0xE0000000
Dave Liu24c3aca2006-12-07 21:13:15 +080083
84/*
85 * DDR Setup
86 */
Joe Hershberger989091a2011-10-11 23:57:13 -050087#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
88#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020089#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
Joe Hershberger989091a2011-10-11 23:57:13 -050090#define CONFIG_SYS_DDRCDR 0x73000002 /* DDR II voltage is 1.8V */
Dave Liu24c3aca2006-12-07 21:13:15 +080091
92#undef CONFIG_SPD_EEPROM
93#if defined(CONFIG_SPD_EEPROM)
94/* Determine DDR configuration from I2C interface
95 */
96#define SPD_EEPROM_ADDRESS 0x51 /* DDR SODIMM */
97#else
98/* Manually set up DDR parameters
99 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200100#define CONFIG_SYS_DDR_SIZE 128 /* MB */
Joe Hershberger2fef4022011-10-11 23:57:29 -0500101#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
102 | CSCONFIG_AP \
103 | CSCONFIG_ODT_WR_CFG \
104 | CSCONFIG_ROW_BIT_13 \
105 | CSCONFIG_COL_BIT_10)
106 /* 0x80840102 */
107#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
108 | (0 << TIMING_CFG0_WRT_SHIFT) \
109 | (0 << TIMING_CFG0_RRT_SHIFT) \
110 | (0 << TIMING_CFG0_WWT_SHIFT) \
111 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
112 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
113 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
114 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
115 /* 0x00220802 */
116#define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
117 | (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \
118 | (3 << TIMING_CFG1_ACTTORW_SHIFT) \
119 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
120 | (13 << TIMING_CFG1_REFREC_SHIFT) \
121 | (3 << TIMING_CFG1_WRREC_SHIFT) \
122 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
123 | (2 << TIMING_CFG1_WRTORD_SHIFT))
124 /* 0x3935D322 */
125#define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
126 | (31 << TIMING_CFG2_CPO_SHIFT) \
127 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
128 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
129 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
130 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
131 | (10 << TIMING_CFG2_FOUR_ACT_SHIFT))
132 /* 0x0F9048CA */
Joe Hershberger989091a2011-10-11 23:57:13 -0500133#define CONFIG_SYS_DDR_TIMING_3 0x00000000
Joe Hershberger2fef4022011-10-11 23:57:29 -0500134#define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
135 /* 0x02000000 */
136#define CONFIG_SYS_DDR_MODE ((0x4440 << SDRAM_MODE_ESD_SHIFT) \
137 | (0x0232 << SDRAM_MODE_SD_SHIFT))
138 /* 0x44400232 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200139#define CONFIG_SYS_DDR_MODE2 0x8000c000
Joe Hershberger2fef4022011-10-11 23:57:29 -0500140#define CONFIG_SYS_DDR_INTERVAL ((800 << SDRAM_INTERVAL_REFINT_SHIFT) \
141 | (100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
142 /* 0x03200064 */
Joe Hershberger989091a2011-10-11 23:57:13 -0500143#define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
Joe Hershberger2fef4022011-10-11 23:57:29 -0500144#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
145 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
146 | SDRAM_CFG_32_BE)
147 /* 0x43080000 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200148#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
Dave Liu24c3aca2006-12-07 21:13:15 +0800149#endif
150
151/*
152 * Memory test
153 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200154#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
155#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */
156#define CONFIG_SYS_MEMTEST_END 0x00100000
Dave Liu24c3aca2006-12-07 21:13:15 +0800157
158/*
159 * The reserved memory
160 */
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200161#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
Dave Liu24c3aca2006-12-07 21:13:15 +0800162
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200163#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
164#define CONFIG_SYS_RAMBOOT
Dave Liu24c3aca2006-12-07 21:13:15 +0800165#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200166#undef CONFIG_SYS_RAMBOOT
Dave Liu24c3aca2006-12-07 21:13:15 +0800167#endif
168
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200169/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
Joe Hershberger989091a2011-10-11 23:57:13 -0500170#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
Timur Tabi3b6b2562012-03-17 17:44:00 -0500171#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */
Dave Liu24c3aca2006-12-07 21:13:15 +0800172
173/*
174 * Initial RAM Base Address Setup
175 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200176#define CONFIG_SYS_INIT_RAM_LOCK 1
Joe Hershberger989091a2011-10-11 23:57:13 -0500177#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM addr */
178#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
179#define CONFIG_SYS_GBL_DATA_OFFSET \
180 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Dave Liu24c3aca2006-12-07 21:13:15 +0800181
182/*
183 * Local Bus Configuration & Clock Setup
184 */
Kim Phillipsc7190f02009-09-25 18:19:44 -0500185#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
186#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200187#define CONFIG_SYS_LBC_LBCR 0x00000000
Dave Liu24c3aca2006-12-07 21:13:15 +0800188
189/*
190 * FLASH on the Local Bus
191 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200192#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
Joe Hershberger989091a2011-10-11 23:57:13 -0500193#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
194#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
195#define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size is 16M */
196#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
Dave Liu24c3aca2006-12-07 21:13:15 +0800197
Joe Hershberger989091a2011-10-11 23:57:13 -0500198 /* Window base at flash base */
199#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500200#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB)
Dave Liu24c3aca2006-12-07 21:13:15 +0800201
Joe Hershberger989091a2011-10-11 23:57:13 -0500202#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500203 | BR_PS_16 /* 16 bit port */ \
204 | BR_MS_GPCM /* MSEL = GPCM */ \
205 | BR_V) /* valid */
206#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
207 | OR_GPCM_XAM \
208 | OR_GPCM_CSNT \
209 | OR_GPCM_ACS_DIV2 \
210 | OR_GPCM_XACS \
211 | OR_GPCM_SCY_15 \
212 | OR_GPCM_TRLX_SET \
213 | OR_GPCM_EHTR_SET \
214 | OR_GPCM_EAD)
215 /* 0xfe006ff7 */
Dave Liu24c3aca2006-12-07 21:13:15 +0800216
Joe Hershberger989091a2011-10-11 23:57:13 -0500217#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
218#define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
Dave Liu24c3aca2006-12-07 21:13:15 +0800219
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200220#undef CONFIG_SYS_FLASH_CHECKSUM
Dave Liu24c3aca2006-12-07 21:13:15 +0800221
222/*
223 * BCSR on the Local Bus
224 */
Joe Hershberger989091a2011-10-11 23:57:13 -0500225#define CONFIG_SYS_BCSR 0xF8000000
226 /* Access window base at BCSR base */
227#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500228#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
Dave Liu24c3aca2006-12-07 21:13:15 +0800229
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500230#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR \
231 | BR_PS_8 \
232 | BR_MS_GPCM \
233 | BR_V)
234#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \
235 | OR_GPCM_XAM \
236 | OR_GPCM_CSNT \
237 | OR_GPCM_XACS \
238 | OR_GPCM_SCY_15 \
239 | OR_GPCM_TRLX_SET \
240 | OR_GPCM_EHTR_SET \
241 | OR_GPCM_EAD)
242 /* 0xFFFFE9F7 */
Dave Liu24c3aca2006-12-07 21:13:15 +0800243
244/*
245 * Windows to access PIB via local bus
246 */
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500247 /* PIB window base 0xF8008000 */
248#define CONFIG_SYS_PIB_BASE 0xF8008000
249#define CONFIG_SYS_PIB_WINDOW_SIZE (32 * 1024)
250#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_PIB_BASE
251#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_64KB)
Dave Liu24c3aca2006-12-07 21:13:15 +0800252
253/*
254 * CS2 on Local Bus, to PIB
255 */
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500256#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_PIB_BASE \
257 | BR_PS_8 \
258 | BR_MS_GPCM \
259 | BR_V)
260 /* 0xF8008801 */
261#define CONFIG_SYS_OR2_PRELIM (P2SZ_TO_AM(CONFIG_SYS_PIB_WINDOW_SIZE) \
262 | OR_GPCM_XAM \
263 | OR_GPCM_CSNT \
264 | OR_GPCM_XACS \
265 | OR_GPCM_SCY_15 \
266 | OR_GPCM_TRLX_SET \
267 | OR_GPCM_EHTR_SET \
268 | OR_GPCM_EAD)
269 /* 0xffffe9f7 */
Dave Liu24c3aca2006-12-07 21:13:15 +0800270
271/*
272 * CS3 on Local Bus, to PIB
273 */
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500274#define CONFIG_SYS_BR3_PRELIM ((CONFIG_SYS_PIB_BASE + \
275 CONFIG_SYS_PIB_WINDOW_SIZE) \
276 | BR_PS_8 \
277 | BR_MS_GPCM \
278 | BR_V)
279 /* 0xF8010801 */
280#define CONFIG_SYS_OR3_PRELIM (P2SZ_TO_AM(CONFIG_SYS_PIB_WINDOW_SIZE) \
281 | OR_GPCM_XAM \
282 | OR_GPCM_CSNT \
283 | OR_GPCM_XACS \
284 | OR_GPCM_SCY_15 \
285 | OR_GPCM_TRLX_SET \
286 | OR_GPCM_EHTR_SET \
287 | OR_GPCM_EAD)
288 /* 0xffffe9f7 */
Dave Liu24c3aca2006-12-07 21:13:15 +0800289
290/*
291 * Serial Port
292 */
293#define CONFIG_CONS_INDEX 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200294#define CONFIG_SYS_NS16550
295#define CONFIG_SYS_NS16550_SERIAL
296#define CONFIG_SYS_NS16550_REG_SIZE 1
297#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
Dave Liu24c3aca2006-12-07 21:13:15 +0800298
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200299#define CONFIG_SYS_BAUDRATE_TABLE \
Joe Hershberger989091a2011-10-11 23:57:13 -0500300 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
Dave Liu24c3aca2006-12-07 21:13:15 +0800301
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200302#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
303#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
Dave Liu24c3aca2006-12-07 21:13:15 +0800304
Kim Phillips22d71a72007-02-27 18:41:08 -0600305#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
Kim Phillipsa059e902010-04-15 17:36:05 -0500306#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
Dave Liu24c3aca2006-12-07 21:13:15 +0800307/* Use the HUSH parser */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200308#define CONFIG_SYS_HUSH_PARSER
Dave Liu24c3aca2006-12-07 21:13:15 +0800309
310/* pass open firmware flat tree */
Kim Phillips35cc4e42007-08-15 22:30:39 -0500311#define CONFIG_OF_LIBFDT 1
Dave Liu24c3aca2006-12-07 21:13:15 +0800312#define CONFIG_OF_BOARD_SETUP 1
Kim Phillips5b8bc602007-12-20 14:09:22 -0600313#define CONFIG_OF_STDOUT_VIA_ALIAS 1
Dave Liu24c3aca2006-12-07 21:13:15 +0800314
315/* I2C */
Heiko Schocher00f792e2012-10-24 13:48:22 +0200316#define CONFIG_SYS_I2C
317#define CONFIG_SYS_I2C_FSL
318#define CONFIG_SYS_FSL_I2C_SPEED 400000
319#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
320#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
321#define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} }
Dave Liu24c3aca2006-12-07 21:13:15 +0800322
323/*
324 * Config on-board RTC
325 */
326#define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200327#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
Dave Liu24c3aca2006-12-07 21:13:15 +0800328
329/*
330 * General PCI
331 * Addresses are mapped 1-1.
332 */
Kim Phillips9993e192009-07-18 18:42:13 -0500333#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
334#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
335#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
336#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
337#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
338#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
339#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
340#define CONFIG_SYS_PCI1_IO_PHYS 0xE0300000
341#define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */
Dave Liu24c3aca2006-12-07 21:13:15 +0800342
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200343#define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE
344#define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000
345#define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000
Dave Liu24c3aca2006-12-07 21:13:15 +0800346
347
348#ifdef CONFIG_PCI
Gabor Juhos842033e2013-05-30 07:06:12 +0000349#define CONFIG_PCI_INDIRECT_BRIDGE
Dave Liu24c3aca2006-12-07 21:13:15 +0800350
Dave Liu24c3aca2006-12-07 21:13:15 +0800351#define CONFIG_PCI_PNP /* do pci plug-and-play */
Kim Phillips9993e192009-07-18 18:42:13 -0500352#define CONFIG_83XX_PCI_STREAMING
Dave Liu24c3aca2006-12-07 21:13:15 +0800353
354#undef CONFIG_EEPRO100
355#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200356#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
Dave Liu24c3aca2006-12-07 21:13:15 +0800357
358#endif /* CONFIG_PCI */
359
Dave Liu24c3aca2006-12-07 21:13:15 +0800360/*
361 * QE UEC ethernet configuration
362 */
363#define CONFIG_UEC_ETH
Kim Phillips78b7a8e2010-07-26 18:34:57 -0500364#define CONFIG_ETHPRIME "UEC0"
Dave Liu24c3aca2006-12-07 21:13:15 +0800365
366#define CONFIG_UEC_ETH1 /* ETH3 */
367
368#ifdef CONFIG_UEC_ETH1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200369#define CONFIG_SYS_UEC1_UCC_NUM 2 /* UCC3 */
370#define CONFIG_SYS_UEC1_RX_CLK QE_CLK9
371#define CONFIG_SYS_UEC1_TX_CLK QE_CLK10
372#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
373#define CONFIG_SYS_UEC1_PHY_ADDR 3
Andy Fleming865ff852011-04-13 00:37:12 -0500374#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_MII
Heiko Schocher582c55a2010-01-20 09:04:28 +0100375#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
Dave Liu24c3aca2006-12-07 21:13:15 +0800376#endif
377
378#define CONFIG_UEC_ETH2 /* ETH4 */
379
380#ifdef CONFIG_UEC_ETH2
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200381#define CONFIG_SYS_UEC2_UCC_NUM 3 /* UCC4 */
382#define CONFIG_SYS_UEC2_RX_CLK QE_CLK7
383#define CONFIG_SYS_UEC2_TX_CLK QE_CLK8
384#define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH
385#define CONFIG_SYS_UEC2_PHY_ADDR 4
Andy Fleming865ff852011-04-13 00:37:12 -0500386#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_MII
Heiko Schocher582c55a2010-01-20 09:04:28 +0100387#define CONFIG_SYS_UEC2_INTERFACE_SPEED 100
Dave Liu24c3aca2006-12-07 21:13:15 +0800388#endif
389
390/*
391 * Environment
392 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200393#ifndef CONFIG_SYS_RAMBOOT
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200394 #define CONFIG_ENV_IS_IN_FLASH 1
Joe Hershberger989091a2011-10-11 23:57:13 -0500395 #define CONFIG_ENV_ADDR \
396 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200397 #define CONFIG_ENV_SECT_SIZE 0x20000
398 #define CONFIG_ENV_SIZE 0x2000
Dave Liu24c3aca2006-12-07 21:13:15 +0800399#else
Joe Hershberger989091a2011-10-11 23:57:13 -0500400 #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
Jean-Christophe PLAGNIOL-VILLARD93f6d722008-09-10 22:48:00 +0200401 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200402 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200403 #define CONFIG_ENV_SIZE 0x2000
Dave Liu24c3aca2006-12-07 21:13:15 +0800404#endif
405
406#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200407#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
Dave Liu24c3aca2006-12-07 21:13:15 +0800408
Jon Loeliger8ea54992007-07-04 22:30:06 -0500409/*
Jon Loeliger079a1362007-07-10 10:12:10 -0500410 * BOOTP options
411 */
412#define CONFIG_BOOTP_BOOTFILESIZE
413#define CONFIG_BOOTP_BOOTPATH
414#define CONFIG_BOOTP_GATEWAY
415#define CONFIG_BOOTP_HOSTNAME
416
417
418/*
Jon Loeliger8ea54992007-07-04 22:30:06 -0500419 * Command line configuration.
420 */
421#include <config_cmd_default.h>
422
423#define CONFIG_CMD_PING
424#define CONFIG_CMD_I2C
425#define CONFIG_CMD_ASKENV
426
Dave Liu24c3aca2006-12-07 21:13:15 +0800427#if defined(CONFIG_PCI)
Jon Loeliger8ea54992007-07-04 22:30:06 -0500428 #define CONFIG_CMD_PCI
Dave Liu24c3aca2006-12-07 21:13:15 +0800429#endif
430
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200431#if defined(CONFIG_SYS_RAMBOOT)
Mike Frysingerbdab39d2009-01-28 19:08:14 -0500432 #undef CONFIG_CMD_SAVEENV
Jon Loeliger8ea54992007-07-04 22:30:06 -0500433 #undef CONFIG_CMD_LOADS
434#endif
435
Dave Liu24c3aca2006-12-07 21:13:15 +0800436
437#undef CONFIG_WATCHDOG /* watchdog disabled */
438
439/*
440 * Miscellaneous configurable options
441 */
Joe Hershberger989091a2011-10-11 23:57:13 -0500442#define CONFIG_SYS_LONGHELP /* undef to save memory */
443#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
444#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Dave Liu24c3aca2006-12-07 21:13:15 +0800445
Jon Loeliger8ea54992007-07-04 22:30:06 -0500446#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200447 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Dave Liu24c3aca2006-12-07 21:13:15 +0800448#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200449 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Dave Liu24c3aca2006-12-07 21:13:15 +0800450#endif
451
Joe Hershberger989091a2011-10-11 23:57:13 -0500452 /* Print Buffer Size */
453#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
454#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
455 /* Boot Argument Buffer Size */
456#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
457#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
Dave Liu24c3aca2006-12-07 21:13:15 +0800458
459/*
460 * For booting Linux, the board info and command line data
Ira W. Snyder9f530d52010-09-10 15:42:32 -0700461 * have to be in the first 256 MB of memory, since this is
Dave Liu24c3aca2006-12-07 21:13:15 +0800462 * the maximum mapped by the Linux kernel during initialization.
463 */
Joe Hershberger989091a2011-10-11 23:57:13 -0500464 /* Initial Memory map for Linux */
465#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
Dave Liu24c3aca2006-12-07 21:13:15 +0800466
467/*
468 * Core HID Setup
469 */
Kim Phillips1a2e2032010-04-20 19:37:54 -0500470#define CONFIG_SYS_HID0_INIT 0x000000000
471#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
472 HID0_ENABLE_INSTRUCTION_CACHE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200473#define CONFIG_SYS_HID2 HID2_HBE
Dave Liu24c3aca2006-12-07 21:13:15 +0800474
475/*
Dave Liu24c3aca2006-12-07 21:13:15 +0800476 * MMU Setup
477 */
478
Becky Bruce31d82672008-05-08 19:02:12 -0500479#define CONFIG_HIGH_BATS 1 /* High BATs supported */
480
Dave Liu24c3aca2006-12-07 21:13:15 +0800481/* DDR: cache cacheable */
Joe Hershberger989091a2011-10-11 23:57:13 -0500482#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500483 | BATL_PP_RW \
Joe Hershberger989091a2011-10-11 23:57:13 -0500484 | BATL_MEMCOHERENCE)
485#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
486 | BATU_BL_256M \
487 | BATU_VS \
488 | BATU_VP)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200489#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
490#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
Dave Liu24c3aca2006-12-07 21:13:15 +0800491
492/* IMMRBAR & PCI IO: cache-inhibit and guarded */
Joe Hershberger989091a2011-10-11 23:57:13 -0500493#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500494 | BATL_PP_RW \
Joe Hershberger989091a2011-10-11 23:57:13 -0500495 | BATL_CACHEINHIBIT \
496 | BATL_GUARDEDSTORAGE)
497#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR \
498 | BATU_BL_4M \
499 | BATU_VS \
500 | BATU_VP)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200501#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
502#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
Dave Liu24c3aca2006-12-07 21:13:15 +0800503
504/* BCSR: cache-inhibit and guarded */
Joe Hershberger989091a2011-10-11 23:57:13 -0500505#define CONFIG_SYS_IBAT2L (CONFIG_SYS_BCSR \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500506 | BATL_PP_RW \
Joe Hershberger989091a2011-10-11 23:57:13 -0500507 | BATL_CACHEINHIBIT \
508 | BATL_GUARDEDSTORAGE)
509#define CONFIG_SYS_IBAT2U (CONFIG_SYS_BCSR \
510 | BATU_BL_128K \
511 | BATU_VS \
512 | BATU_VP)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200513#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
514#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
Dave Liu24c3aca2006-12-07 21:13:15 +0800515
516/* FLASH: icache cacheable, but dcache-inhibit and guarded */
Joe Hershberger989091a2011-10-11 23:57:13 -0500517#define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500518 | BATL_PP_RW \
Joe Hershberger989091a2011-10-11 23:57:13 -0500519 | BATL_MEMCOHERENCE)
520#define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE \
521 | BATU_BL_32M \
522 | BATU_VS \
523 | BATU_VP)
524#define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500525 | BATL_PP_RW \
Joe Hershberger989091a2011-10-11 23:57:13 -0500526 | BATL_CACHEINHIBIT \
527 | BATL_GUARDEDSTORAGE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200528#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
Dave Liu24c3aca2006-12-07 21:13:15 +0800529
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200530#define CONFIG_SYS_IBAT4L (0)
531#define CONFIG_SYS_IBAT4U (0)
532#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
533#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
Dave Liu24c3aca2006-12-07 21:13:15 +0800534
535/* Stack in dcache: cacheable, no memory coherence */
Joe Hershberger72cd4082011-10-11 23:57:28 -0500536#define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
Joe Hershberger989091a2011-10-11 23:57:13 -0500537#define CONFIG_SYS_IBAT5U (CONFIG_SYS_INIT_RAM_ADDR \
538 | BATU_BL_128K \
539 | BATU_VS \
540 | BATU_VP)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200541#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
542#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
Dave Liu24c3aca2006-12-07 21:13:15 +0800543
544#ifdef CONFIG_PCI
545/* PCI MEM space: cacheable */
Joe Hershberger989091a2011-10-11 23:57:13 -0500546#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI1_MEM_PHYS \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500547 | BATL_PP_RW \
Joe Hershberger989091a2011-10-11 23:57:13 -0500548 | BATL_MEMCOHERENCE)
549#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI1_MEM_PHYS \
550 | BATU_BL_256M \
551 | BATU_VS \
552 | BATU_VP)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200553#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
554#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
Dave Liu24c3aca2006-12-07 21:13:15 +0800555/* PCI MMIO space: cache-inhibit and guarded */
Joe Hershberger989091a2011-10-11 23:57:13 -0500556#define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI1_MMIO_PHYS \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500557 | BATL_PP_RW \
Joe Hershberger989091a2011-10-11 23:57:13 -0500558 | BATL_CACHEINHIBIT \
559 | BATL_GUARDEDSTORAGE)
560#define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI1_MMIO_PHYS \
561 | BATU_BL_256M \
562 | BATU_VS \
563 | BATU_VP)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200564#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
565#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
Dave Liu24c3aca2006-12-07 21:13:15 +0800566#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200567#define CONFIG_SYS_IBAT6L (0)
568#define CONFIG_SYS_IBAT6U (0)
569#define CONFIG_SYS_IBAT7L (0)
570#define CONFIG_SYS_IBAT7U (0)
571#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
572#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
573#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
574#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
Dave Liu24c3aca2006-12-07 21:13:15 +0800575#endif
576
Jon Loeliger8ea54992007-07-04 22:30:06 -0500577#if defined(CONFIG_CMD_KGDB)
Dave Liu24c3aca2006-12-07 21:13:15 +0800578#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
579#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
580#endif
581
582/*
583 * Environment Configuration
Kim Phillips9993e192009-07-18 18:42:13 -0500584 */ #define CONFIG_ENV_OVERWRITE
Dave Liu24c3aca2006-12-07 21:13:15 +0800585
586#if defined(CONFIG_UEC_ETH)
Kim Phillips977b5752008-01-09 15:24:06 -0600587#define CONFIG_HAS_ETH0
Dave Liu24c3aca2006-12-07 21:13:15 +0800588#define CONFIG_HAS_ETH1
Dave Liu24c3aca2006-12-07 21:13:15 +0800589#endif
590
591#define CONFIG_BAUDRATE 115200
592
Kim Phillips79f516b2009-08-21 16:34:38 -0500593#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
Dave Liu24c3aca2006-12-07 21:13:15 +0800594
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200595#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
Dave Liu24c3aca2006-12-07 21:13:15 +0800596#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
597
598#define CONFIG_EXTRA_ENV_SETTINGS \
Joe Hershberger989091a2011-10-11 23:57:13 -0500599 "netdev=eth0\0" \
600 "consoledev=ttyS0\0" \
601 "ramdiskaddr=1000000\0" \
602 "ramdiskfile=ramfs.83xx\0" \
603 "fdtaddr=780000\0" \
604 "fdtfile=mpc832x_mds.dtb\0" \
605 ""
Dave Liu24c3aca2006-12-07 21:13:15 +0800606
607#define CONFIG_NFSBOOTCOMMAND \
Joe Hershberger989091a2011-10-11 23:57:13 -0500608 "setenv bootargs root=/dev/nfs rw " \
609 "nfsroot=$serverip:$rootpath " \
610 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
611 "$netdev:off " \
612 "console=$consoledev,$baudrate $othbootargs;" \
613 "tftp $loadaddr $bootfile;" \
614 "tftp $fdtaddr $fdtfile;" \
615 "bootm $loadaddr - $fdtaddr"
Dave Liu24c3aca2006-12-07 21:13:15 +0800616
617#define CONFIG_RAMBOOTCOMMAND \
Joe Hershberger989091a2011-10-11 23:57:13 -0500618 "setenv bootargs root=/dev/ram rw " \
619 "console=$consoledev,$baudrate $othbootargs;" \
620 "tftp $ramdiskaddr $ramdiskfile;" \
621 "tftp $loadaddr $bootfile;" \
622 "tftp $fdtaddr $fdtfile;" \
623 "bootm $loadaddr $ramdiskaddr $fdtaddr"
Dave Liu24c3aca2006-12-07 21:13:15 +0800624
625
626#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
627
628#endif /* __CONFIG_H */