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wdenk0f8c9762002-08-19 11:57:05 +00001/*
wdenk414eec32005-04-02 22:37:54 +00002 * (C) Copyright 2001-2005
wdenk0f8c9762002-08-19 11:57:05 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
wdenk0f8c9762002-08-19 11:57:05 +00006 */
7
8/*
9 * board/config.h - configuration options, board specific
10 */
11
12#ifndef __CONFIG_H
13#define __CONFIG_H
14
15/*
16 * Imported from global configuration:
wdenk27b207f2003-07-24 23:38:38 +000017 * CONFIG_MPC8255
18 * CONFIG_MPC8265
19 * CONFIG_200MHz
wdenk0f8c9762002-08-19 11:57:05 +000020 * CONFIG_266MHz
21 * CONFIG_300MHz
wdenk27b207f2003-07-24 23:38:38 +000022 * CONFIG_L2_CACHE
23 * CONFIG_BUSMODE_60x
wdenk0f8c9762002-08-19 11:57:05 +000024 */
25
26/*
27 * High Level Configuration Options
28 * (easy to change)
29 */
30
Wolfgang Denk2ae18242010-10-06 09:05:45 +020031#define CONFIG_SYS_TEXT_BASE 0x40000000
32
wdenk0f8c9762002-08-19 11:57:05 +000033#define CONFIG_MPC8260 1 /* This is a MPC8260 CPU */
34
35#if 0
36#define CONFIG_TQM8260 100 /* ...on a TQM8260 module Rev.100 */
37#else
38#define CONFIG_TQM8260 200 /* ...on a TQM8260 module Rev.200 */
39#endif
40
Jon Loeliger9c4c5ae2005-07-23 10:37:35 -050041#define CONFIG_CPM2 1 /* Has a CPM2 */
42
wdenk0f8c9762002-08-19 11:57:05 +000043#define CONFIG_82xx_CONS_SMC1 1 /* console on SMC1 */
44
45#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
46
wdenkae3af052003-08-07 22:18:11 +000047#define CONFIG_BOOTCOUNT_LIMIT
48
Wolfgang Denk055b12f2008-10-19 21:54:30 +020049#define CONFIG_BAUDRATE 115200
wdenk0f8c9762002-08-19 11:57:05 +000050
Wolfgang Denk32bf3d12008-03-03 12:16:44 +010051#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
wdenk0f8c9762002-08-19 11:57:05 +000052
53#undef CONFIG_BOOTARGS
wdenk506f0442003-03-28 14:40:36 +000054
55#define CONFIG_EXTRA_ENV_SETTINGS \
wdenkae3af052003-08-07 22:18:11 +000056 "netdev=eth0\0" \
wdenk506f0442003-03-28 14:40:36 +000057 "nfsargs=setenv bootargs root=/dev/nfs rw " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010058 "nfsroot=${serverip}:${rootpath}\0" \
wdenk506f0442003-03-28 14:40:36 +000059 "ramargs=setenv bootargs root=/dev/ram rw\0" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010060 "addip=setenv bootargs ${bootargs} " \
61 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
62 ":${hostname}:${netdev}:off panic=1\0" \
wdenk506f0442003-03-28 14:40:36 +000063 "flash_nfs=run nfsargs addip;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010064 "bootm ${kernel_addr}\0" \
wdenk506f0442003-03-28 14:40:36 +000065 "flash_self=run ramargs addip;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010066 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
67 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
Wolfgang Denk055b12f2008-10-19 21:54:30 +020068 "rootpath=/opt/eldk/ppc_6xx\0" \
69 "bootfile=tqm8260/uImage\0" \
Wolfgang Denk86b4baf2009-02-17 10:26:38 +010070 "kernel_addr=400C0000\0" \
71 "ramdisk_addr=40240000\0" \
wdenk506f0442003-03-28 14:40:36 +000072 ""
73#define CONFIG_BOOTCOMMAND "run flash_self"
wdenk0f8c9762002-08-19 11:57:05 +000074
75/* enable I2C and select the hardware/software driver */
Heiko Schocherea818db2013-01-29 08:53:15 +010076#define CONFIG_SYS_I2C
77#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
78#define CONFIG_SYS_I2C_SOFT_SPEED 400000
79#define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F
wdenk0f8c9762002-08-19 11:57:05 +000080
81/*
82 * Software (bit-bang) I2C driver configuration
83 */
84
85/* TQM8260 Rev.100 has the clock and data pins swapped (!!!) on EEPROM */
86#if (CONFIG_TQM8260 <= 100)
87
88#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
89#define I2C_ACTIVE (iop->pdir |= 0x00020000)
90#define I2C_TRISTATE (iop->pdir &= ~0x00020000)
91#define I2C_READ ((iop->pdat & 0x00020000) != 0)
92#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00020000; \
93 else iop->pdat &= ~0x00020000
94#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00010000; \
95 else iop->pdat &= ~0x00010000
96#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
97
98#else
99
100#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
101#define I2C_ACTIVE (iop->pdir |= 0x00010000)
102#define I2C_TRISTATE (iop->pdir &= ~0x00010000)
103#define I2C_READ ((iop->pdat & 0x00010000) != 0)
104#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \
105 else iop->pdat &= ~0x00010000
106#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \
107 else iop->pdat &= ~0x00020000
108#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
109#endif
110
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200111#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
112#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
113#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
114#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
wdenk0f8c9762002-08-19 11:57:05 +0000115
116#define CONFIG_I2C_X
117
118/*
119 * select serial console configuration
120 *
121 * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
122 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
123 * for SCC).
124 *
125 * if CONFIG_CONS_NONE is defined, then the serial console routines must
126 * defined elsewhere (for example, on the cogent platform, there are serial
127 * ports on the motherboard which are used for the serial console - see
128 * cogent/cma101/serial.[ch]).
129 */
130#define CONFIG_CONS_ON_SMC /* define if console on SMC */
131#undef CONFIG_CONS_ON_SCC /* define if console on SCC */
132#undef CONFIG_CONS_NONE /* define if console on something else*/
133#ifdef CONFIG_82xx_CONS_SMC1
134#define CONFIG_CONS_INDEX 1 /* which serial channel for console */
135#endif
136#ifdef CONFIG_82xx_CONS_SMC2
137#define CONFIG_CONS_INDEX 2 /* which serial channel for console */
138#endif
139
140#undef CONFIG_CONS_USE_EXTC /* SMC/SCC use ext clock not brg_clk */
141#define CONFIG_CONS_EXTC_RATE 3686400 /* SMC/SCC ext clk rate in Hz */
142#define CONFIG_CONS_EXTC_PINSEL 0 /* pin select 0=CLK3/CLK9 */
143
144/*
145 * select ethernet configuration
146 *
147 * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
148 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
149 * for FCC)
150 *
151 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
Jon Loeliger639221c2007-07-09 17:15:49 -0500152 * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
wdenk0f8c9762002-08-19 11:57:05 +0000153 *
154 * (On TQM8260 either SCC1 or FCC2 may be chosen: SCC1 is hardwired to the
155 * X.29 connector, and FCC2 is hardwired to the X.1 connector)
156 */
157#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
158#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */
159#undef CONFIG_ETHER_NONE /* define if ether on something else */
160#define CONFIG_ETHER_INDEX 2 /* which SCC/FCC channel for ethernet */
161
162#if defined(CONFIG_ETHER_ON_SCC) && (CONFIG_ETHER_INDEX == 1)
163
164/*
165 * - RX clk is CLK11
166 * - TX clk is CLK12
167 */
Mike Frysingerd4590da2011-10-17 05:38:58 +0000168# define CONFIG_SYS_CMXSCR_VALUE1 (CMXSCR_RS1CS_CLK11 | CMXSCR_TS1CS_CLK12)
wdenk0f8c9762002-08-19 11:57:05 +0000169
170#elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
171
172/*
173 * - Rx-CLK is CLK13
174 * - Tx-CLK is CLK14
175 * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
176 * - Enable Full Duplex in FSMR
177 */
Mike Frysingerd4590da2011-10-17 05:38:58 +0000178# define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
179# define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200180# define CONFIG_SYS_CPMFCR_RAMTYPE 0
181# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB)
wdenk0f8c9762002-08-19 11:57:05 +0000182
183#endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */
184
185
186/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
wdenk27b207f2003-07-24 23:38:38 +0000187#if defined(CONFIG_MPC8255) || defined(CONFIG_MPC8265)
wdenk7aa78612003-05-03 15:50:43 +0000188# define CONFIG_8260_CLKIN 66666666 /* in Hz */
wdenk27b207f2003-07-24 23:38:38 +0000189#else /* !CONFIG_MPC8255 && !CONFIG_MPC8265 */
wdenk7aa78612003-05-03 15:50:43 +0000190# ifndef CONFIG_300MHz
191# define CONFIG_8260_CLKIN 66666666 /* in Hz */
192# else
193# define CONFIG_8260_CLKIN 83333000 /* in Hz */
194# endif
195#endif /* CONFIG_MPC8255 */
wdenk0f8c9762002-08-19 11:57:05 +0000196
wdenk0f8c9762002-08-19 11:57:05 +0000197#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200198#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
wdenk0f8c9762002-08-19 11:57:05 +0000199
200#undef CONFIG_WATCHDOG /* watchdog disabled */
201
wdenk414eec32005-04-02 22:37:54 +0000202#define CONFIG_TIMESTAMP /* Print image info with timestamp */
203
Jon Loeliger37d4bb72007-07-09 21:38:02 -0500204
205/*
206 * BOOTP options
207 */
208#define CONFIG_BOOTP_SUBNETMASK
209#define CONFIG_BOOTP_GATEWAY
210#define CONFIG_BOOTP_HOSTNAME
211#define CONFIG_BOOTP_BOOTPATH
212#define CONFIG_BOOTP_BOOTFILESIZE
wdenk0f8c9762002-08-19 11:57:05 +0000213
wdenk0f8c9762002-08-19 11:57:05 +0000214
Jon Loeliger26946902007-07-04 22:30:50 -0500215/*
216 * Command line configuration.
217 */
218#include <config_cmd_default.h>
219
220#define CONFIG_CMD_DHCP
221#define CONFIG_CMD_I2C
222#define CONFIG_CMD_EEPROM
223#define CONFIG_CMD_NFS
224#define CONFIG_CMD_SNTP
225
wdenk0f8c9762002-08-19 11:57:05 +0000226
227/*
228 * Miscellaneous configurable options
229 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200230#define CONFIG_SYS_LONGHELP /* undef to save memory */
231#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Wolfgang Denk2751a952006-10-28 02:29:14 +0200232
233#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200234#define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */
Wolfgang Denk2751a952006-10-28 02:29:14 +0200235
Jon Loeliger26946902007-07-04 22:30:50 -0500236#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200237#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenk0f8c9762002-08-19 11:57:05 +0000238#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200239#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenk0f8c9762002-08-19 11:57:05 +0000240#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200241#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
242#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
243#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenk0f8c9762002-08-19 11:57:05 +0000244
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200245#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
246#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
wdenk0f8c9762002-08-19 11:57:05 +0000247
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200248#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
wdenk0f8c9762002-08-19 11:57:05 +0000249
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200250#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenk0f8c9762002-08-19 11:57:05 +0000251
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200252#define CONFIG_SYS_RESET_ADDRESS 0xFFFFFFFC /* "bad" address */
wdenk0f8c9762002-08-19 11:57:05 +0000253
254/*
255 * For booting Linux, the board info and command line data
256 * have to be in the first 8 MB of memory, since this is
257 * the maximum mapped by the Linux kernel during initialization.
258 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200259#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenk0f8c9762002-08-19 11:57:05 +0000260
261
262/* What should the base address of the main FLASH be and how big is
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200263 * it (in MBytes)? This must contain CONFIG_SYS_TEXT_BASE from board/tqm8260/config.mk
wdenk0f8c9762002-08-19 11:57:05 +0000264 * The main FLASH is whichever is connected to *CS0.
265 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200266#define CONFIG_SYS_FLASH0_BASE 0x40000000
267#define CONFIG_SYS_FLASH1_BASE 0x60000000
268#define CONFIG_SYS_FLASH0_SIZE 32
269#define CONFIG_SYS_FLASH1_SIZE 32
wdenk0f8c9762002-08-19 11:57:05 +0000270
271/* Flash bank size (for preliminary settings)
272 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200273#define CONFIG_SYS_FLASH_SIZE CONFIG_SYS_FLASH0_SIZE
wdenk0f8c9762002-08-19 11:57:05 +0000274
275/*-----------------------------------------------------------------------
276 * FLASH organization
277 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200278#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
279#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */
wdenk0f8c9762002-08-19 11:57:05 +0000280
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200281#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
282#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
wdenk0f8c9762002-08-19 11:57:05 +0000283
Wolfgang Denk60c68d92008-10-31 01:13:37 +0100284/* use CFI flash driver */
285#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
286#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
287#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
288#define CONFIG_SYS_FLASH_EMPTY_INFO 1
289#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
290
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200291#define CONFIG_ENV_IS_IN_FLASH 1
Wolfgang Denk055b12f2008-10-19 21:54:30 +0200292#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000)
293#define CONFIG_ENV_SIZE 0x08000
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200294#define CONFIG_ENV_SECT_SIZE 0x40000
Wolfgang Denk055b12f2008-10-19 21:54:30 +0200295#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
296#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
wdenk0f8c9762002-08-19 11:57:05 +0000297
298/*-----------------------------------------------------------------------
299 * Hardware Information Block
300 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200301#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
302#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */
303#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
wdenk0f8c9762002-08-19 11:57:05 +0000304
305/*-----------------------------------------------------------------------
306 * Hard Reset Configuration Words
307 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200308 * if you change bits in the HRCW, you must also change the CONFIG_SYS_*
wdenk0f8c9762002-08-19 11:57:05 +0000309 * defines for the various registers affected by the HRCW e.g. changing
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200310 * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR.
wdenk0f8c9762002-08-19 11:57:05 +0000311 */
wdenk7aa78612003-05-03 15:50:43 +0000312#define __HRCW__ALL__ (HRCW_CIP | HRCW_ISB111 | HRCW_BMS)
313
wdenk27b207f2003-07-24 23:38:38 +0000314#if defined(CONFIG_MPC8255) || defined(CONFIG_MPC8265)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200315# define CONFIG_SYS_HRCW_MASTER (__HRCW__ALL__ | HRCW_MODCK_H0111)
wdenk27b207f2003-07-24 23:38:38 +0000316#else /* ! MPC8255 && !MPC8265 */
wdenk7aa78612003-05-03 15:50:43 +0000317# if defined(CONFIG_266MHz)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200318# define CONFIG_SYS_HRCW_MASTER (__HRCW__ALL__ | HRCW_MODCK_H0111)
wdenk7aa78612003-05-03 15:50:43 +0000319# elif defined(CONFIG_300MHz)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200320# define CONFIG_SYS_HRCW_MASTER (__HRCW__ALL__ | HRCW_MODCK_H0110)
wdenk7aa78612003-05-03 15:50:43 +0000321# else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200322# define CONFIG_SYS_HRCW_MASTER (__HRCW__ALL__)
wdenk7aa78612003-05-03 15:50:43 +0000323# endif
324#endif /* CONFIG_MPC8255 */
wdenk0f8c9762002-08-19 11:57:05 +0000325
326/* no slaves so just fill with zeros */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200327#define CONFIG_SYS_HRCW_SLAVE1 0
328#define CONFIG_SYS_HRCW_SLAVE2 0
329#define CONFIG_SYS_HRCW_SLAVE3 0
330#define CONFIG_SYS_HRCW_SLAVE4 0
331#define CONFIG_SYS_HRCW_SLAVE5 0
332#define CONFIG_SYS_HRCW_SLAVE6 0
333#define CONFIG_SYS_HRCW_SLAVE7 0
wdenk0f8c9762002-08-19 11:57:05 +0000334
335/*-----------------------------------------------------------------------
336 * Internal Memory Mapped Register
337 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200338#define CONFIG_SYS_IMMR 0xFFF00000
wdenk0f8c9762002-08-19 11:57:05 +0000339
340/*-----------------------------------------------------------------------
341 * Definitions for initial stack pointer and data area (in DPRAM)
342 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200343#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
Wolfgang Denk553f0982010-10-26 13:32:32 +0200344#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in DPRAM */
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200345#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200346#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenk0f8c9762002-08-19 11:57:05 +0000347
348/*-----------------------------------------------------------------------
349 * Start addresses for the final memory configuration
350 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200351 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenk0f8c9762002-08-19 11:57:05 +0000352 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200353 * 60x SDRAM is mapped at CONFIG_SYS_SDRAM_BASE, local SDRAM
wdenk0f8c9762002-08-19 11:57:05 +0000354 * is mapped at SDRAM_BASE2_PRELIM.
355 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200356#define CONFIG_SYS_SDRAM_BASE 0x00000000
357#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH0_BASE
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200358#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200359#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
Wolfgang Denk055b12f2008-10-19 21:54:30 +0200360#define CONFIG_SYS_MALLOC_LEN (512 << 10) /* Reserve 512 kB for malloc()*/
wdenk0f8c9762002-08-19 11:57:05 +0000361
wdenk0f8c9762002-08-19 11:57:05 +0000362/*-----------------------------------------------------------------------
363 * Cache Configuration
364 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200365#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */
Jon Loeliger26946902007-07-04 22:30:50 -0500366#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200367# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
wdenk0f8c9762002-08-19 11:57:05 +0000368#endif
369
370/*-----------------------------------------------------------------------
371 * HIDx - Hardware Implementation-dependent Registers 2-11
372 *-----------------------------------------------------------------------
373 * HID0 also contains cache control - initially enable both caches and
374 * invalidate contents, then the final state leaves only the instruction
375 * cache enabled. Note that Power-On and Hard reset invalidate the caches,
376 * but Soft reset does not.
377 *
378 * HID1 has only read-only information - nothing to set.
379 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200380#define CONFIG_SYS_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
wdenk8bde7f72003-06-27 21:31:46 +0000381 HID0_IFEM|HID0_ABE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200382#define CONFIG_SYS_HID0_FINAL (HID0_IFEM|HID0_ABE)
383#define CONFIG_SYS_HID2 0
wdenk0f8c9762002-08-19 11:57:05 +0000384
385/*-----------------------------------------------------------------------
386 * RMR - Reset Mode Register 5-5
387 *-----------------------------------------------------------------------
388 * turn on Checkstop Reset Enable
389 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200390#define CONFIG_SYS_RMR RMR_CSRE
wdenk0f8c9762002-08-19 11:57:05 +0000391
392/*-----------------------------------------------------------------------
393 * BCR - Bus Configuration 4-25
394 *-----------------------------------------------------------------------
395 */
396#ifdef CONFIG_BUSMODE_60x
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200397#define CONFIG_SYS_BCR (BCR_EBM|BCR_L2C|BCR_LETM|\
wdenk0f8c9762002-08-19 11:57:05 +0000398 BCR_NPQM0|BCR_NPQM1|BCR_NPQM2) /* 60x mode */
399#else
400#define BCR_APD01 0x10000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200401#define CONFIG_SYS_BCR (BCR_APD01|BCR_ETM|BCR_LETM) /* 8260 mode */
wdenk0f8c9762002-08-19 11:57:05 +0000402#endif
403
404/*-----------------------------------------------------------------------
405 * SIUMCR - SIU Module Configuration 4-31
406 *-----------------------------------------------------------------------
407 */
408#if 0
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200409#define CONFIG_SYS_SIUMCR (SIUMCR_DPPC10|SIUMCR_APPC10)
wdenk0f8c9762002-08-19 11:57:05 +0000410#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200411#define CONFIG_SYS_SIUMCR (SIUMCR_DPPC00|SIUMCR_APPC10)
wdenk0f8c9762002-08-19 11:57:05 +0000412#endif
413
414
415/*-----------------------------------------------------------------------
416 * SYPCR - System Protection Control 4-35
417 * SYPCR can only be written once after reset!
418 *-----------------------------------------------------------------------
419 * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
420 */
421#if defined(CONFIG_WATCHDOG)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200422#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
wdenk8bde7f72003-06-27 21:31:46 +0000423 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
wdenk0f8c9762002-08-19 11:57:05 +0000424#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200425#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
wdenk8bde7f72003-06-27 21:31:46 +0000426 SYPCR_SWRI|SYPCR_SWP)
wdenk0f8c9762002-08-19 11:57:05 +0000427#endif /* CONFIG_WATCHDOG */
428
429/*-----------------------------------------------------------------------
430 * TMCNTSC - Time Counter Status and Control 4-40
431 *-----------------------------------------------------------------------
432 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
433 * and enable Time Counter
434 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200435#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
wdenk0f8c9762002-08-19 11:57:05 +0000436
437/*-----------------------------------------------------------------------
438 * PISCR - Periodic Interrupt Status and Control 4-42
439 *-----------------------------------------------------------------------
440 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
441 * Periodic timer
442 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200443#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
wdenk0f8c9762002-08-19 11:57:05 +0000444
445/*-----------------------------------------------------------------------
446 * SCCR - System Clock Control 9-8
447 *-----------------------------------------------------------------------
448 * Ensure DFBRG is Divide by 16
449 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200450#define CONFIG_SYS_SCCR 0
wdenk0f8c9762002-08-19 11:57:05 +0000451
452/*-----------------------------------------------------------------------
453 * RCCR - RISC Controller Configuration 13-7
454 *-----------------------------------------------------------------------
455 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200456#define CONFIG_SYS_RCCR 0
wdenk0f8c9762002-08-19 11:57:05 +0000457
458/*
459 * Init Memory Controller:
460 *
461 * Bank Bus Machine PortSz Device
462 * ---- --- ------- ------ ------
463 * 0 60x GPCM 64 bit FLASH
464 * 1 60x SDRAM 64 bit SDRAM
465 * 2 Local SDRAM 32 bit SDRAM
466 *
467 */
468
469 /* Initialize SDRAM on local bus
470 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200471#define CONFIG_SYS_INIT_LOCAL_SDRAM
wdenk0f8c9762002-08-19 11:57:05 +0000472
473#define SDRAM_MAX_SIZE 0x08000000 /* max. 128 MB */
474
475/* Minimum mask to separate preliminary
476 * address ranges for CS[0:2]
477 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200478#define CONFIG_SYS_GLOBAL_SDRAM_LIMIT (512<<20) /* less than 512 MB */
479#define CONFIG_SYS_LOCAL_SDRAM_LIMIT (128<<20) /* less than 128 MB */
wdenk0f8c9762002-08-19 11:57:05 +0000480
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200481#define CONFIG_SYS_MPTPR 0x4000
wdenk0f8c9762002-08-19 11:57:05 +0000482
483/*-----------------------------------------------------------------------------
484 * Address for Mode Register Set (MRS) command
485 *-----------------------------------------------------------------------------
486 * In fact, the address is rather configuration data presented to the SDRAM on
487 * its address lines. Because the address lines may be mux'ed externally either
488 * for 8 column or 9 column devices, some bits appear twice in the 8260's
489 * address:
490 *
491 * | (RFU) | (RFU) | WBL | TM | CL | BT | Burst Length |
492 * | BA1 BA0 | A12 : A10 | A9 | A8 A7 | A6 : A4 | A3 | A2 : A0 |
493 * 8 columns mux'ing: | A9 | A10 A21 | A22 : A24 | A25 | A26 : A28 |
494 * 9 columns mux'ing: | A8 | A20 A21 | A22 : A24 | A25 | A26 : A28 |
495 * Settings: | 0 | 0 0 | 0 1 0 | 0 | 0 1 0 |
496 *-----------------------------------------------------------------------------
497 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200498#define CONFIG_SYS_MRS_OFFS 0x00000110
wdenk0f8c9762002-08-19 11:57:05 +0000499
500
501/* Bank 0 - FLASH
502 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200503#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) |\
wdenk8bde7f72003-06-27 21:31:46 +0000504 BRx_PS_64 |\
505 BRx_MS_GPCM_P |\
506 BRx_V)
wdenk0f8c9762002-08-19 11:57:05 +0000507
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200508#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) |\
wdenk8bde7f72003-06-27 21:31:46 +0000509 ORxG_CSNT |\
510 ORxG_ACS_DIV1 |\
511 ORxG_SCY_3_CLK |\
512 ORxG_EHTR |\
513 ORxG_TRLX)
wdenk0f8c9762002-08-19 11:57:05 +0000514
515 /* SDRAM on TQM8260 can have either 8 or 9 columns.
516 * The number affects configuration values.
517 */
518
519/* Bank 1 - 60x bus SDRAM
520 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200521#define CONFIG_SYS_PSRT 0x20
522#define CONFIG_SYS_LSRT 0x20
523#ifndef CONFIG_SYS_RAMBOOT
524#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) |\
wdenk8bde7f72003-06-27 21:31:46 +0000525 BRx_PS_64 |\
526 BRx_MS_SDRAM_P |\
527 BRx_V)
wdenk0f8c9762002-08-19 11:57:05 +0000528
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200529#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR1_8COL
wdenk0f8c9762002-08-19 11:57:05 +0000530
531
532 /* SDRAM initialization values for 8-column chips
533 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200534#define CONFIG_SYS_OR1_8COL ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
wdenk8bde7f72003-06-27 21:31:46 +0000535 ORxS_BPD_4 |\
536 ORxS_ROWST_PBI1_A7 |\
537 ORxS_NUMR_12)
wdenk0f8c9762002-08-19 11:57:05 +0000538
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200539#define CONFIG_SYS_PSDMR_8COL (PSDMR_PBI |\
wdenk8bde7f72003-06-27 21:31:46 +0000540 PSDMR_SDAM_A15_IS_A5 |\
541 PSDMR_BSMA_A12_A14 |\
542 PSDMR_SDA10_PBI1_A8 |\
543 PSDMR_RFRC_7_CLK |\
544 PSDMR_PRETOACT_2W |\
545 PSDMR_ACTTORW_2W |\
546 PSDMR_LDOTOPRE_1C |\
547 PSDMR_WRC_2C |\
548 PSDMR_EAMUX |\
549 PSDMR_CL_2)
wdenk0f8c9762002-08-19 11:57:05 +0000550
551 /* SDRAM initialization values for 9-column chips
552 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200553#define CONFIG_SYS_OR1_9COL ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
wdenk8bde7f72003-06-27 21:31:46 +0000554 ORxS_BPD_4 |\
555 ORxS_ROWST_PBI1_A5 |\
556 ORxS_NUMR_13)
wdenk0f8c9762002-08-19 11:57:05 +0000557
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200558#define CONFIG_SYS_PSDMR_9COL (PSDMR_PBI |\
wdenk8bde7f72003-06-27 21:31:46 +0000559 PSDMR_SDAM_A16_IS_A5 |\
560 PSDMR_BSMA_A12_A14 |\
561 PSDMR_SDA10_PBI1_A7 |\
562 PSDMR_RFRC_7_CLK |\
563 PSDMR_PRETOACT_2W |\
564 PSDMR_ACTTORW_2W |\
565 PSDMR_LDOTOPRE_1C |\
566 PSDMR_WRC_2C |\
567 PSDMR_EAMUX |\
568 PSDMR_CL_2)
wdenk0f8c9762002-08-19 11:57:05 +0000569
570/* Bank 2 - Local bus SDRAM
571 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200572#ifdef CONFIG_SYS_INIT_LOCAL_SDRAM
573#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BRx_BA_MSK) |\
wdenk8bde7f72003-06-27 21:31:46 +0000574 BRx_PS_32 |\
575 BRx_MS_SDRAM_L |\
576 BRx_V)
wdenk0f8c9762002-08-19 11:57:05 +0000577
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200578#define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_OR2_8COL
wdenk0f8c9762002-08-19 11:57:05 +0000579
580#define SDRAM_BASE2_PRELIM 0x80000000
581
582 /* SDRAM initialization values for 8-column chips
583 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200584#define CONFIG_SYS_OR2_8COL ((~(CONFIG_SYS_LOCAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
wdenk8bde7f72003-06-27 21:31:46 +0000585 ORxS_BPD_4 |\
586 ORxS_ROWST_PBI1_A8 |\
587 ORxS_NUMR_12)
wdenk0f8c9762002-08-19 11:57:05 +0000588
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200589#define CONFIG_SYS_LSDMR_8COL (PSDMR_PBI |\
wdenk8bde7f72003-06-27 21:31:46 +0000590 PSDMR_SDAM_A15_IS_A5 |\
591 PSDMR_BSMA_A13_A15 |\
592 PSDMR_SDA10_PBI1_A9 |\
593 PSDMR_RFRC_7_CLK |\
594 PSDMR_PRETOACT_2W |\
595 PSDMR_ACTTORW_2W |\
596 PSDMR_BL |\
597 PSDMR_LDOTOPRE_1C |\
598 PSDMR_WRC_2C |\
599 PSDMR_CL_2)
wdenk0f8c9762002-08-19 11:57:05 +0000600
601 /* SDRAM initialization values for 9-column chips
602 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200603#define CONFIG_SYS_OR2_9COL ((~(CONFIG_SYS_LOCAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
wdenk8bde7f72003-06-27 21:31:46 +0000604 ORxS_BPD_4 |\
605 ORxS_ROWST_PBI1_A6 |\
606 ORxS_NUMR_13)
wdenk0f8c9762002-08-19 11:57:05 +0000607
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200608#define CONFIG_SYS_LSDMR_9COL (PSDMR_PBI |\
wdenk8bde7f72003-06-27 21:31:46 +0000609 PSDMR_SDAM_A16_IS_A5 |\
610 PSDMR_BSMA_A13_A15 |\
611 PSDMR_SDA10_PBI1_A8 |\
612 PSDMR_RFRC_7_CLK |\
613 PSDMR_PRETOACT_2W |\
614 PSDMR_ACTTORW_2W |\
615 PSDMR_BL |\
616 PSDMR_LDOTOPRE_1C |\
617 PSDMR_WRC_2C |\
618 PSDMR_CL_2)
wdenk0f8c9762002-08-19 11:57:05 +0000619
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200620#endif /* CONFIG_SYS_INIT_LOCAL_SDRAM */
wdenk0f8c9762002-08-19 11:57:05 +0000621
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200622#endif /* CONFIG_SYS_RAMBOOT */
wdenk0f8c9762002-08-19 11:57:05 +0000623
624#endif /* __CONFIG_H */