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wdenke2211742002-11-02 23:30:20 +00001/*
2 * (C) Copyright 2001
3 * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
wdenke2211742002-11-02 23:30:20 +00006 */
7
8/*
9 * board/config.h - configuration options, board specific
10 */
11
12#ifndef __CONFIG_H
13#define __CONFIG_H
14
15/*
16 * High Level Configuration Options
17 * (easy to change)
18 */
19
20#define CONFIG_405GP 1 /* This is a PPC405GP CPU */
21#define CONFIG_4xx 1 /* ...member of PPC405 family */
22#define CONFIG_W7O 1 /* ...on a Wave 7 Optics board */
23#define CONFIG_W7OLMG 1 /* ...specifically an LMG */
24
Wolfgang Denk2ae18242010-10-06 09:05:45 +020025#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
26
wdenkc837dcb2004-01-20 23:12:12 +000027#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
28#define CONFIG_MISC_INIT_F 1 /* and misc_init_f() */
Peter Tyser3a8f28d2009-09-16 22:03:07 -050029#define CONFIG_MISC_INIT_R 1 /* and misc_init_r() */
wdenke2211742002-11-02 23:30:20 +000030
31#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
32
33#define CONFIG_BAUDRATE 9600
34#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
35
36#if 1
37#define CONFIG_BOOTCOMMAND "bootvx" /* VxWorks boot command */
38#else
39#define CONFIG_BOOTCOMMAND "bootp" /* autoboot command */
40#endif
41
42#undef CONFIG_BOOTARGS
43
44#define CONFIG_LOADADDR F0080000
45
46#define CONFIG_ETHADDR 00:06:0D:00:00:00 /* Default, overridden at boot */
47#define CONFIG_OVERWRITE_ETHADDR_ONCE
48#define CONFIG_IPADDR 192.168.1.1
49#define CONFIG_NETMASK 255.255.255.0
50#define CONFIG_SERVERIP 192.168.1.2
51
52#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020053#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* disallow baudrate change */
wdenke2211742002-11-02 23:30:20 +000054
Ben Warren96e21f82008-10-27 23:50:15 -070055#define CONFIG_PPC4xx_EMAC
wdenke2211742002-11-02 23:30:20 +000056#define CONFIG_MII 1 /* MII PHY management */
57#define CONFIG_PHY_ADDR 0 /* PHY address */
58
59#define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */
60#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
61#define CONFIG_DTT_SENSORS {2, 4} /* Sensor addresses */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020062#define CONFIG_SYS_DTT_MAX_TEMP 70
63#define CONFIG_SYS_DTT_LOW_TEMP -30
64#define CONFIG_SYS_DTT_HYSTERESIS 3
wdenke2211742002-11-02 23:30:20 +000065
wdenke2211742002-11-02 23:30:20 +000066
Jon Loeligera5562902007-07-08 15:31:57 -050067/*
Jon Loeligera1aa0bb2007-07-10 09:22:23 -050068 * BOOTP options
69 */
70#define CONFIG_BOOTP_BOOTFILESIZE
71#define CONFIG_BOOTP_BOOTPATH
72#define CONFIG_BOOTP_GATEWAY
73#define CONFIG_BOOTP_HOSTNAME
74
75
76/*
Jon Loeligera5562902007-07-08 15:31:57 -050077 * Command line configuration.
78 */
79#include <config_cmd_default.h>
80
81#define CONFIG_CMD_PCI
82#define CONFIG_CMD_IRQ
83#define CONFIG_CMD_ASKENV
84#define CONFIG_CMD_DHCP
85#define CONFIG_CMD_BEDBUG
86#define CONFIG_CMD_DATE
87#define CONFIG_CMD_I2C
88#define CONFIG_CMD_EEPROM
89#define CONFIG_CMD_ELF
90#define CONFIG_CMD_BSP
91#define CONFIG_CMD_REGINFO
92#define CONFIG_CMD_DTT
93
wdenke2211742002-11-02 23:30:20 +000094
95#undef CONFIG_WATCHDOG /* watchdog disabled */
96#define CONFIG_HW_WATCHDOG /* HW Watchdog, board specific */
97
98#define CONFIG_SPD_EEPROM /* SPD EEPROM for SDRAM param. */
wdenkdb2f721f2003-03-06 00:58:30 +000099#define CONFIG_SPDDRAM_SILENT /* No output if spd fails */
wdenke2211742002-11-02 23:30:20 +0000100/*
101 * Miscellaneous configurable options
102 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200103#define CONFIG_SYS_LONGHELP /* undef to save memory */
104#define CONFIG_SYS_PROMPT "Wave7Optics> " /* Monitor Command Prompt */
105#undef CONFIG_SYS_HUSH_PARSER /* No hush parse for U-Boot */
106#ifdef CONFIG_SYS_HUSH_PARSER
wdenke2211742002-11-02 23:30:20 +0000107#endif
Jon Loeligera5562902007-07-08 15:31:57 -0500108#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200109#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenke2211742002-11-02 23:30:20 +0000110#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200111#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenke2211742002-11-02 23:30:20 +0000112#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200113#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
114#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
115#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenke2211742002-11-02 23:30:20 +0000116
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200117#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
118#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
wdenke2211742002-11-02 23:30:20 +0000119
Stefan Roese550650d2010-09-20 16:05:31 +0200120#define CONFIG_CONS_INDEX 1 /* Use UART0 */
121#define CONFIG_SYS_NS16550
122#define CONFIG_SYS_NS16550_SERIAL
123#define CONFIG_SYS_NS16550_REG_SIZE 1
124#define CONFIG_SYS_NS16550_CLK get_serial_clock()
125
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200126#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */
127#define CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
128#define CONFIG_SYS_BASE_BAUD 384000
wdenke2211742002-11-02 23:30:20 +0000129
130
131/* The following table includes the supported baudrates */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200132#define CONFIG_SYS_BAUDRATE_TABLE {9600}
wdenke2211742002-11-02 23:30:20 +0000133
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200134#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
135#define CONFIG_SYS_EXTBDINFO 1 /* use extended board_info (bd_t) */
wdenke2211742002-11-02 23:30:20 +0000136
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200137#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenke2211742002-11-02 23:30:20 +0000138
139/*-----------------------------------------------------------------------
140 * PCI stuff
141 *-----------------------------------------------------------------------
142 */
143#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
144#define PCI_HOST_FORCE 1 /* configure as pci host */
145#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
146
147#define CONFIG_PCI /* include pci support */
Gabor Juhos842033e2013-05-30 07:06:12 +0000148#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
wdenke2211742002-11-02 23:30:20 +0000149#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */
150#define CONFIG_PCI_PNP /* pci plug-and-play */
151/* resource configuration */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200152#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014 /* PCI Vendor ID: IBM */
153#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0156 /* PCI Device ID: 405GP */
154#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */
155#define CONFIG_SYS_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */
156#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
157#define CONFIG_SYS_PCI_PTM2LA 0x00000000 /* disabled */
158#define CONFIG_SYS_PCI_PTM2MS 0x00000000 /* disabled */
159#define CONFIG_SYS_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */
wdenke2211742002-11-02 23:30:20 +0000160
161/*-----------------------------------------------------------------------
162 * Set up values for external bus controller
163 * used by cpu_init.c
164 *-----------------------------------------------------------------------
165 */
166 /* use PerWE instead of PCI_INT ( these functions share a pin ) */
167#define CONFIG_USE_PERWE 1
168
169/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200170#define CONFIG_SYS_TEMP_STACK_OCM 1
wdenke2211742002-11-02 23:30:20 +0000171
172/* bank 0 is boot flash */
173/* BME=0,TWT=6,CSN=1,OEN=1,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=1,PEN=0 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200174#define CONFIG_SYS_W7O_EBC_PB0AP 0x03050440
wdenke2211742002-11-02 23:30:20 +0000175/* BAS=0xFFE,BS=0x1(2MB),BU=0x3(R/W),BW=0x0(8 bits) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200176#define CONFIG_SYS_W7O_EBC_PB0CR 0xFFE38000
wdenke2211742002-11-02 23:30:20 +0000177
178/* bank 1 is main flash */
179/* BME=0,TWT=9,CSN=1,OEN=1,WBN=0,WBF=0,TH=1,RE=0,SOR=0,BEM=1,PEN=0 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200180#define CONFIG_SYS_EBC_PB1AP 0x04850240
wdenke2211742002-11-02 23:30:20 +0000181/* BAS=0xF00,BS=0x7(128MB),BU=0x3(R/W),BW=0x10(32 bits) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200182#define CONFIG_SYS_EBC_PB1CR 0xF00FC000
wdenke2211742002-11-02 23:30:20 +0000183
184/* bank 2 is RTC/NVRAM */
185/* BME=0,TWT=6,CSN=0,OEN=0,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=1,PEN=0 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200186#define CONFIG_SYS_EBC_PB2AP 0x03000440
wdenke2211742002-11-02 23:30:20 +0000187/* BAS=0xFC0,BS=0x0(1MB),BU=0x3(R/W),BW=0x0(8 bits) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200188#define CONFIG_SYS_EBC_PB2CR 0xFC018000
wdenke2211742002-11-02 23:30:20 +0000189
190/* bank 3 is FPGA 0 */
191/* BME=0,TWT=4,CSN=0,OEN=0,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=0,PEN=0 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200192#define CONFIG_SYS_EBC_PB3AP 0x02000400
wdenke2211742002-11-02 23:30:20 +0000193/* BAS=0xFD0,BS=0x0(1MB),BU=0x3(R/W),BW=0x1(16 bits) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200194#define CONFIG_SYS_EBC_PB3CR 0xFD01A000
wdenke2211742002-11-02 23:30:20 +0000195
196/* bank 4 is SAM 8 bit range */
197/* BME=,TWT=,CSN=,OEN=,WBN=,WBF=,TH=,RE=,SOR=,BEM=,PEN= */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200198#define CONFIG_SYS_EBC_PB4AP 0x02840380
wdenke2211742002-11-02 23:30:20 +0000199/* BAS=,BS=,BU=0x3(R/W),BW=0x0(8 bits) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200200#define CONFIG_SYS_EBC_PB4CR 0xFE878000
wdenke2211742002-11-02 23:30:20 +0000201
202/* bank 5 is SAM 16 bit range */
203/* BME=0,TWT=10,CSN=2,OEN=0,WBN=0,WBF=0,TH=6,RE=1,SOR=1,BEM=0,PEN=0 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200204#define CONFIG_SYS_EBC_PB5AP 0x05040d80
wdenke2211742002-11-02 23:30:20 +0000205/* BAS=,BS=,BU=0x3(R/W),BW=0x1(16 bits) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200206#define CONFIG_SYS_EBC_PB5CR 0xFD87A000
wdenke2211742002-11-02 23:30:20 +0000207
208/* bank 6 is unused */
Stefan Roesed1c3b272009-09-09 16:25:29 +0200209/* PB6AP = 0 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200210#define CONFIG_SYS_EBC_PB6AP 0x00000000
Stefan Roesed1c3b272009-09-09 16:25:29 +0200211/* PB6CR = 0 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200212#define CONFIG_SYS_EBC_PB6CR 0x00000000
wdenke2211742002-11-02 23:30:20 +0000213
214/* bank 7 is LED register */
215/* BME=0,TWT=6,CSN=1,OEN=1,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=1,PEN=0 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200216#define CONFIG_SYS_W7O_EBC_PB7AP 0x03050440
wdenke2211742002-11-02 23:30:20 +0000217/* BAS=0xFE0,BS=0x0(1MB),BU=0x3(R/W),BW=0x2(32 bits) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200218#define CONFIG_SYS_W7O_EBC_PB7CR 0xFE01C000
wdenke2211742002-11-02 23:30:20 +0000219
220/*-----------------------------------------------------------------------
221 * Start addresses for the final memory configuration
222 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200223 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenke2211742002-11-02 23:30:20 +0000224 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200225#define CONFIG_SYS_SDRAM_BASE 0x00000000
226#define CONFIG_SYS_FLASH_BASE 0xFFFC0000
227#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
228#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 196 kB for Monitor */
229#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
wdenke2211742002-11-02 23:30:20 +0000230
231/*
232 * For booting Linux, the board info and command line data
233 * have to be in the first 8 MB of memory, since this is
234 * the maximum mapped by the Linux kernel during initialization.
235 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200236#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenke2211742002-11-02 23:30:20 +0000237/*-----------------------------------------------------------------------
238 * FLASH organization
239 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200240#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
241#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sec on 1 chip */
wdenke2211742002-11-02 23:30:20 +0000242
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200243#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout, Flash Erase, in ms */
244#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout, Flash Write, in ms */
245#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use real Flash protection */
wdenke2211742002-11-02 23:30:20 +0000246
247#if 1 /* Use NVRAM for environment variables */
248/*-----------------------------------------------------------------------
249 * NVRAM organization
250 */
Jean-Christophe PLAGNIOL-VILLARD9314cee2008-09-10 22:47:59 +0200251#define CONFIG_ENV_IS_IN_NVRAM 1 /* use NVRAM for env vars */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200252#define CONFIG_SYS_NVRAM_BASE_ADDR 0xfc000000 /* NVRAM base address */
253#define CONFIG_SYS_NVRAM_SIZE (32*1024) /* NVRAM size */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200254#define CONFIG_ENV_SIZE 0x1000 /* Size of Environment vars */
255/*define CONFIG_ENV_ADDR \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200256 (CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-CONFIG_ENV_SIZE) Env */
257#define CONFIG_ENV_ADDR CONFIG_SYS_NVRAM_BASE_ADDR
wdenke2211742002-11-02 23:30:20 +0000258
259#else /* Use Boot Flash for environment variables */
260/*-----------------------------------------------------------------------
261 * Flash EEPROM for environment
262 */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200263#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200264#define CONFIG_ENV_OFFSET 0x00040000 /* Offset of Environment Sector */
265#define CONFIG_ENV_SIZE 0x10000 /* Total Size of env. sector */
wdenke2211742002-11-02 23:30:20 +0000266
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200267#define CONFIG_ENV_SECT_SIZE 0x10000 /* see README - env sec tot sze */
wdenke2211742002-11-02 23:30:20 +0000268#endif
269
270/*-----------------------------------------------------------------------
271 * I2C EEPROM (ATMEL 24C04N)
272 */
Dirk Eibach880540d2013-04-25 02:40:01 +0000273#define CONFIG_SYS_I2C
274#define CONFIG_SYS_I2C_PPC4XX
275#define CONFIG_SYS_I2C_PPC4XX_CH0
276#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
277#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
wdenke2211742002-11-02 23:30:20 +0000278
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200279#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM ATMEL 24C04N */
280#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
281#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
282#define CONFIG_SYS_I2C_MULTI_EEPROMS
wdenke2211742002-11-02 23:30:20 +0000283/*-----------------------------------------------------------------------
284 * Definitions for Serial Presence Detect EEPROM address
285 * (to get SDRAM settings)
286 */
287#define SPD_EEPROM_ADDRESS 0x50 /* XXX conflicting address!!! XXX */
288
wdenke2211742002-11-02 23:30:20 +0000289/*
290 * Init Memory Controller:
291 */
292#define FLASH_BASE0_PRELIM 0xFFE00000 /* FLASH bank #0 */
293#define FLASH_BASE1_PRELIM 0xF0000000 /* FLASH bank #1 */
294
295/* On Chip Memory location */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200296#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
297#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
wdenke2211742002-11-02 23:30:20 +0000298
299/*-----------------------------------------------------------------------
300 * Definitions for initial stack pointer and data area (in RAM)
301 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200302#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200303#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200304#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200305#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenke2211742002-11-02 23:30:20 +0000306
Jon Loeligera5562902007-07-08 15:31:57 -0500307#if defined(CONFIG_CMD_KGDB)
wdenke2211742002-11-02 23:30:20 +0000308#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
309#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
310#endif
311
312/*
313 * FPGA(s) configuration
314 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200315#define CONFIG_SYS_FPGA_IMAGE_LEN 0x80000 /* 512KB FPGA image */
wdenke2211742002-11-02 23:30:20 +0000316#define CONFIG_NUM_FPGAS 1 /* Number of FPGAs on board */
317#define CONFIG_MAX_FPGAS 6 /* Maximum number of FPGAs */
318#define CONFIG_FPGAS_BASE 0xFD000000L /* Base address of FPGAs */
319#define CONFIG_FPGAS_BANK_SIZE 0x00100000L /* FPGAs' mmap bank size */
320
321#endif /* __CONFIG_H */