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Wolfgang Grandeggercd12f612009-10-23 12:03:16 +02001/*
2 * (C) Copyright 2006
3 * MicroSys GmbH
4 *
5 * (C) Copyright 2009
6 * Wolfgang Grandegger, DENX Software Engineering, wg@denx.de.
7 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02008 * SPDX-License-Identifier: GPL-2.0+
Wolfgang Grandeggercd12f612009-10-23 12:03:16 +02009 */
10
11#ifndef __CONFIG_H
12#define __CONFIG_H
13
14/*
15 * High Level Configuration Options
16 */
17
18#define CONFIG_MPC5200
19#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
20#define CONFIG_MPX5200 1 /* ... on MPX5200 board */
21#define CONFIG_MPC5200_DDR 1 /* ... use DDR RAM */
22#define CONFIG_IPEK01 /* Motherboard is ipek01 */
23
Wolfgang Denk2ae18242010-10-06 09:05:45 +020024#define CONFIG_SYS_TEXT_BASE 0xfc000000
25
Wolfgang Grandeggercd12f612009-10-23 12:03:16 +020026#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33MHz */
27
28#define CONFIG_MISC_INIT_R
29
Wolfgang Grandeggercd12f612009-10-23 12:03:16 +020030#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
31#ifdef CONFIG_CMD_KGDB
32#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
33#endif
34
35/*
36 * Serial console configuration
37 */
38#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
39#define CONFIG_BAUDRATE 115200 /* ... at 9600 bps */
40#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
41
42#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
43
44/*
45 * Video configuration for LIME GDC
46 */
47#define CONFIG_VIDEO
48#ifdef CONFIG_VIDEO
49#define CONFIG_VIDEO_MB862xx
50#define CONFIG_VIDEO_MB862xx_ACCEL
51#define VIDEO_FB_16BPP_WORD_SWAP
52#define CONFIG_CFB_CONSOLE
53#define CONFIG_VIDEO_LOGO
54#define CONFIG_VIDEO_BMP_LOGO
55#define CONFIG_CONSOLE_EXTRA_INFO
56#define CONFIG_VGA_AS_SINGLE_DEVICE
57#define CONFIG_SYS_CONSOLE_IS_IN_ENV
58#define CONFIG_VIDEO_SW_CURSOR
59#define CONFIG_SPLASH_SCREEN
60#define CONFIG_VIDEO_BMP_GZIP
61#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20) /* decompressed img */
62/* Lime clock frequency */
63#define CONFIG_SYS_MB862xx_CCF 0x90000 /* geo 166MHz other 133MHz */
64/* SDRAM parameter */
65#define CONFIG_SYS_MB862xx_MMR 0x41c767e3
66#endif
67
68/*
69 * PCI Mapping:
70 * 0x40000000 - 0x4fffffff - PCI Memory
71 * 0x50000000 - 0x50ffffff - PCI IO Space
72 */
73#define CONFIG_PCI 1
74#define CONFIG_PCI_PNP 1
75#define CONFIG_PCI_SCAN_SHOW 1
76
77#define CONFIG_PCI_MEM_BUS 0x40000000
78#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
79#define CONFIG_PCI_MEM_SIZE 0x10000000
80
81#define CONFIG_PCI_IO_BUS 0x50000000
82#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
83#define CONFIG_PCI_IO_SIZE 0x01000000
84
Wolfgang Grandeggercd12f612009-10-23 12:03:16 +020085#define CONFIG_MII 1
86#define CONFIG_EEPRO100 1
87#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
88
89/* Partitions */
90#define CONFIG_DOS_PARTITION
91
92/* USB */
93#define CONFIG_USB_OHCI_NEW
94#define CONFIG_SYS_OHCI_BE_CONTROLLER
95#define CONFIG_USB_STORAGE
96
97#define CONFIG_SYS_USB_OHCI_CPU_INIT
98#define CONFIG_SYS_USB_OHCI_REGS_BASE MPC5XXX_USB
99#define CONFIG_SYS_USB_OHCI_SLOT_NAME "mpc5200"
100#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
101
102/*
103 * Command line configuration.
104 */
105#include <config_cmd_default.h>
106
107#ifdef CONFIG_VIDEO
108#define CONFIG_CMD_BMP /* BMP support */
109#endif
110#define CONFIG_CMD_DATE /* support for RTC, date/time...*/
111#define CONFIG_CMD_DHCP /* DHCP Support */
112#define CONFIG_CMD_FAT /* FAT support */
113#define CONFIG_CMD_I2C /* I2C serial bus support */
114#define CONFIG_CMD_IDE /* IDE harddisk support */
115#define CONFIG_CMD_IRQ /* irqinfo */
116#define CONFIG_CMD_MII /* MII support */
117#define CONFIG_CMD_PCI /* pciinfo */
118#define CONFIG_CMD_USB /* USB Support */
119
120#define CONFIG_SYS_LOWBOOT 1
121
122/*
123 * Autobooting
124 */
125#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
126
127#define CONFIG_PREBOOT "echo;" \
128 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
129 "echo"
130
131#undef CONFIG_BOOTARGS
132
133#define CONFIG_EXTRA_ENV_SETTINGS \
134 "netdev=eth0\0" \
135 "consoledev=ttyPSC0\0" \
136 "hostname=ipek01\0" \
137 "nfsargs=setenv bootargs root=/dev/nfs rw " \
138 "nfsroot=${serverip}:${rootpath}\0" \
139 "ramargs=setenv bootargs root=/dev/ram rw\0" \
140 "addip=setenv bootargs ${bootargs} " \
141 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
142 ":${hostname}:${netdev}:off panic=1\0" \
143 "addtty=setenv bootargs ${bootargs} " \
144 "console=${consoledev},${baudrate}\0" \
145 "flash_nfs=run nfsargs addip addtty;" \
146 "bootm ${kernel_addr} - ${fdtaddr}\0" \
147 "flash_self=run ramargs addip addtty;" \
148 "bootm ${kernel_addr} ${ramdisk_addr} ${fdtaddr}\0" \
149 "net_nfs=tftp 200000 ${bootfile}; tftp ${fdtaddr} ${fdtfile};" \
150 "run nfsargs addip addtty;" \
151 "bootm ${loadaddr} - ${fdtaddr}\0" \
152 "rootpath=/opt/eldk/ppc_6xx\0" \
153 "bootfile=ipek01/uImage\0" \
154 "load=tftp 100000 ipek01/u-boot.bin\0" \
155 "update=protect off FC000000 +60000; era FC000000 +60000; " \
156 "cp.b 100000 FC000000 ${filesize}\0" \
157 "upd=run load;run update\0" \
158 "fdtaddr=800000\0" \
159 "loadaddr=400000\0" \
160 "fdtfile=ipek01/ipek01.dtb\0" \
161 ""
162
163#define CONFIG_BOOTCOMMAND "run flash_self"
164
165/*
166 * IPB Bus clocking configuration.
167 */
168#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* for 133MHz */
169/* PCI clock must be 33, because board will not boot */
170#undef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 /* for 66MHz */
171
172/*
173 * Open firmware flat tree support
174 */
175#define CONFIG_OF_LIBFDT 1
176#define CONFIG_OF_BOARD_SETUP 1
177
178#define OF_CPU "PowerPC,5200@0"
179#define OF_SOC "soc5200@f0000000"
180#define OF_TBCLK (bd->bi_busfreq / 4)
181
182/*
183 * I2C configuration
184 */
185#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
186#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */
187
188#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
189#define CONFIG_SYS_I2C_SLAVE 0x7F
190
191/*
192 * EEPROM configuration
193 */
194#define CONFIG_SYS_I2C_EEPROM_ADDR 0x53
195#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
196#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6
197#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
198
199/*
200 * RTC configuration
201 */
202#define CONFIG_RTC_PCF8563
203#define CONFIG_SYS_I2C_RTC_ADDR 0x51
204
205#define CONFIG_SYS_FLASH_BASE 0xFC000000
206#define CONFIG_SYS_FLASH_SIZE 0x01000000
207#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + \
208 CONFIG_SYS_MONITOR_LEN)
209
210#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
211#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max num of sects on one chip */
212#define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
213
214/* use CFI flash driver */
215#define CONFIG_FLASH_CFI_DRIVER
216#define CONFIG_SYS_FLASH_CFI
217#define CONFIG_SYS_FLASH_EMPTY_INFO
218#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
219
220/*
221 * Environment settings
222 */
223#define CONFIG_ENV_IS_IN_FLASH 1
224#define CONFIG_ENV_SIZE 0x10000
225#define CONFIG_ENV_SECT_SIZE 0x20000
226#define CONFIG_ENV_OVERWRITE 1
227#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
228#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
229
230/*
231 * Memory map
232 */
233#define CONFIG_SYS_MBAR 0xf0000000
234#define CONFIG_SYS_SDRAM_BASE 0x00000000
235#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
236#define CONFIG_SYS_SRAM_BASE 0xF1000000
237#define CONFIG_SYS_SRAM_SIZE 0x00200000
238#define CONFIG_SYS_LIME_BASE 0xE4000000
239#define CONFIG_SYS_LIME_SIZE 0x04000000
240#define CONFIG_SYS_FPGA_BASE 0xC0000000
241#define CONFIG_SYS_FPGA_SIZE 0x10000000
242#define CONFIG_SYS_MPEG_BASE 0xe2000000
243#define CONFIG_SYS_MPEG_SIZE 0x01000000
244#define CONFIG_SYS_CF_BASE 0xe1000000
245#define CONFIG_SYS_CF_SIZE 0x01000000
246
247/* Use SRAM until RAM will be available */
248#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
249/* End of used area in DPRAM */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200250#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE
Wolfgang Grandeggercd12f612009-10-23 12:03:16 +0200251
Wolfgang Denk553f0982010-10-26 13:32:32 +0200252#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200253 GENERATED_GBL_DATA_SIZE)
Wolfgang Grandeggercd12f612009-10-23 12:03:16 +0200254#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
255
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200256#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
Wolfgang Grandeggercd12f612009-10-23 12:03:16 +0200257#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
258# define CONFIG_SYS_RAMBOOT 1
259#endif
260
261#define CONFIG_SYS_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */
262#define CONFIG_SYS_MALLOC_LEN (4 << 20) /* Reserve 128 kB for malloc() */
263#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
264
265/*
266 * Ethernet configuration
267 */
268#define CONFIG_MPC5xxx_FEC 1
269#define CONFIG_MPC5xxx_FEC_MII100
270#define CONFIG_PHY_ADDR 0x00
271
272/*
273 * GPIO configuration
274 */
275#define CONFIG_SYS_GPS_PORT_CONFIG 0x1d556624
276
277/*
278 * Miscellaneous configurable options
279 */
280#define CONFIG_SYS_LONGHELP /* undef to save memory */
281#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
282#ifdef CONFIG_CMD_KGDB
283#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
284#else
285#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
286#endif
287/* Print Buffer Size */
288#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
289 sizeof(CONFIG_SYS_PROMPT) + 16)
290/* max number of command args */
291#define CONFIG_SYS_MAXARGS 16
292/* Boot Argument Buffer Size */
293#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
294
Wolfgang Grandeggercd12f612009-10-23 12:03:16 +0200295#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
296#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1...15 MB in DRAM */
297
298#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
299
300#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
301#define CONFIG_LOOPW
302
303/*
304 * Various low-level settings
305 */
Wolfgang Grandeggercd12f612009-10-23 12:03:16 +0200306#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
307#define CONFIG_SYS_HID0_FINAL HID0_ICE
Wolfgang Grandeggercd12f612009-10-23 12:03:16 +0200308
309#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
310#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
311#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
312#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
313#define CONFIG_SYS_CS1_START CONFIG_SYS_SRAM_BASE
314#define CONFIG_SYS_CS1_SIZE CONFIG_SYS_SRAM_SIZE
315#define CONFIG_SYS_CS3_START CONFIG_SYS_LIME_BASE
316#define CONFIG_SYS_CS3_SIZE CONFIG_SYS_LIME_SIZE
317#define CONFIG_SYS_CS6_START CONFIG_SYS_FPGA_BASE
318#define CONFIG_SYS_CS6_SIZE CONFIG_SYS_FPGA_SIZE
319#define CONFIG_SYS_CS5_START CONFIG_SYS_CF_BASE
320#define CONFIG_SYS_CS5_SIZE CONFIG_SYS_CF_SIZE
321#define CONFIG_SYS_CS7_START CONFIG_SYS_MPEG_BASE
322#define CONFIG_SYS_CS7_SIZE CONFIG_SYS_MPEG_SIZE
323
324#ifdef CONFIG_SYS_PCISPEED_66
325#define CONFIG_SYS_BOOTCS_CFG 0x0006F900
326#define CONFIG_SYS_CS1_CFG 0x0004FB00
327#define CONFIG_SYS_CS2_CFG 0x0006F900
328#else
329#define CONFIG_SYS_BOOTCS_CFG 0x0002F900
330#define CONFIG_SYS_CS1_CFG 0x0001FB00
331#define CONFIG_SYS_CS2_CFG 0x0002F90C
332#endif
333
334/*
335 * Ack active, Muxed mode, AS=24 bit address, DS=32 bit data, 0
336 * waitstates, writeswap and readswap enabled
337 */
338#define CONFIG_SYS_CS3_CFG 0x00FFFB0C
339#define CONFIG_SYS_CS6_CFG 0x00FFFB0C
340#define CONFIG_SYS_CS7_CFG 0x4040751C
341
342#define CONFIG_SYS_CS_BURST 0x00000000
343#define CONFIG_SYS_CS_DEADCYCLE 0x33330000
344
345#define CONFIG_SYS_RESET_ADDRESS 0xff000000
346
347/*-----------------------------------------------------------------------
348 * USB stuff
349 *-----------------------------------------------------------------------
350 */
351#define CONFIG_USB_CLOCK 0x0001BBBB
352#define CONFIG_USB_CONFIG 0x00005000
353
354/*-----------------------------------------------------------------------
355 * IDE/ATA stuff Supports IDE harddisk
356 *-----------------------------------------------------------------------
357 */
358#define CONFIG_IDE_PREINIT
359
360#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
361#define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */
362
363#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
364
365#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
366
367/* Offset for data I/O */
368#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
369
370/* Offset for normal register accesses */
371#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
372
373/* Offset for alternate registers */
374#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
375
376/* Interval between registers */
377#define CONFIG_SYS_ATA_STRIDE 4
378
379#endif /* __CONFIG_H */