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Stefan Roese1eac2a72006-11-29 15:42:37 +01001/*
2 * (C) Copyright 2006
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
5 * Based on original work by
6 * Roel Loeffen, (C) Copyright 2006 Prodrive B.V.
7 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02008 * SPDX-License-Identifier: GPL-2.0+
Stefan Roese1eac2a72006-11-29 15:42:37 +01009 */
10
11/************************************************************************
12 * p3mx.h - configuration for Prodrive P3M750 & P3M7448 boards
13 *
14 * The defines:
15 * CONFIG_P3M750 or
16 * CONFIG_P3M7448
17 * are written into include/config.h by the "make xxx_config" command
18 ***********************************************************************/
19#ifndef __CONFIG_H
20#define __CONFIG_H
21
22/*-----------------------------------------------------------------------
23 * High Level Configuration Options
24 *----------------------------------------------------------------------*/
25#define CONFIG_P3Mx /* used for both board versions */
26
Wolfgang Denk2ae18242010-10-06 09:05:45 +020027#define CONFIG_SYS_TEXT_BASE 0xfff00000
28
Stefan Roese1eac2a72006-11-29 15:42:37 +010029#if defined (CONFIG_P3M750)
30#define CONFIG_750FX /* 750GL/GX/FX */
Becky Bruce31d82672008-05-08 19:02:12 -050031#define CONFIG_HIGH_BATS /* High BATs supported */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020032#define CONFIG_SYS_BOARD_NAME "P3M750"
Wolfgang Denkee80fa72010-06-13 18:38:23 +020033#define CONFIG_SYS_BUS_CLK 100000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020034#define CONFIG_SYS_TCLK 100000000
Stefan Roese1eac2a72006-11-29 15:42:37 +010035#elif defined (CONFIG_P3M7448)
36#define CONFIG_74xx
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020037#define CONFIG_SYS_BOARD_NAME "P3M7448"
Wolfgang Denkee80fa72010-06-13 18:38:23 +020038#define CONFIG_SYS_BUS_CLK 133333333
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020039#define CONFIG_SYS_TCLK 133333333
Stefan Roese1eac2a72006-11-29 15:42:37 +010040#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020041#define CONFIG_SYS_GT_DUAL_CPU /* also for JTAG even with one cpu */
Stefan Roese1eac2a72006-11-29 15:42:37 +010042
43/* which initialization functions to call for this board */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020044#define CONFIG_SYS_BOARD_ASM_INIT 1
Stefan Roese1eac2a72006-11-29 15:42:37 +010045#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
Stefan Roese1eac2a72006-11-29 15:42:37 +010046#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r() */
Stefan Roese1eac2a72006-11-29 15:42:37 +010047
48/*-----------------------------------------------------------------------
49 * Base addresses -- Note these are effective addresses where the
50 * actual resources get mapped (not physical addresses)
51 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020052#define CONFIG_SYS_SDRAM_BASE 0x00000000
Stefan Roese1eac2a72006-11-29 15:42:37 +010053#ifdef CONFIG_P3M750
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020054#define CONFIG_SYS_SDRAM1_BASE 0x10000000 /* each 256 MByte */
Stefan Roese1eac2a72006-11-29 15:42:37 +010055#endif
56
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020057#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
Stefan Roese1eac2a72006-11-29 15:42:37 +010058#if defined (CONFIG_P3M750)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020059#define CONFIG_SYS_FLASH_BASE 0xff800000 /* start of flash banks */
60#define CONFIG_SYS_BOOT_SIZE _8M /* boot flash */
Stefan Roese1eac2a72006-11-29 15:42:37 +010061#elif defined (CONFIG_P3M7448)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020062#define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of flash banks */
63#define CONFIG_SYS_BOOT_SIZE _16M /* boot flash */
Stefan Roese1eac2a72006-11-29 15:42:37 +010064#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020065#define CONFIG_SYS_BOOT_SPACE CONFIG_SYS_FLASH_BASE /* BOOT_CS0 flash 0 */
66#define CONFIG_SYS_MONITOR_BASE 0xfff00000
67#define CONFIG_SYS_RESET_ADDRESS 0xfff00100
68#define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc */
69#define CONFIG_SYS_MISC_REGION_BASE 0xf0000000
Stefan Roese1eac2a72006-11-29 15:42:37 +010070
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020071#define CONFIG_SYS_DFL_GT_REGS 0xf1000000 /* boot time GT_REGS */
72#define CONFIG_SYS_GT_REGS 0xf1000000 /* GT Registers are mapped here */
73#define CONFIG_SYS_INT_SRAM_BASE 0x42000000 /* GT offers 256k internal SRAM */
Stefan Roese1eac2a72006-11-29 15:42:37 +010074
75/*-----------------------------------------------------------------------
76 * Initial RAM & stack pointer (placed in internal SRAM)
77 *----------------------------------------------------------------------*/
78 /*
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020079 * When locking data in cache you should point the CONFIG_SYS_INIT_RAM_ADDRESS
Stefan Roese1eac2a72006-11-29 15:42:37 +010080 * To an unused memory region. The stack will remain in cache until RAM
81 * is initialized
82*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020083#undef CONFIG_SYS_INIT_RAM_LOCK
84#define CONFIG_SYS_INIT_RAM_ADDR 0x42000000
Wolfgang Denk553f0982010-10-26 13:32:32 +020085#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +020086#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Stefan Roese1eac2a72006-11-29 15:42:37 +010087
88
89/*-----------------------------------------------------------------------
90 * Serial Port
91 *----------------------------------------------------------------------*/
92#define CONFIG_MPSC /* MV64460 Serial */
93#define CONFIG_MPSC_PORT 0
94#define CONFIG_BAUDRATE 115200 /* console baudrate */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020095#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
Stefan Roese1eac2a72006-11-29 15:42:37 +010096#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020097#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
Stefan Roese1eac2a72006-11-29 15:42:37 +010098
99/*-----------------------------------------------------------------------
100 * Ethernet
101 *----------------------------------------------------------------------*/
102/* Change the default ethernet port, use this define (options: 0, 1, 2) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200103#define CONFIG_SYS_ETH_PORT ETH_0
Stefan Roese1eac2a72006-11-29 15:42:37 +0100104#define MV_ETH_DEVS 2
105#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
106#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
107
108/*-----------------------------------------------------------------------
109 * FLASH related
110 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200111#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200112#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200113#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
114#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
115#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
116#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
117#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
118#define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware flash protection */
119#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
Stefan Roese1eac2a72006-11-29 15:42:37 +0100120
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200121#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
Stefan Roese1eac2a72006-11-29 15:42:37 +0100122#if defined (CONFIG_P3M750)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200123#define CONFIG_ENV_SECT_SIZE 0x20000 /* one sector (1 device) */
Stefan Roese1eac2a72006-11-29 15:42:37 +0100124#elif defined (CONFIG_P3M7448)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200125#define CONFIG_ENV_SECT_SIZE 0x40000 /* two sectors (2 devices parallel */
Stefan Roese1eac2a72006-11-29 15:42:37 +0100126#endif
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200127#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200128#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
Stefan Roese1eac2a72006-11-29 15:42:37 +0100129
130/*-----------------------------------------------------------------------
131 * DDR SDRAM
132 *----------------------------------------------------------------------*/
133#define CONFIG_MV64460_ECC
134
135/*-----------------------------------------------------------------------
136 * I2C
137 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200138#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed default */
Stefan Roese1eac2a72006-11-29 15:42:37 +0100139
140/* I2C RTC */
141#define CONFIG_RTC_M41T11 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200142#define CONFIG_SYS_I2C_RTC_ADDR 0x68
143#define CONFIG_SYS_M41T11_BASE_YEAR 1900 /* play along with linux */
Stefan Roese1eac2a72006-11-29 15:42:37 +0100144
145/*-----------------------------------------------------------------------
146 * PCI stuff
147 *----------------------------------------------------------------------*/
148#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
149#define PCI_HOST_FORCE 1 /* configure as pci host */
150#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
151
Stefan Roese0057d752007-01-18 11:54:52 +0100152#undef CONFIG_PCI /* include pci support */
153#ifdef CONFIG_PCI
Stefan Roese1eac2a72006-11-29 15:42:37 +0100154#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
155#define CONFIG_PCI_PNP /* do pci plug-and-play */
156#define CONFIG_PCI_SCAN_SHOW /* show devices on bus */
Stefan Roese0057d752007-01-18 11:54:52 +0100157#endif /* CONFIG_PCI */
Stefan Roese1eac2a72006-11-29 15:42:37 +0100158
159/* PCI MEMORY MAP section */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200160#define CONFIG_SYS_PCI0_MEM_BASE 0x80000000
161#define CONFIG_SYS_PCI0_MEM_SIZE _128M
162#define CONFIG_SYS_PCI1_MEM_BASE 0x88000000
163#define CONFIG_SYS_PCI1_MEM_SIZE _128M
Stefan Roese1eac2a72006-11-29 15:42:37 +0100164
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200165#define CONFIG_SYS_PCI0_0_MEM_SPACE (CONFIG_SYS_PCI0_MEM_BASE)
166#define CONFIG_SYS_PCI1_0_MEM_SPACE (CONFIG_SYS_PCI1_MEM_BASE)
Stefan Roese1eac2a72006-11-29 15:42:37 +0100167
168/* PCI I/O MAP section */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200169#define CONFIG_SYS_PCI0_IO_BASE 0xfa000000
170#define CONFIG_SYS_PCI0_IO_SIZE _16M
171#define CONFIG_SYS_PCI1_IO_BASE 0xfb000000
172#define CONFIG_SYS_PCI1_IO_SIZE _16M
Stefan Roese1eac2a72006-11-29 15:42:37 +0100173
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200174#define CONFIG_SYS_PCI0_IO_SPACE (CONFIG_SYS_PCI0_IO_BASE)
175#define CONFIG_SYS_PCI0_IO_SPACE_PCI 0x00000000
176#define CONFIG_SYS_PCI1_IO_SPACE (CONFIG_SYS_PCI1_IO_BASE)
177#define CONFIG_SYS_PCI1_IO_SPACE_PCI 0x00000000
Stefan Roese1eac2a72006-11-29 15:42:37 +0100178
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200179#define CONFIG_SYS_ISA_IO_BASE_ADDRESS (CONFIG_SYS_PCI0_IO_BASE)
180#define CONFIG_SYS_PCI_IDSEL 0x30
Stefan Roese1eac2a72006-11-29 15:42:37 +0100181
182#undef CONFIG_BOOTARGS
183#define CONFIG_EXTRA_ENV_SETTINGS_COMMON \
184 "netdev=eth0\0" \
185 "nfsargs=setenv bootargs root=/dev/nfs rw " \
186 "nfsroot=${serverip}:${rootpath}\0" \
187 "ramargs=setenv bootargs root=/dev/ram rw\0" \
188 "addip=setenv bootargs ${bootargs} " \
189 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
190 ":${hostname}:${netdev}:off panic=1\0" \
191 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
192 "flash_nfs=run nfsargs addip addtty;" \
193 "bootm ${kernel_addr}\0" \
194 "flash_self=run ramargs addip addtty;" \
195 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
196 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
197 "bootm\0" \
198 "rootpath=/opt/eldk/ppc_6xx\0" \
199 "u-boot=p3mx/u-boot/u-boot.bin\0" \
200 "load=tftp 100000 ${u-boot}\0" \
201 "update=protect off fff00000 fff3ffff;era fff00000 fff3ffff;" \
202 "cp.b 100000 fff00000 40000;" \
203 "setenv filesize;saveenv\0" \
Detlev Zundeld8ab58b2008-03-06 16:45:53 +0100204 "upd=run load update\0" \
Stefan Roese1eac2a72006-11-29 15:42:37 +0100205 "serverip=11.0.0.152\0"
206
207#if defined (CONFIG_P3M750)
208#define CONFIG_EXTRA_ENV_SETTINGS \
209 CONFIG_EXTRA_ENV_SETTINGS_COMMON \
210 "hostname=p3m750\0" \
211 "bootfile=/tftpboot/p3mx/vxWorks.st\0" \
212 "kernel_addr=fc000000\0" \
213 "ramdisk_addr=fc180000\0" \
214 "vxfile=p3m750/vxWorks\0" \
215 "vxuser=ddg\0" \
216 "vxpass=ddg\0" \
217 "vxtarget=target\0" \
218 "vxflags=0x8\0" \
219 "vxargs=setenv bootargs mgi(0,0)host:${vxfile} h=${serverip} " \
220 "e=${ipaddr} u=${vxuser} pw=${vxpass} tn=${vxtarget} " \
221 "f=${vxflags}\0"
222#elif defined (CONFIG_P3M7448)
223#define CONFIG_EXTRA_ENV_SETTINGS \
224 CONFIG_EXTRA_ENV_SETTINGS_COMMON \
225 "hostname=p3m7448\0"
226#endif
227
228#if defined (CONFIG_P3M750)
229#define CONFIG_BOOTCOMMAND "tftp;run vxargs;bootvx"
230#elif defined (CONFIG_P3M7448)
231#define CONFIG_BOOTCOMMAND " "
232#endif
233
234#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */
Jon Loeligerd3b8c1a2007-07-09 21:57:31 -0500235
236/*
237 * BOOTP options
238 */
239#define CONFIG_BOOTP_SUBNETMASK
240#define CONFIG_BOOTP_GATEWAY
241#define CONFIG_BOOTP_HOSTNAME
242#define CONFIG_BOOTP_BOOTPATH
243#define CONFIG_BOOTP_BOOTFILESIZE
Stefan Roese1eac2a72006-11-29 15:42:37 +0100244
Jon Loeliger26a34562007-07-04 22:33:17 -0500245/*
246 * Command line configuration.
247 */
248#include <config_cmd_default.h>
249
250#define CONFIG_CMD_ASKENV
251#define CONFIG_CMD_DATE
252#define CONFIG_CMD_DIAG
253#define CONFIG_CMD_ELF
254#define CONFIG_CMD_I2C
255#define CONFIG_CMD_IRQ
256#define CONFIG_CMD_MII
257#define CONFIG_CMD_NET
258#define CONFIG_CMD_NFS
259#define CONFIG_CMD_PING
260#define CONFIG_CMD_REGINFO
261#define CONFIG_CMD_PCI
262#define CONFIG_CMD_CACHE
263#define CONFIG_CMD_SDRAM
264
Stefan Roese1eac2a72006-11-29 15:42:37 +0100265
266/*-----------------------------------------------------------------------
267 * Miscellaneous configurable options
268 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200269#define CONFIG_SYS_HUSH_PARSER
Stefan Roese1eac2a72006-11-29 15:42:37 +0100270
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200271#define CONFIG_SYS_LONGHELP /* undef to save memory */
272#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeliger26a34562007-07-04 22:33:17 -0500273#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200274#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Stefan Roese1eac2a72006-11-29 15:42:37 +0100275#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200276#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Stefan Roese1eac2a72006-11-29 15:42:37 +0100277#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200278#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
279#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
280#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
Stefan Roese1eac2a72006-11-29 15:42:37 +0100281
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200282#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
283#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
Stefan Roese1eac2a72006-11-29 15:42:37 +0100284
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200285#define CONFIG_SYS_LOAD_ADDR 0x08000000 /* default load address */
Stefan Roese1eac2a72006-11-29 15:42:37 +0100286
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200287#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
Stefan Roese1eac2a72006-11-29 15:42:37 +0100288
289#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
290#define CONFIG_LOOPW 1 /* enable loopw command */
291#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
292#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
293#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
294
295/*-----------------------------------------------------------------------
296 * Marvell MV64460 config settings
297 *----------------------------------------------------------------------*/
298/* Reset values for Port behavior (8bit/ 32bit, etc.) only corrected device width */
299#if defined (CONFIG_P3M750)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200300#define CONFIG_SYS_BOOT_PAR 0x8FDFF87F /* 16 bit flash, disable burst*/
Stefan Roese1eac2a72006-11-29 15:42:37 +0100301#elif defined (CONFIG_P3M7448)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200302#define CONFIG_SYS_BOOT_PAR 0x8FEFFFFF /* 32 bit flash, burst enabled */
Stefan Roese1eac2a72006-11-29 15:42:37 +0100303#endif
304
305/*
306 * MPP[0] Serial Port 0 TxD TxD OUT Connected to P14 (buffered)
307 * MPP[1] Serial Port 0 RxD RxD IN Connected to P14 (buffered)
308 * MPP[2] NC
309 * MPP[3] Serial Port 1 TxD TxD OUT Connected to P14 (buffered)
310 * MPP[4] PCI Monarch# GPIO IN Connected to P12
311 * MPP[5] Serial Port 1 RxD RxD IN Connected to P14 (buffered)
312 * MPP[6] PMC Carrier Interrupt 0 Int IN Connected to P14
313 * MPP[7] PMC Carrier Interrupt 1 Int IN Connected to P14
314 * MPP[8] Reserved Do not use
315 * MPP[9] Reserved Do not use
316 * MPP[10] Reserved Do not use
317 * MPP[11] Reserved Do not use
318 * MPP[12] Phy 0 Interrupt Int IN
319 * MPP[13] Phy 1 Interrupt Int IN
320 * MPP[14] NC
321 * MPP[15] NC
322 * MPP[16] PCI Interrupt C Int IN Connected to P11
323 * MPP[17] PCI Interrupt D Int IN Connected to P11
324 * MPP[18] Watchdog NMI# GPIO IN Connected to MPP[24]
325 * MPP[19] Watchdog Expired# WDE OUT Connected to rst logic
326 * MPP[20] Watchdog Status WD_STS IN Read back of rst by watchdog
327 * MPP[21] NC
328 * MPP[22] GP LED Green GPIO OUT
329 * MPP[23] GP LED Red GPIO OUT
330 * MPP[24] Watchdog NMI# Int OUT
331 * MPP[25] NC
332 * MPP[26] NC
333 * MPP[27] PCI Interrupt A Int IN Connected to P11
334 * MPP[28] NC
335 * MPP[29] PCI Interrupt B Int IN Connected to P11
336 * MPP[30] Module reset GPIO OUT Board reset
337 * MPP[31] PCI EReady GPIO IN Connected to P12
338 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200339#define CONFIG_SYS_MPP_CONTROL_0 0x00303022
340#define CONFIG_SYS_MPP_CONTROL_1 0x00000000
341#define CONFIG_SYS_MPP_CONTROL_2 0x00004000
342#define CONFIG_SYS_MPP_CONTROL_3 0x00000004
343#define CONFIG_SYS_GPP_LEVEL_CONTROL 0x280730D0
Stefan Roese1eac2a72006-11-29 15:42:37 +0100344
345/*----------------------------------------------------------------------
346 * Initial BAT mappings
347 */
348
349/* NOTES:
350 * 1) GUARDED and WRITE_THRU not allowed in IBATS
351 * 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT
352 */
353/* SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200354#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
355#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
356#define CONFIG_SYS_DBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_GUARDEDSTORAGE | BATL_CACHEINHIBIT)
357#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
Stefan Roese1eac2a72006-11-29 15:42:37 +0100358
359/* init ram */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200360#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
361#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_256K | BATU_VS | BATU_VP)
362#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
363#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
Stefan Roese1eac2a72006-11-29 15:42:37 +0100364
365/* PCI0, PCI1 in one BAT */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200366#define CONFIG_SYS_IBAT2L BATL_NO_ACCESS
367#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
368#define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
369#define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
Stefan Roese1eac2a72006-11-29 15:42:37 +0100370
371/* GT regs, bootrom, all the devices, PCI I/O */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200372#define CONFIG_SYS_IBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW)
373#define CONFIG_SYS_IBAT3U (CONFIG_SYS_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M)
374#define CONFIG_SYS_DBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
375#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
Stefan Roese1eac2a72006-11-29 15:42:37 +0100376
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200377#define CONFIG_SYS_IBAT4L (CONFIG_SYS_SDRAM1_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
378#define CONFIG_SYS_IBAT4U (CONFIG_SYS_SDRAM1_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
379#define CONFIG_SYS_DBAT4L (CONFIG_SYS_SDRAM1_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
380#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
Stefan Roese1eac2a72006-11-29 15:42:37 +0100381
382/* set rest out of range for Linux !!!!!!!!!!! */
383
384/* IBAT5 and DBAT5 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200385#define CONFIG_SYS_IBAT5L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT)
386#define CONFIG_SYS_IBAT5U (0x20000000 | BATU_BL_256M | BATU_VS | BATU_VP)
387#define CONFIG_SYS_DBAT5L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
388#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
Stefan Roese1eac2a72006-11-29 15:42:37 +0100389
390/* IBAT6 and DBAT6 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200391#define CONFIG_SYS_IBAT6L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT)
392#define CONFIG_SYS_IBAT6U (0x20000000 | BATU_BL_256M | BATU_VS | BATU_VP)
393#define CONFIG_SYS_DBAT6L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
394#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
Stefan Roese1eac2a72006-11-29 15:42:37 +0100395
396/* IBAT7 and DBAT7 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200397#define CONFIG_SYS_IBAT7L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT)
398#define CONFIG_SYS_IBAT7U (0x20000000 | BATU_BL_256M | BATU_VS | BATU_VP)
399#define CONFIG_SYS_DBAT7L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
400#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
Stefan Roese1eac2a72006-11-29 15:42:37 +0100401
402/*
403 * For booting Linux, the board info and command line data
404 * have to be in the first 8 MB of memory, since this is
405 * the maximum mapped by the Linux kernel during initialization.
406 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200407#define CONFIG_SYS_BOOTMAPSZ (8<<20) /* Initial Memory map for Linux */
408#define CONFIG_SYS_VXWORKS_MAC_PTR 0x42010000 /* use some memory in SRAM that's not used!!! */
Stefan Roese1eac2a72006-11-29 15:42:37 +0100409
410/*-----------------------------------------------------------------------
411 * Cache Configuration
412 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200413#define CONFIG_SYS_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */
Jon Loeliger26a34562007-07-04 22:33:17 -0500414#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200415#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
Stefan Roese1eac2a72006-11-29 15:42:37 +0100416#endif
417
418/*-----------------------------------------------------------------------
419 * L2CR setup -- make sure this is right for your board!
420 * look in include/mpc74xx.h for the defines used here
421 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200422#define CONFIG_SYS_L2
Stefan Roese1eac2a72006-11-29 15:42:37 +0100423
424#if defined (CONFIG_750CX) || defined (CONFIG_750FX)
425#define L2_INIT 0
426#else
427#define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
428 L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT)
429#endif
430
431#define L2_ENABLE (L2_INIT | L2CR_L2E)
432
Marek Vasut0aa27652011-10-21 14:17:33 +0000433#ifndef __ASSEMBLY__
434#include <../board/Marvell/include/core.h>
435#endif
436
Stefan Roese1eac2a72006-11-29 15:42:37 +0100437#endif /* __CONFIG_H */