Tom Rini | 83d290c | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
Rob Herring | 37fc0ed | 2011-10-24 08:50:20 +0000 | [diff] [blame] | 2 | /* |
| 3 | * Copyright 2010-2011 Calxeda, Inc. |
Rob Herring | 37fc0ed | 2011-10-24 08:50:20 +0000 | [diff] [blame] | 4 | */ |
| 5 | |
| 6 | #ifndef __CONFIG_H |
| 7 | #define __CONFIG_H |
| 8 | |
Rob Herring | 37fc0ed | 2011-10-24 08:50:20 +0000 | [diff] [blame] | 9 | #define CONFIG_SYS_BOOTMAPSZ (16 << 20) |
| 10 | |
Rob Herring | 9df1bd4 | 2013-10-04 10:22:43 -0500 | [diff] [blame] | 11 | #define CONFIG_SYS_TIMER_RATE (150000000/256) |
| 12 | #define CONFIG_SYS_TIMER_COUNTER (0xFFF34000 + 0x4) |
| 13 | #define CONFIG_SYS_TIMER_COUNTS_DOWN |
| 14 | |
Rob Herring | 37fc0ed | 2011-10-24 08:50:20 +0000 | [diff] [blame] | 15 | /* |
| 16 | * Size of malloc() pool |
| 17 | */ |
| 18 | #define CONFIG_SYS_MALLOC_LEN (512 * 1024) |
| 19 | |
Rob Herring | 37fc0ed | 2011-10-24 08:50:20 +0000 | [diff] [blame] | 20 | #define CONFIG_PL011_CLOCK 150000000 |
Rob Herring | 37fc0ed | 2011-10-24 08:50:20 +0000 | [diff] [blame] | 21 | |
Stefan Roese | 0044c42 | 2012-08-16 17:55:41 +0000 | [diff] [blame] | 22 | #define CONFIG_SYS_BOOTCOUNT_LE /* Use little-endian accessors */ |
Rob Herring | 877012d | 2012-02-01 16:57:54 +0000 | [diff] [blame] | 23 | |
Rob Herring | 37fc0ed | 2011-10-24 08:50:20 +0000 | [diff] [blame] | 24 | #define CONFIG_SCSI_AHCI_PLAT |
| 25 | #define CONFIG_SYS_SCSI_MAX_SCSI_ID 5 |
| 26 | #define CONFIG_SYS_SCSI_MAX_LUN 1 |
| 27 | #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ |
| 28 | CONFIG_SYS_SCSI_MAX_LUN) |
| 29 | |
Rob Herring | e1df283 | 2013-06-12 22:24:51 -0500 | [diff] [blame] | 30 | #define CONFIG_BOOT_RETRY_TIME -1 |
| 31 | #define CONFIG_RESET_TO_RETRY |
Stefan Roese | d126e01 | 2015-05-18 14:08:23 +0200 | [diff] [blame] | 32 | |
Rob Herring | 37fc0ed | 2011-10-24 08:50:20 +0000 | [diff] [blame] | 33 | /* |
| 34 | * Miscellaneous configurable options |
| 35 | */ |
Rob Herring | 185a5bb | 2013-06-12 22:24:47 -0500 | [diff] [blame] | 36 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
Rob Herring | 37fc0ed | 2011-10-24 08:50:20 +0000 | [diff] [blame] | 37 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE |
Rob Herring | 37fc0ed | 2011-10-24 08:50:20 +0000 | [diff] [blame] | 38 | |
| 39 | #define CONFIG_SYS_LOAD_ADDR 0x800000 |
Rob Herring | 185a5bb | 2013-06-12 22:24:47 -0500 | [diff] [blame] | 40 | #define CONFIG_SYS_64BIT_LBA |
| 41 | |
Jason Hobbs | a34e854 | 2012-02-01 16:57:56 +0000 | [diff] [blame] | 42 | /* Environment data setup |
| 43 | */ |
Jason Hobbs | a34e854 | 2012-02-01 16:57:56 +0000 | [diff] [blame] | 44 | #define CONFIG_SYS_NVRAM_BASE_ADDR 0xfff88000 /* NVRAM base address */ |
| 45 | #define CONFIG_SYS_NVRAM_SIZE 0x8000 /* NVRAM size */ |
Rob Herring | 37fc0ed | 2011-10-24 08:50:20 +0000 | [diff] [blame] | 46 | |
| 47 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
Rob Herring | 37fc0ed | 2011-10-24 08:50:20 +0000 | [diff] [blame] | 48 | #define CONFIG_SYS_INIT_SP_ADDR 0x01000000 |
| 49 | #define CONFIG_SKIP_LOWLEVEL_INIT |
| 50 | |
Andre Przywara | 84b2cd7 | 2021-04-12 01:04:50 +0100 | [diff] [blame] | 51 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
| 52 | "fdt_high=0x20000000\0" \ |
| 53 | "initrd_high=0x20000000\0" |
| 54 | |
Rob Herring | 37fc0ed | 2011-10-24 08:50:20 +0000 | [diff] [blame] | 55 | #endif |