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Timur Tabic59e1b42010-06-14 15:28:24 -05001/*
ramneek mehresh3d7506f2012-04-18 19:39:53 +00002 * Copyright 2010-2012 Freescale Semiconductor, Inc.
Timur Tabic59e1b42010-06-14 15:28:24 -05003 * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
4 * Timur Tabi <timur@freescale.com>
5 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02006 * SPDX-License-Identifier: GPL-2.0+
Timur Tabic59e1b42010-06-14 15:28:24 -05007 */
8
9#ifndef __CONFIG_H
10#define __CONFIG_H
11
12#include "../board/freescale/common/ics307_clk.h"
13
Matthew McClintockaf253602012-05-18 06:04:17 +000014#ifdef CONFIG_SDCARD
Ying Zhang7c8eea52013-08-16 15:16:12 +080015#define CONFIG_SPL_MMC_MINIMAL
16#define CONFIG_SPL_FLUSH_IMAGE
17#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
Ying Zhang7c8eea52013-08-16 15:16:12 +080018#define CONFIG_SYS_TEXT_BASE 0x11001000
19#define CONFIG_SPL_TEXT_BASE 0xf8f81000
Ying Zhangee4d6512014-01-24 15:50:06 +080020#define CONFIG_SPL_PAD_TO 0x20000
21#define CONFIG_SPL_MAX_SIZE (128 * 1024)
Prabhakar Kushwahae222b1f2014-01-14 11:34:26 +053022#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
Ying Zhang7c8eea52013-08-16 15:16:12 +080023#define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000)
24#define CONFIG_SYS_MMC_U_BOOT_START (0x11000000)
Ying Zhangee4d6512014-01-24 15:50:06 +080025#define CONFIG_SYS_MMC_U_BOOT_OFFS (128 << 10)
Ying Zhang7c8eea52013-08-16 15:16:12 +080026#define CONFIG_SYS_MPC85XX_NO_RESETVEC
27#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
28#define CONFIG_SPL_MMC_BOOT
29#ifdef CONFIG_SPL_BUILD
30#define CONFIG_SPL_COMMON_INIT_DDR
31#endif
Matthew McClintockaf253602012-05-18 06:04:17 +000032#endif
33
34#ifdef CONFIG_SPIFLASH
Ying Zhang382ce7e2013-08-16 15:16:14 +080035#define CONFIG_SPL_SPI_FLASH_MINIMAL
36#define CONFIG_SPL_FLUSH_IMAGE
37#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
Ying Zhang382ce7e2013-08-16 15:16:14 +080038#define CONFIG_SYS_TEXT_BASE 0x11001000
39#define CONFIG_SPL_TEXT_BASE 0xf8f81000
Ying Zhangee4d6512014-01-24 15:50:06 +080040#define CONFIG_SPL_PAD_TO 0x20000
41#define CONFIG_SPL_MAX_SIZE (128 * 1024)
Prabhakar Kushwahae222b1f2014-01-14 11:34:26 +053042#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
Ying Zhang382ce7e2013-08-16 15:16:14 +080043#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000)
44#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000)
Ying Zhangee4d6512014-01-24 15:50:06 +080045#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (128 << 10)
Ying Zhang382ce7e2013-08-16 15:16:14 +080046#define CONFIG_SYS_MPC85XX_NO_RESETVEC
47#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
48#define CONFIG_SPL_SPI_BOOT
49#ifdef CONFIG_SPL_BUILD
50#define CONFIG_SPL_COMMON_INIT_DDR
51#endif
Matthew McClintockaf253602012-05-18 06:04:17 +000052#endif
53
Matthew McClintockf45210d2013-02-18 10:02:19 +000054#define CONFIG_NAND_FSL_ELBC
York Sun9407c3f2013-12-17 11:21:08 -080055#define CONFIG_SYS_NAND_MAX_ECCPOS 56
56#define CONFIG_SYS_NAND_MAX_OOBFREE 5
Matthew McClintockf45210d2013-02-18 10:02:19 +000057
58#ifdef CONFIG_NAND
Ying Zhang5d97fe22013-08-16 15:16:16 +080059#ifdef CONFIG_TPL_BUILD
60#define CONFIG_SPL_NAND_BOOT
61#define CONFIG_SPL_FLUSH_IMAGE
Simon Glass989e1ce2016-09-12 23:18:45 -060062#define CONFIG_SPL_NAND_INIT
Ying Zhang5d97fe22013-08-16 15:16:16 +080063#define CONFIG_SPL_COMMON_INIT_DDR
64#define CONFIG_SPL_MAX_SIZE (128 << 10)
65#define CONFIG_SPL_TEXT_BASE 0xf8f81000
66#define CONFIG_SYS_MPC85XX_NO_RESETVEC
Prabhakar Kushwahae222b1f2014-01-14 11:34:26 +053067#define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10)
Ying Zhang5d97fe22013-08-16 15:16:16 +080068#define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)
69#define CONFIG_SYS_NAND_U_BOOT_START (0x11000000)
70#define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10)
71#elif defined(CONFIG_SPL_BUILD)
Matthew McClintockf45210d2013-02-18 10:02:19 +000072#define CONFIG_SPL_INIT_MINIMAL
Matthew McClintockf45210d2013-02-18 10:02:19 +000073#define CONFIG_SPL_FLUSH_IMAGE
Ying Zhang5d97fe22013-08-16 15:16:16 +080074#define CONFIG_SPL_TEXT_BASE 0xff800000
75#define CONFIG_SPL_MAX_SIZE 4096
76#define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10)
77#define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000
78#define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000
79#define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10)
80#endif
81#define CONFIG_SPL_PAD_TO 0x20000
82#define CONFIG_TPL_PAD_TO 0x20000
83#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
84#define CONFIG_SYS_TEXT_BASE 0x11001000
85#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
Matthew McClintockf45210d2013-02-18 10:02:19 +000086#endif
87
Timur Tabic59e1b42010-06-14 15:28:24 -050088/* High Level Configuration Options */
Timur Tabic59e1b42010-06-14 15:28:24 -050089#define CONFIG_MP /* support multiple processors */
90
Wolfgang Denk2ae18242010-10-06 09:05:45 +020091#ifndef CONFIG_SYS_TEXT_BASE
Prabhakar Kushwahae222b1f2014-01-14 11:34:26 +053092#define CONFIG_SYS_TEXT_BASE 0xeff40000
Wolfgang Denk2ae18242010-10-06 09:05:45 +020093#endif
94
Kumar Gala7a577fd2011-01-12 02:48:53 -060095#ifndef CONFIG_RESET_VECTOR_ADDRESS
96#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
97#endif
98
Robert P. J. Dayb38eaec2016-05-03 19:52:49 -040099#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
100#define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
101#define CONFIG_PCIE3 /* PCIE controller 3 (ULI bridge) */
Timur Tabic59e1b42010-06-14 15:28:24 -0500102#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
103#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
104#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
105
Timur Tabic59e1b42010-06-14 15:28:24 -0500106#define CONFIG_ENABLE_36BIT_PHYS
Timur Tabibabb3482011-09-06 09:36:06 -0500107
108#ifdef CONFIG_PHYS_64BIT
Timur Tabic59e1b42010-06-14 15:28:24 -0500109#define CONFIG_ADDR_MAP
110#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
Jiang Yutang9899ac12011-01-24 18:21:15 +0800111#endif
Timur Tabic59e1b42010-06-14 15:28:24 -0500112
Timur Tabic59e1b42010-06-14 15:28:24 -0500113#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
114#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
115#define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */
116
117/*
118 * These can be toggled for performance analysis, otherwise use default.
119 */
120#define CONFIG_L2_CACHE
121#define CONFIG_BTB
122
123#define CONFIG_SYS_MEMTEST_START 0x00000000
124#define CONFIG_SYS_MEMTEST_END 0x7fffffff
125
Timur Tabie46fedf2011-08-04 18:03:41 -0500126#define CONFIG_SYS_CCSRBAR 0xffe00000
127#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
Timur Tabic59e1b42010-06-14 15:28:24 -0500128
Matthew McClintockf45210d2013-02-18 10:02:19 +0000129/* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k
130 SPL code*/
131#ifdef CONFIG_SPL_BUILD
132#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
133#endif
134
Timur Tabic59e1b42010-06-14 15:28:24 -0500135/* DDR Setup */
136#define CONFIG_DDR_SPD
137#define CONFIG_VERY_BIG_RAM
Timur Tabic59e1b42010-06-14 15:28:24 -0500138
139#ifdef CONFIG_DDR_ECC
140#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
141#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
142#endif
143
144#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
145#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
146
Timur Tabic59e1b42010-06-14 15:28:24 -0500147#define CONFIG_DIMM_SLOTS_PER_CTLR 1
148#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
149
150/* I2C addresses of SPD EEPROMs */
151#define CONFIG_SYS_SPD_BUS_NUM 1
Kumar Galac39f44d2011-01-31 22:18:47 -0600152#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
Timur Tabic59e1b42010-06-14 15:28:24 -0500153
Matthew McClintockf45210d2013-02-18 10:02:19 +0000154/* These are used when DDR doesn't use SPD. */
155#define CONFIG_SYS_SDRAM_SIZE 2048
156#define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G
157#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F
158#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202
159#define CONFIG_SYS_DDR_CS1_BNDS 0x0040007F
160#define CONFIG_SYS_DDR_CS1_CONFIG 0x80014202
161#define CONFIG_SYS_DDR_TIMING_3 0x00010000
162#define CONFIG_SYS_DDR_TIMING_0 0x40110104
163#define CONFIG_SYS_DDR_TIMING_1 0x5c5bd746
164#define CONFIG_SYS_DDR_TIMING_2 0x0fa8d4ca
165#define CONFIG_SYS_DDR_MODE_1 0x00441221
166#define CONFIG_SYS_DDR_MODE_2 0x00000000
167#define CONFIG_SYS_DDR_INTERVAL 0x0a280100
168#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
169#define CONFIG_SYS_DDR_CLK_CTRL 0x02800000
170#define CONFIG_SYS_DDR_CONTROL 0xc7000008
171#define CONFIG_SYS_DDR_CONTROL_2 0x24401041
172#define CONFIG_SYS_DDR_TIMING_4 0x00220001
173#define CONFIG_SYS_DDR_TIMING_5 0x02401400
174#define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
175#define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8675f608
176
Timur Tabic59e1b42010-06-14 15:28:24 -0500177/*
178 * Memory map
179 *
180 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
181 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable
182 * 0xffc0_0000 0xffc2_ffff PCI IO range 192K non-cacheable
183 *
184 * Localbus cacheable (TBD)
185 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable
186 *
187 * Localbus non-cacheable
188 * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable
189 * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable
Matthew McClintockf45210d2013-02-18 10:02:19 +0000190 * 0xff80_0000 0xff80_7fff NAND 32K non-cacheable
Timur Tabic59e1b42010-06-14 15:28:24 -0500191 * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0
192 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
193 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
194 */
195
196/*
197 * Local Bus Definitions
198 */
Matthew McClintockf45210d2013-02-18 10:02:19 +0000199#define CONFIG_SYS_FLASH_BASE 0xe8000000 /* start of FLASH 128M */
Jiang Yutang9899ac12011-01-24 18:21:15 +0800200#ifdef CONFIG_PHYS_64BIT
Matthew McClintockf45210d2013-02-18 10:02:19 +0000201#define CONFIG_SYS_FLASH_BASE_PHYS 0xfe8000000ull
Jiang Yutang9899ac12011-01-24 18:21:15 +0800202#else
203#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
204#endif
Timur Tabic59e1b42010-06-14 15:28:24 -0500205
206#define CONFIG_FLASH_BR_PRELIM \
Matthew McClintockf45210d2013-02-18 10:02:19 +0000207 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
Timur Tabic59e1b42010-06-14 15:28:24 -0500208#define CONFIG_FLASH_OR_PRELIM (OR_AM_128MB | 0xff7)
209
Matthew McClintockf45210d2013-02-18 10:02:19 +0000210#ifdef CONFIG_NAND
211#define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
212#define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
213#else
Timur Tabic59e1b42010-06-14 15:28:24 -0500214#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
215#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
Matthew McClintockf45210d2013-02-18 10:02:19 +0000216#endif
Timur Tabic59e1b42010-06-14 15:28:24 -0500217
Matthew McClintockf45210d2013-02-18 10:02:19 +0000218#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
Timur Tabic59e1b42010-06-14 15:28:24 -0500219#define CONFIG_SYS_FLASH_QUIET_TEST
220#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
221
Matthew McClintockf45210d2013-02-18 10:02:19 +0000222#define CONFIG_SYS_MAX_FLASH_BANKS 1
Timur Tabic59e1b42010-06-14 15:28:24 -0500223#define CONFIG_SYS_MAX_FLASH_SECT 1024
224
Matthew McClintockf45210d2013-02-18 10:02:19 +0000225#ifndef CONFIG_SYS_MONITOR_BASE
226#ifdef CONFIG_SPL_BUILD
227#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
228#else
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200229#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
Matthew McClintockf45210d2013-02-18 10:02:19 +0000230#endif
231#endif
Timur Tabic59e1b42010-06-14 15:28:24 -0500232
233#define CONFIG_FLASH_CFI_DRIVER
234#define CONFIG_SYS_FLASH_CFI
235#define CONFIG_SYS_FLASH_EMPTY_INFO
236
Matthew McClintockf45210d2013-02-18 10:02:19 +0000237/* Nand Flash */
238#if defined(CONFIG_NAND_FSL_ELBC)
239#define CONFIG_SYS_NAND_BASE 0xff800000
240#ifdef CONFIG_PHYS_64BIT
241#define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull
242#else
243#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
244#endif
245
Ying Zhang5d97fe22013-08-16 15:16:16 +0800246#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
Matthew McClintockf45210d2013-02-18 10:02:19 +0000247#define CONFIG_SYS_MAX_NAND_DEVICE 1
Ying Zhang5d97fe22013-08-16 15:16:16 +0800248#define CONFIG_SYS_NAND_BLOCK_SIZE (256 * 1024)
Matthew McClintockf45210d2013-02-18 10:02:19 +0000249#define CONFIG_ELBC_NAND_SPL_STATIC_PGSIZE
250
251/* NAND flash config */
252#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
253 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
254 | BR_PS_8 /* Port Size = 8 bit */ \
255 | BR_MS_FCM /* MSEL = FCM */ \
256 | BR_V) /* valid */
257#define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB /* length 256K */ \
258 | OR_FCM_PGS /* Large Page*/ \
259 | OR_FCM_CSCT \
260 | OR_FCM_CST \
261 | OR_FCM_CHT \
262 | OR_FCM_SCY_1 \
263 | OR_FCM_TRLX \
264 | OR_FCM_EHTR)
265#ifdef CONFIG_NAND
266#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
267#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
268#else
269#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
270#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
271#endif
272
273#endif /* CONFIG_NAND_FSL_ELBC */
274
Timur Tabic59e1b42010-06-14 15:28:24 -0500275#define CONFIG_BOARD_EARLY_INIT_R
276#define CONFIG_MISC_INIT_R
Timur Tabia2d12f82010-07-21 16:56:19 -0500277#define CONFIG_HWCONFIG
Timur Tabic59e1b42010-06-14 15:28:24 -0500278
279#define CONFIG_FSL_NGPIXIS
280#define PIXIS_BASE 0xffdf0000 /* PIXIS registers */
Jiang Yutang9899ac12011-01-24 18:21:15 +0800281#ifdef CONFIG_PHYS_64BIT
Timur Tabic59e1b42010-06-14 15:28:24 -0500282#define PIXIS_BASE_PHYS 0xfffdf0000ull
Jiang Yutang9899ac12011-01-24 18:21:15 +0800283#else
284#define PIXIS_BASE_PHYS PIXIS_BASE
285#endif
Timur Tabic59e1b42010-06-14 15:28:24 -0500286
287#define CONFIG_SYS_BR2_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
288#define CONFIG_SYS_OR2_PRELIM (OR_AM_32KB | 0x6ff7)
289
290#define PIXIS_LBMAP_SWITCH 7
York Sun29068452011-01-26 10:30:00 -0800291#define PIXIS_LBMAP_MASK 0xF0
Timur Tabic59e1b42010-06-14 15:28:24 -0500292#define PIXIS_LBMAP_ALTBANK 0x20
Matthew McClintockf45210d2013-02-18 10:02:19 +0000293#define PIXIS_SPD 0x07
294#define PIXIS_SPD_SYSCLK_MASK 0x07
Jiang Yutang9b6e9d12011-02-24 16:11:56 +0800295#define PIXIS_ELBC_SPI_MASK 0xc0
296#define PIXIS_SPI 0x80
Timur Tabic59e1b42010-06-14 15:28:24 -0500297
298#define CONFIG_SYS_INIT_RAM_LOCK
299#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200300#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
Timur Tabic59e1b42010-06-14 15:28:24 -0500301
Timur Tabic59e1b42010-06-14 15:28:24 -0500302#define CONFIG_SYS_GBL_DATA_OFFSET \
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200303 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Timur Tabic59e1b42010-06-14 15:28:24 -0500304#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
305
Prabhakar Kushwaha9307cba2014-03-31 15:31:48 +0530306#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
Jerry Huang07b5edc2011-11-02 09:16:44 +0800307#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
Timur Tabic59e1b42010-06-14 15:28:24 -0500308
309/*
Ying Zhang7c8eea52013-08-16 15:16:12 +0800310 * Config the L2 Cache as L2 SRAM
311*/
312#if defined(CONFIG_SPL_BUILD)
Ying Zhang382ce7e2013-08-16 15:16:14 +0800313#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
Ying Zhang7c8eea52013-08-16 15:16:12 +0800314#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
315#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
316#define CONFIG_SYS_L2_SIZE (256 << 10)
317#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
318#define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
Ying Zhang27585bd2014-01-24 15:50:08 +0800319#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024)
Ying Zhang7c8eea52013-08-16 15:16:12 +0800320#define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10)
Ying Zhang27585bd2014-01-24 15:50:08 +0800321#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024)
322#define CONFIG_SPL_RELOC_MALLOC_SIZE (108 << 10)
Ying Zhang7c8eea52013-08-16 15:16:12 +0800323#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
Ying Zhang5d97fe22013-08-16 15:16:16 +0800324#elif defined(CONFIG_NAND)
325#ifdef CONFIG_TPL_BUILD
326#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
327#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
328#define CONFIG_SYS_L2_SIZE (256 << 10)
329#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
330#define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
331#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
332#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
333#define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10)
334#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
335#else
336#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
337#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
338#define CONFIG_SYS_L2_SIZE (256 << 10)
339#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
340#define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x2000)
341#define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
342#endif
Ying Zhang7c8eea52013-08-16 15:16:12 +0800343#endif
344#endif
345
346/*
Timur Tabic59e1b42010-06-14 15:28:24 -0500347 * Serial Port
348 */
349#define CONFIG_CONS_INDEX 1
Timur Tabic59e1b42010-06-14 15:28:24 -0500350#define CONFIG_SYS_NS16550_SERIAL
351#define CONFIG_SYS_NS16550_REG_SIZE 1
352#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
Ying Zhang7c8eea52013-08-16 15:16:12 +0800353#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
Matthew McClintockf45210d2013-02-18 10:02:19 +0000354#define CONFIG_NS16550_MIN_FUNCTIONS
355#endif
Timur Tabic59e1b42010-06-14 15:28:24 -0500356
357#define CONFIG_SYS_BAUDRATE_TABLE \
358 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
359
360#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
361#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
362
Timur Tabic59e1b42010-06-14 15:28:24 -0500363/* Video */
Timur Tabiba8e76b2011-04-11 14:18:22 -0500364
Timur Tabid5e01e42010-09-24 01:25:53 +0200365#ifdef CONFIG_FSL_DIU_FB
366#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x10000)
Timur Tabid5e01e42010-09-24 01:25:53 +0200367#define CONFIG_VIDEO_LOGO
368#define CONFIG_VIDEO_BMP_LOGO
Timur Tabi55b05232010-09-16 16:35:44 -0500369#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
370/*
371 * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
372 * disable empty flash sector detection, which is I/O-intensive.
373 */
374#undef CONFIG_SYS_FLASH_EMPTY_INFO
Timur Tabic59e1b42010-06-14 15:28:24 -0500375#endif
376
Timur Tabiba8e76b2011-04-11 14:18:22 -0500377#ifndef CONFIG_FSL_DIU_FB
Jiang Yutang218a7582011-01-24 18:21:19 +0800378#endif
379
380#ifdef CONFIG_ATI
381#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT
Jiang Yutang218a7582011-01-24 18:21:19 +0800382#define CONFIG_BIOSEMU
Jiang Yutang218a7582011-01-24 18:21:19 +0800383#define CONFIG_ATI_RADEON_FB
384#define CONFIG_VIDEO_LOGO
385#define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
Jiang Yutang218a7582011-01-24 18:21:19 +0800386#endif
387
Timur Tabic59e1b42010-06-14 15:28:24 -0500388/* I2C */
Heiko Schocher00f792e2012-10-24 13:48:22 +0200389#define CONFIG_SYS_I2C
390#define CONFIG_SYS_I2C_FSL
391#define CONFIG_SYS_FSL_I2C_SPEED 400000
392#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
393#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
394#define CONFIG_SYS_FSL_I2C2_SPEED 400000
395#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
396#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
Timur Tabic59e1b42010-06-14 15:28:24 -0500397#define CONFIG_SYS_I2C_NOPROBES {{0, 0x29}}
Timur Tabic59e1b42010-06-14 15:28:24 -0500398
399/*
400 * I2C2 EEPROM
401 */
402#define CONFIG_ID_EEPROM
403#define CONFIG_SYS_I2C_EEPROM_NXID
404#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
405#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
406#define CONFIG_SYS_EEPROM_BUS_NUM 1
407
408/*
Jiang Yutang9b6e9d12011-02-24 16:11:56 +0800409 * eSPI - Enhanced SPI
410 */
Jiang Yutang9b6e9d12011-02-24 16:11:56 +0800411
412#define CONFIG_HARD_SPI
Jiang Yutang9b6e9d12011-02-24 16:11:56 +0800413
Jiang Yutang9b6e9d12011-02-24 16:11:56 +0800414#define CONFIG_SF_DEFAULT_SPEED 10000000
415#define CONFIG_SF_DEFAULT_MODE 0
416
417/*
Timur Tabic59e1b42010-06-14 15:28:24 -0500418 * General PCI
419 * Memory space is mapped 1-1, but I/O space must start from 0.
420 */
421
422/* controller 1, Slot 2, tgtid 1, Base address a000 */
423#define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
Jiang Yutang9899ac12011-01-24 18:21:15 +0800424#ifdef CONFIG_PHYS_64BIT
Timur Tabic59e1b42010-06-14 15:28:24 -0500425#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
426#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull
Jiang Yutang9899ac12011-01-24 18:21:15 +0800427#else
428#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
429#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000
430#endif
Timur Tabic59e1b42010-06-14 15:28:24 -0500431#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
432#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000
433#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
Jiang Yutang9899ac12011-01-24 18:21:15 +0800434#ifdef CONFIG_PHYS_64BIT
Timur Tabic59e1b42010-06-14 15:28:24 -0500435#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull
Jiang Yutang9899ac12011-01-24 18:21:15 +0800436#else
437#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000
438#endif
Timur Tabic59e1b42010-06-14 15:28:24 -0500439#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
440
441/* controller 2, direct to uli, tgtid 2, Base address 9000 */
442#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
Jiang Yutang9899ac12011-01-24 18:21:15 +0800443#ifdef CONFIG_PHYS_64BIT
Timur Tabic59e1b42010-06-14 15:28:24 -0500444#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
445#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
Jiang Yutang9899ac12011-01-24 18:21:15 +0800446#else
447#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
448#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
449#endif
Timur Tabic59e1b42010-06-14 15:28:24 -0500450#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
451#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
452#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
Jiang Yutang9899ac12011-01-24 18:21:15 +0800453#ifdef CONFIG_PHYS_64BIT
Timur Tabic59e1b42010-06-14 15:28:24 -0500454#define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
Jiang Yutang9899ac12011-01-24 18:21:15 +0800455#else
456#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
457#endif
Timur Tabic59e1b42010-06-14 15:28:24 -0500458#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
459
460/* controller 3, Slot 1, tgtid 3, Base address b000 */
461#define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000
Jiang Yutang9899ac12011-01-24 18:21:15 +0800462#ifdef CONFIG_PHYS_64BIT
Timur Tabic59e1b42010-06-14 15:28:24 -0500463#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
464#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull
Jiang Yutang9899ac12011-01-24 18:21:15 +0800465#else
466#define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000
467#define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000
468#endif
Timur Tabic59e1b42010-06-14 15:28:24 -0500469#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
470#define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000
471#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
Jiang Yutang9899ac12011-01-24 18:21:15 +0800472#ifdef CONFIG_PHYS_64BIT
Timur Tabic59e1b42010-06-14 15:28:24 -0500473#define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull
Jiang Yutang9899ac12011-01-24 18:21:15 +0800474#else
475#define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000
476#endif
Timur Tabic59e1b42010-06-14 15:28:24 -0500477#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
478
479#ifdef CONFIG_PCI
Gabor Juhos842033e2013-05-30 07:06:12 +0000480#define CONFIG_PCI_INDIRECT_BRIDGE
Timur Tabic59e1b42010-06-14 15:28:24 -0500481#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
482#endif
483
484/* SATA */
485#define CONFIG_LIBATA
486#define CONFIG_FSL_SATA
Zang Roy-R619119760b272012-11-26 00:05:38 +0000487#define CONFIG_FSL_SATA_V2
Timur Tabic59e1b42010-06-14 15:28:24 -0500488
489#define CONFIG_SYS_SATA_MAX_DEVICE 2
490#define CONFIG_SATA1
491#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
492#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
493#define CONFIG_SATA2
494#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
495#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
496
497#ifdef CONFIG_FSL_SATA
498#define CONFIG_LBA48
Timur Tabic59e1b42010-06-14 15:28:24 -0500499#endif
500
Timur Tabic59e1b42010-06-14 15:28:24 -0500501#ifdef CONFIG_MMC
Timur Tabic59e1b42010-06-14 15:28:24 -0500502#define CONFIG_FSL_ESDHC
Timur Tabic59e1b42010-06-14 15:28:24 -0500503#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
504#endif
505
Timur Tabic59e1b42010-06-14 15:28:24 -0500506#define CONFIG_TSEC_ENET
507#ifdef CONFIG_TSEC_ENET
508
509#define CONFIG_TSECV2
Timur Tabic59e1b42010-06-14 15:28:24 -0500510
511#define CONFIG_MII /* MII PHY management */
512#define CONFIG_TSEC1 1
513#define CONFIG_TSEC1_NAME "eTSEC1"
514#define CONFIG_TSEC2 1
515#define CONFIG_TSEC2_NAME "eTSEC2"
516
517#define TSEC1_PHY_ADDR 1
518#define TSEC2_PHY_ADDR 2
519
520#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
521#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
522
523#define TSEC1_PHYIDX 0
524#define TSEC2_PHYIDX 0
525
526#define CONFIG_ETHPRIME "eTSEC1"
Timur Tabic59e1b42010-06-14 15:28:24 -0500527#endif
528
529/*
Yangbo Lu94b383e2014-10-16 10:58:55 +0800530 * Dynamic MTD Partition support with mtdparts
531 */
532#define CONFIG_MTD_DEVICE
533#define CONFIG_MTD_PARTITIONS
Yangbo Lu94b383e2014-10-16 10:58:55 +0800534#define CONFIG_FLASH_CFI_MTD
535#ifdef CONFIG_PHYS_64BIT
536#define MTDIDS_DEFAULT "nor0=fe8000000.nor"
537#define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:48m(ramdisk)," \
538 "14m(diagnostic),2m(dink),6m(kernel),58112k(fs)," \
539 "512k(dtb),768k(u-boot)"
540#else
541#define MTDIDS_DEFAULT "nor0=e8000000.nor"
542#define MTDPARTS_DEFAULT "mtdparts=e8000000.nor:48m(ramdisk)," \
543 "14m(diagnostic),2m(dink),6m(kernel),58112k(fs)," \
544 "512k(dtb),768k(u-boot)"
545#endif
546
547/*
Timur Tabic59e1b42010-06-14 15:28:24 -0500548 * Environment
549 */
Ying Zhang382ce7e2013-08-16 15:16:14 +0800550#ifdef CONFIG_SPIFLASH
Matthew McClintockaf253602012-05-18 06:04:17 +0000551#define CONFIG_ENV_SPI_BUS 0
552#define CONFIG_ENV_SPI_CS 0
553#define CONFIG_ENV_SPI_MAX_HZ 10000000
554#define CONFIG_ENV_SPI_MODE 0
555#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
556#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
557#define CONFIG_ENV_SECT_SIZE 0x10000
Ying Zhang7c8eea52013-08-16 15:16:12 +0800558#elif defined(CONFIG_SDCARD)
Ying Zhang7c8eea52013-08-16 15:16:12 +0800559#define CONFIG_FSL_FIXED_MMC_LOCATION
Timur Tabic59e1b42010-06-14 15:28:24 -0500560#define CONFIG_ENV_SIZE 0x2000
Matthew McClintockaf253602012-05-18 06:04:17 +0000561#define CONFIG_SYS_MMC_ENV_DEV 0
Matthew McClintockf45210d2013-02-18 10:02:19 +0000562#elif defined(CONFIG_NAND)
Ying Zhang5d97fe22013-08-16 15:16:16 +0800563#ifdef CONFIG_TPL_BUILD
564#define CONFIG_ENV_SIZE 0x2000
565#define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
566#else
Matthew McClintockaf253602012-05-18 06:04:17 +0000567#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
Ying Zhang5d97fe22013-08-16 15:16:16 +0800568#endif
Ying Zhang5d97fe22013-08-16 15:16:16 +0800569#define CONFIG_ENV_OFFSET (1024 * 1024)
Matthew McClintockaf253602012-05-18 06:04:17 +0000570#define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE)
Matthew McClintockf45210d2013-02-18 10:02:19 +0000571#elif defined(CONFIG_SYS_RAMBOOT)
Matthew McClintockaf253602012-05-18 06:04:17 +0000572#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
573#define CONFIG_ENV_SIZE 0x2000
Matthew McClintockaf253602012-05-18 06:04:17 +0000574#else
Matthew McClintockaf253602012-05-18 06:04:17 +0000575#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
Matthew McClintockaf253602012-05-18 06:04:17 +0000576#define CONFIG_ENV_SIZE 0x2000
577#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
578#endif
Timur Tabic59e1b42010-06-14 15:28:24 -0500579
580#define CONFIG_LOADS_ECHO
581#define CONFIG_SYS_LOADS_BAUD_CHANGE
582
583/*
Timur Tabic59e1b42010-06-14 15:28:24 -0500584 * USB
585 */
ramneek mehresh3d7506f2012-04-18 19:39:53 +0000586#define CONFIG_HAS_FSL_DR_USB
587#ifdef CONFIG_HAS_FSL_DR_USB
Tom Rini8850c5d2017-05-12 22:33:27 -0400588#ifdef CONFIG_USB_EHCI_HCD
Timur Tabic59e1b42010-06-14 15:28:24 -0500589#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
590#define CONFIG_USB_EHCI_FSL
Timur Tabic59e1b42010-06-14 15:28:24 -0500591#endif
ramneek mehresh3d7506f2012-04-18 19:39:53 +0000592#endif
Timur Tabic59e1b42010-06-14 15:28:24 -0500593
594/*
595 * Miscellaneous configurable options
596 */
597#define CONFIG_SYS_LONGHELP /* undef to save memory */
598#define CONFIG_CMDLINE_EDITING /* Command-line editing */
Kim Phillips5be58f52010-07-14 19:47:18 -0500599#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
Timur Tabic59e1b42010-06-14 15:28:24 -0500600#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Timur Tabic59e1b42010-06-14 15:28:24 -0500601
602/*
603 * For booting Linux, the board info and command line data
Kumar Galaa832ac42011-04-28 10:13:41 -0500604 * have to be in the first 64 MB of memory, since this is
Timur Tabic59e1b42010-06-14 15:28:24 -0500605 * the maximum mapped by the Linux kernel during initialization.
606 */
Kumar Galaa832ac42011-04-28 10:13:41 -0500607#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
608#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
Timur Tabic59e1b42010-06-14 15:28:24 -0500609
Timur Tabic59e1b42010-06-14 15:28:24 -0500610#ifdef CONFIG_CMD_KGDB
611#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
Timur Tabic59e1b42010-06-14 15:28:24 -0500612#endif
613
614/*
615 * Environment Configuration
616 */
617
618#define CONFIG_HOSTNAME p1022ds
Joe Hershberger8b3637c2011-10-13 13:03:47 +0000619#define CONFIG_ROOTPATH "/opt/nfsroot"
Joe Hershbergerb3f44c22011-10-13 13:03:48 +0000620#define CONFIG_BOOTFILE "uImage"
Timur Tabic59e1b42010-06-14 15:28:24 -0500621#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
622
623#define CONFIG_LOADADDR 1000000
624
Timur Tabi84e34b62012-05-04 12:21:29 +0000625#define CONFIG_EXTRA_ENV_SETTINGS \
626 "netdev=eth0\0" \
Marek Vasut5368c552012-09-23 17:41:24 +0200627 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
628 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
Timur Tabi84e34b62012-05-04 12:21:29 +0000629 "tftpflash=tftpboot $loadaddr $uboot && " \
630 "protect off $ubootaddr +$filesize && " \
631 "erase $ubootaddr +$filesize && " \
632 "cp.b $loadaddr $ubootaddr $filesize && " \
633 "protect on $ubootaddr +$filesize && " \
634 "cmp.b $loadaddr $ubootaddr $filesize\0" \
635 "consoledev=ttyS0\0" \
636 "ramdiskaddr=2000000\0" \
637 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
Scott Woodb24a4f62016-07-19 17:52:06 -0500638 "fdtaddr=1e00000\0" \
Timur Tabi84e34b62012-05-04 12:21:29 +0000639 "fdtfile=p1022ds.dtb\0" \
640 "bdev=sda3\0" \
Timur Tabiba8e76b2011-04-11 14:18:22 -0500641 "hwconfig=esdhc;audclk:12\0"
Timur Tabic59e1b42010-06-14 15:28:24 -0500642
643#define CONFIG_HDBOOT \
644 "setenv bootargs root=/dev/$bdev rw " \
Timur Tabi84e34b62012-05-04 12:21:29 +0000645 "console=$consoledev,$baudrate $othbootargs $videobootargs;" \
Timur Tabic59e1b42010-06-14 15:28:24 -0500646 "tftp $loadaddr $bootfile;" \
647 "tftp $fdtaddr $fdtfile;" \
648 "bootm $loadaddr - $fdtaddr"
649
650#define CONFIG_NFSBOOTCOMMAND \
651 "setenv bootargs root=/dev/nfs rw " \
652 "nfsroot=$serverip:$rootpath " \
653 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
Timur Tabi84e34b62012-05-04 12:21:29 +0000654 "console=$consoledev,$baudrate $othbootargs $videobootargs;" \
Timur Tabic59e1b42010-06-14 15:28:24 -0500655 "tftp $loadaddr $bootfile;" \
656 "tftp $fdtaddr $fdtfile;" \
657 "bootm $loadaddr - $fdtaddr"
658
659#define CONFIG_RAMBOOTCOMMAND \
660 "setenv bootargs root=/dev/ram rw " \
Timur Tabi84e34b62012-05-04 12:21:29 +0000661 "console=$consoledev,$baudrate $othbootargs $videobootargs;" \
Timur Tabic59e1b42010-06-14 15:28:24 -0500662 "tftp $ramdiskaddr $ramdiskfile;" \
663 "tftp $loadaddr $bootfile;" \
664 "tftp $fdtaddr $fdtfile;" \
665 "bootm $loadaddr $ramdiskaddr $fdtaddr"
666
667#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
668
669#endif