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Michal Simek1f4f3d32016-04-07 15:58:23 +02001/*
2 * Configuration for Xilinx ZynqMP zcu102
3 *
4 * (C) Copyright 2015 Xilinx, Inc.
5 * Michal Simek <michal.simek@xilinx.com>
6 *
7 * SPDX-License-Identifier: GPL-2.0+
8 */
9
10#ifndef __CONFIG_ZYNQMP_ZCU102_H
11#define __CONFIG_ZYNQMP_ZCU102_H
12
13#define CONFIG_ZYNQ_SDHCI1
14#define CONFIG_ZYNQ_I2C0
15#define CONFIG_ZYNQ_I2C1
16#define CONFIG_SYS_I2C_MAX_HOPS 1
17#define CONFIG_SYS_NUM_I2C_BUSES 18
18#define CONFIG_SYS_I2C_BUSES { \
19 {0, {I2C_NULL_HOP} }, \
20 {0, {{I2C_MUX_PCA9544, 0x75, 0} } }, \
21 {0, {{I2C_MUX_PCA9544, 0x75, 1} } }, \
22 {0, {{I2C_MUX_PCA9544, 0x75, 2} } }, \
23 {1, {I2C_NULL_HOP} }, \
24 {1, {{I2C_MUX_PCA9548, 0x74, 0} } }, \
25 {1, {{I2C_MUX_PCA9548, 0x74, 1} } }, \
26 {1, {{I2C_MUX_PCA9548, 0x74, 2} } }, \
27 {1, {{I2C_MUX_PCA9548, 0x74, 3} } }, \
28 {1, {{I2C_MUX_PCA9548, 0x74, 4} } }, \
29 {1, {{I2C_MUX_PCA9548, 0x75, 0} } }, \
30 {1, {{I2C_MUX_PCA9548, 0x75, 1} } }, \
31 {1, {{I2C_MUX_PCA9548, 0x75, 2} } }, \
32 {1, {{I2C_MUX_PCA9548, 0x75, 3} } }, \
33 {1, {{I2C_MUX_PCA9548, 0x75, 4} } }, \
34 {1, {{I2C_MUX_PCA9548, 0x75, 5} } }, \
35 {1, {{I2C_MUX_PCA9548, 0x75, 6} } }, \
36 {1, {{I2C_MUX_PCA9548, 0x75, 7} } }, \
37 }
38
39#define CONFIG_SYS_I2C_ZYNQ
Michal Simekff9bd8e2016-04-11 13:48:32 +020040#define CONFIG_PCA953X
Michal Simekff9bd8e2016-04-11 13:48:32 +020041
Michal Simek1f4f3d32016-04-07 15:58:23 +020042#define CONFIG_ZYNQMP_XHCI_LIST {ZYNQMP_USB0_XHCI_BASEADDR}
43
Michal Simek6919b4b2016-04-22 11:48:49 +020044#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
Michal Simek6919b4b2016-04-22 11:48:49 +020045#define CONFIG_ZYNQ_EEPROM_BUS 5
46#define CONFIG_ZYNQ_GEM_EEPROM_ADDR 0x54
47#define CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET 0x20
48
Michal Simek1f4f3d32016-04-07 15:58:23 +020049#include <configs/xilinx_zynqmp.h>
50
51#endif /* __CONFIG_ZYNQMP_ZCU102_H */