blob: 71f8be8138a30119f45470e5ff61dfe9d688e928 [file] [log] [blame]
Vasily Khoruzhickf19eb152016-03-20 18:37:00 -07001/*
2 * Aeronix Zipit Z2 configuration file
3 *
4 * Copyright (C) 2009-2010 Marek Vasut <marek.vasut@gmail.com>
5 *
6 * SPDX-License-Identifier: GPL-2.0+
7 */
8
9#ifndef __CONFIG_H
10#define __CONFIG_H
11
12/*
13 * High Level Board Configuration Options
14 */
15#define CONFIG_CPU_PXA27X 1 /* Marvell PXA270 CPU */
16#define CONFIG_SYS_TEXT_BASE 0x0
17
Vasily Khoruzhickf19eb152016-03-20 18:37:00 -070018#undef CONFIG_SKIP_LOWLEVEL_INIT
19#define CONFIG_PREBOOT
20
21/*
22 * Environment settings
23 */
24#define CONFIG_ENV_OVERWRITE
Vasily Khoruzhickf19eb152016-03-20 18:37:00 -070025#define CONFIG_ENV_ADDR 0x40000
26#define CONFIG_ENV_SIZE 0x10000
27
Vasily Khoruzhickf19eb152016-03-20 18:37:00 -070028#define CONFIG_SYS_MALLOC_LEN (128*1024)
29#define CONFIG_ARCH_CPU_INIT
30
31#define CONFIG_BOOTCOMMAND \
32 "if mmc rescan && ext2load mmc 0 0xa0000000 boot/uboot.script ;"\
33 "then " \
34 "source 0xa0000000; " \
35 "else " \
36 "bootm 0x50000; " \
37 "fi; "
Vasily Khoruzhickf19eb152016-03-20 18:37:00 -070038#define CONFIG_TIMESTAMP
Vasily Khoruzhickf19eb152016-03-20 18:37:00 -070039#define CONFIG_CMDLINE_TAG
40#define CONFIG_SETUP_MEMORY_TAGS
41#define CONFIG_SYS_TEXT_BASE 0x0
Vasily Khoruzhickf19eb152016-03-20 18:37:00 -070042
43/*
44 * Serial Console Configuration
45 * STUART - the lower serial port on Colibri board
46 */
Vasily Khoruzhickf19eb152016-03-20 18:37:00 -070047#define CONFIG_STUART 1
48#define CONFIG_CONS_INDEX 2
Vasily Khoruzhickf19eb152016-03-20 18:37:00 -070049
50/*
51 * Bootloader Components Configuration
52 */
Vasily Khoruzhickf19eb152016-03-20 18:37:00 -070053
54/*
55 * MMC Card Configuration
56 */
57#ifdef CONFIG_CMD_MMC
Vasily Khoruzhickf19eb152016-03-20 18:37:00 -070058#define CONFIG_PXA_MMC_GENERIC
59#define CONFIG_SYS_MMC_BASE 0xF0000000
Vasily Khoruzhickf19eb152016-03-20 18:37:00 -070060#endif
61
62/*
63 * SPI and LCD
64 */
65#ifdef CONFIG_CMD_SPI
66#define CONFIG_SOFT_SPI
Vasily Khoruzhick59fa0892016-03-20 18:37:01 -070067#define CONFIG_LCD_ROTATION
Vasily Khoruzhickf19eb152016-03-20 18:37:00 -070068#define CONFIG_PXA_LCD
69#define CONFIG_LMS283GF05
70
71#define SPI_DELAY udelay(10)
72#define SPI_SDA(val) zipitz2_spi_sda(val)
73#define SPI_SCL(val) zipitz2_spi_scl(val)
74#define SPI_READ zipitz2_spi_read()
75#ifndef __ASSEMBLY__
76void zipitz2_spi_sda(int);
77void zipitz2_spi_scl(int);
78unsigned char zipitz2_spi_read(void);
79#endif
80#endif
81
Vasily Khoruzhickf19eb152016-03-20 18:37:00 -070082#define CONFIG_SYS_LONGHELP /* undef to save memory */
Thomas Petazzoni432e3982017-08-23 22:59:02 +020083
Vasily Khoruzhickf19eb152016-03-20 18:37:00 -070084#define CONFIG_SYS_DEVICE_NULLDEV 1
85
86/*
87 * Clock Configuration
88 */
89#define CONFIG_SYS_CPUSPEED 0x190 /* standard setting for 312MHz; L=16, N=1.5, A=0, SDCLK!=SystemBus */
90
91/*
92 * SRAM Map
93 */
94#define PHYS_SRAM 0x5c000000 /* SRAM Bank #1 */
95#define PHYS_SRAM_SIZE 0x00040000 /* 256k */
96
97/*
98 * DRAM Map
99 */
100#define CONFIG_NR_DRAM_BANKS 1 /* We have 1 bank of DRAM */
101#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
102#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */
103
104#define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */
105#define CONFIG_SYS_DRAM_SIZE 0x02000000 /* 32 MB DRAM */
106
107#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */
108#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
109
110#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_DRAM_BASE
111
112#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
113#define CONFIG_SYS_INIT_SP_ADDR (GENERATED_GBL_DATA_SIZE + PHYS_SRAM + 2048)
114
115/*
116 * NOR FLASH
117 */
118#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
119#define PHYS_FLASH_SIZE 0x00800000 /* 8 MB */
120#define PHYS_FLASH_SECT_SIZE 0x00010000 /* 64 KB sectors */
121#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
122
123#define CONFIG_SYS_FLASH_CFI
124#define CONFIG_FLASH_CFI_DRIVER 1
125#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
126
127#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1
128#define CONFIG_SYS_MONITOR_LEN PHYS_FLASH_SECT_SIZE
129
130#define CONFIG_SYS_MAX_FLASH_BANKS 1
131#define CONFIG_SYS_MAX_FLASH_SECT 256
132
133#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
134
135#define CONFIG_SYS_FLASH_ERASE_TOUT 240000
136#define CONFIG_SYS_FLASH_WRITE_TOUT 240000
137#define CONFIG_SYS_FLASH_LOCK_TOUT 240000
138#define CONFIG_SYS_FLASH_UNLOCK_TOUT 240000
139#define CONFIG_SYS_FLASH_PROTECTION
140
141/*
142 * GPIO settings
143 */
144#define CONFIG_SYS_GAFR0_L_VAL 0x02000140
145#define CONFIG_SYS_GAFR0_U_VAL 0x59188000
146#define CONFIG_SYS_GAFR1_L_VAL 0x63900002
147#define CONFIG_SYS_GAFR1_U_VAL 0xaaa03950
148#define CONFIG_SYS_GAFR2_L_VAL 0x0aaaaaaa
149#define CONFIG_SYS_GAFR2_U_VAL 0x29000308
150#define CONFIG_SYS_GAFR3_L_VAL 0x54000000
151#define CONFIG_SYS_GAFR3_U_VAL 0x000000d5
152#define CONFIG_SYS_GPCR0_VAL 0x00000000
153#define CONFIG_SYS_GPCR1_VAL 0x00000020
154#define CONFIG_SYS_GPCR2_VAL 0x00000000
155#define CONFIG_SYS_GPCR3_VAL 0x00000000
156#define CONFIG_SYS_GPDR0_VAL 0xdafcee00
157#define CONFIG_SYS_GPDR1_VAL 0xffa3aaab
158#define CONFIG_SYS_GPDR2_VAL 0x8fe9ffff
159#define CONFIG_SYS_GPDR3_VAL 0x001b1f8a
160#define CONFIG_SYS_GPSR0_VAL 0x06080400
161#define CONFIG_SYS_GPSR1_VAL 0x007f0000
162#define CONFIG_SYS_GPSR2_VAL 0x032a0000
163#define CONFIG_SYS_GPSR3_VAL 0x00000180
164
165#define CONFIG_SYS_PSSR_VAL 0x30
166
167/*
168 * Clock settings
169 */
170#define CONFIG_SYS_CKEN 0x00511220
171#define CONFIG_SYS_CCCR 0x00000190
172
173/*
174 * Memory settings
175 */
176#define CONFIG_SYS_MSC0_VAL 0x2ffc38f8
177#define CONFIG_SYS_MSC1_VAL 0x0000ccd1
178#define CONFIG_SYS_MSC2_VAL 0x0000b884
179#define CONFIG_SYS_MDCNFG_VAL 0x08000ba9
180#define CONFIG_SYS_MDREFR_VAL 0x2011a01e
181#define CONFIG_SYS_MDMRS_VAL 0x00000000
182#define CONFIG_SYS_FLYCNFG_VAL 0x00010001
183#define CONFIG_SYS_SXCNFG_VAL 0x40044004
184
185/*
186 * PCMCIA and CF Interfaces
187 */
188#define CONFIG_SYS_MECR_VAL 0x00000001
189#define CONFIG_SYS_MCMEM0_VAL 0x00014307
190#define CONFIG_SYS_MCMEM1_VAL 0x00014307
191#define CONFIG_SYS_MCATT0_VAL 0x0001c787
192#define CONFIG_SYS_MCATT1_VAL 0x0001c787
193#define CONFIG_SYS_MCIO0_VAL 0x0001430f
194#define CONFIG_SYS_MCIO1_VAL 0x0001430f
195
196#include "pxa-common.h"
197
198#endif /* __CONFIG_H */