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Dave Liu5f820432006-11-03 19:33:44 -06001/*
2 * Copyright (C) 2006 Freescale Semiconductor, Inc.
Dave Liu5f820432006-11-03 19:33:44 -06003 * Dave Liu <daveliu@freescale.com>
Dave Liu5f820432006-11-03 19:33:44 -06004 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 */
13
14#include <common.h>
15#include <ioports.h>
16#include <mpc83xx.h>
17#include <i2c.h>
18#include <spd.h>
19#include <miiphy.h>
Dave Liu5f820432006-11-03 19:33:44 -060020#if defined(CONFIG_PCI)
21#include <pci.h>
22#endif
23#if defined(CONFIG_SPD_EEPROM)
24#include <spd_sdram.h>
25#else
26#include <asm/mmu.h>
27#endif
Kim Phillipsbf0b5422006-11-01 00:10:40 -060028#if defined(CONFIG_OF_FLAT_TREE)
29#include <ft_build.h>
Jerry Van Baren26d02c92007-07-04 21:27:30 -040030#elif defined(CONFIG_OF_LIBFDT)
Gerald Van Baren213bf8c2007-03-31 12:23:51 -040031#include <libfdt.h>
Gerald Van Baren213bf8c2007-03-31 12:23:51 -040032#endif
Tony Li14778582007-08-17 10:35:59 +080033#if defined(CONFIG_PQ_MDS_PIB)
Kim Phillipse58fe952007-08-16 22:53:09 -050034#include "../common/pq-mds-pib.h"
Tony Li14778582007-08-17 10:35:59 +080035#endif
Dave Liu5f820432006-11-03 19:33:44 -060036
Dave Liu7737d5c2006-11-03 12:11:15 -060037const qe_iop_conf_t qe_iop_conf_tab[] = {
38 /* GETH1 */
39 {0, 3, 1, 0, 1}, /* TxD0 */
40 {0, 4, 1, 0, 1}, /* TxD1 */
41 {0, 5, 1, 0, 1}, /* TxD2 */
42 {0, 6, 1, 0, 1}, /* TxD3 */
43 {1, 6, 1, 0, 3}, /* TxD4 */
44 {1, 7, 1, 0, 1}, /* TxD5 */
45 {1, 9, 1, 0, 2}, /* TxD6 */
46 {1, 10, 1, 0, 2}, /* TxD7 */
47 {0, 9, 2, 0, 1}, /* RxD0 */
48 {0, 10, 2, 0, 1}, /* RxD1 */
49 {0, 11, 2, 0, 1}, /* RxD2 */
50 {0, 12, 2, 0, 1}, /* RxD3 */
51 {0, 13, 2, 0, 1}, /* RxD4 */
52 {1, 1, 2, 0, 2}, /* RxD5 */
53 {1, 0, 2, 0, 2}, /* RxD6 */
54 {1, 4, 2, 0, 2}, /* RxD7 */
55 {0, 7, 1, 0, 1}, /* TX_EN */
56 {0, 8, 1, 0, 1}, /* TX_ER */
57 {0, 15, 2, 0, 1}, /* RX_DV */
58 {0, 16, 2, 0, 1}, /* RX_ER */
59 {0, 0, 2, 0, 1}, /* RX_CLK */
60 {2, 9, 1, 0, 3}, /* GTX_CLK - CLK10 */
61 {2, 8, 2, 0, 1}, /* GTX125 - CLK9 */
62 /* GETH2 */
63 {0, 17, 1, 0, 1}, /* TxD0 */
64 {0, 18, 1, 0, 1}, /* TxD1 */
65 {0, 19, 1, 0, 1}, /* TxD2 */
66 {0, 20, 1, 0, 1}, /* TxD3 */
67 {1, 2, 1, 0, 1}, /* TxD4 */
68 {1, 3, 1, 0, 2}, /* TxD5 */
69 {1, 5, 1, 0, 3}, /* TxD6 */
70 {1, 8, 1, 0, 3}, /* TxD7 */
71 {0, 23, 2, 0, 1}, /* RxD0 */
72 {0, 24, 2, 0, 1}, /* RxD1 */
73 {0, 25, 2, 0, 1}, /* RxD2 */
74 {0, 26, 2, 0, 1}, /* RxD3 */
75 {0, 27, 2, 0, 1}, /* RxD4 */
76 {1, 12, 2, 0, 2}, /* RxD5 */
77 {1, 13, 2, 0, 3}, /* RxD6 */
78 {1, 11, 2, 0, 2}, /* RxD7 */
79 {0, 21, 1, 0, 1}, /* TX_EN */
80 {0, 22, 1, 0, 1}, /* TX_ER */
81 {0, 29, 2, 0, 1}, /* RX_DV */
82 {0, 30, 2, 0, 1}, /* RX_ER */
83 {0, 31, 2, 0, 1}, /* RX_CLK */
84 {2, 2, 1, 0, 2}, /* GTX_CLK = CLK10 */
85 {2, 3, 2, 0, 1}, /* GTX125 - CLK4 */
86
87 {0, 1, 3, 0, 2}, /* MDIO */
88 {0, 2, 1, 0, 1}, /* MDC */
89
90 {0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */
91};
92
Dave Liu5f820432006-11-03 19:33:44 -060093int board_early_init_f(void)
94{
Kim Phillips3fc0bd12007-02-14 19:50:53 -060095
96 u8 *bcsr = (u8 *)CFG_BCSR;
97 const immap_t *immr = (immap_t *)CFG_IMMR;
Dave Liu5f820432006-11-03 19:33:44 -060098
99 /* Enable flash write */
100 bcsr[0xa] &= ~0x04;
101
Kim Phillips3fc0bd12007-02-14 19:50:53 -0600102 /* Disable G1TXCLK, G2TXCLK h/w buffers (rev.2 h/w bug workaround) */
103 if (immr->sysconf.spridr == SPR_8360_REV20 ||
Lee Nipper1ded0242007-06-14 20:07:33 -0500104 immr->sysconf.spridr == SPR_8360E_REV20 ||
105 immr->sysconf.spridr == SPR_8360_REV21 ||
106 immr->sysconf.spridr == SPR_8360E_REV21)
Kim Phillips3fc0bd12007-02-14 19:50:53 -0600107 bcsr[0xe] = 0x30;
108
Dave Liu5f820432006-11-03 19:33:44 -0600109 return 0;
110}
111
Tony Li14778582007-08-17 10:35:59 +0800112int board_early_init_r(void)
113{
114#ifdef CONFIG_PQ_MDS_PIB
115 pib_init();
116#endif
117 return 0;
118}
119
Dave Liu5f820432006-11-03 19:33:44 -0600120#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
121extern void ddr_enable_ecc(unsigned int dram_size);
122#endif
123int fixed_sdram(void);
124void sdram_init(void);
125
126long int initdram(int board_type)
127{
Timur Tabid239d742006-11-03 12:00:28 -0600128 volatile immap_t *im = (immap_t *) CFG_IMMR;
Dave Liu5f820432006-11-03 19:33:44 -0600129 u32 msize = 0;
130
131 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
132 return -1;
133
134 /* DDR SDRAM - Main SODIMM */
135 im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR;
136#if defined(CONFIG_SPD_EEPROM)
137 msize = spd_sdram();
138#else
139 msize = fixed_sdram();
140#endif
141
142#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
143 /*
144 * Initialize DDR ECC byte
145 */
146 ddr_enable_ecc(msize * 1024 * 1024);
147#endif
148 /*
149 * Initialize SDRAM if it is on local bus.
150 */
151 sdram_init();
Kim Phillipsbbea46f2007-08-16 22:52:48 -0500152
Dave Liu5f820432006-11-03 19:33:44 -0600153 /* return total bus SDRAM size(bytes) -- DDR */
154 return (msize * 1024 * 1024);
155}
156
157#if !defined(CONFIG_SPD_EEPROM)
158/*************************************************************************
159 * fixed sdram init -- doesn't use serial presence detect.
160 ************************************************************************/
161int fixed_sdram(void)
162{
Timur Tabid239d742006-11-03 12:00:28 -0600163 volatile immap_t *im = (immap_t *) CFG_IMMR;
Dave Liu5f820432006-11-03 19:33:44 -0600164 u32 msize = 0;
165 u32 ddr_size;
166 u32 ddr_size_log2;
167
168 msize = CFG_DDR_SIZE;
169 for (ddr_size = msize << 20, ddr_size_log2 = 0;
170 (ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++) {
171 if (ddr_size & 1) {
172 return -1;
173 }
174 }
175 im->sysconf.ddrlaw[0].ar =
176 LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
177#if (CFG_DDR_SIZE != 256)
178#warning Currenly any ddr size other than 256 is not supported
179#endif
Xie Xiaobod61853c2007-02-14 18:27:17 +0800180#ifdef CONFIG_DDR_II
181 im->ddr.csbnds[0].csbnds = CFG_DDR_CS0_BNDS;
182 im->ddr.cs_config[0] = CFG_DDR_CS0_CONFIG;
183 im->ddr.timing_cfg_0 = CFG_DDR_TIMING_0;
184 im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1;
185 im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2;
186 im->ddr.timing_cfg_3 = CFG_DDR_TIMING_3;
187 im->ddr.sdram_cfg = CFG_DDR_SDRAM_CFG;
188 im->ddr.sdram_cfg2 = CFG_DDR_SDRAM_CFG2;
189 im->ddr.sdram_mode = CFG_DDR_MODE;
190 im->ddr.sdram_mode2 = CFG_DDR_MODE2;
191 im->ddr.sdram_interval = CFG_DDR_INTERVAL;
192 im->ddr.sdram_clk_cntl = CFG_DDR_CLK_CNTL;
193#else
Dave Liu5f820432006-11-03 19:33:44 -0600194 im->ddr.csbnds[0].csbnds = 0x00000007;
195 im->ddr.csbnds[1].csbnds = 0x0008000f;
196
197 im->ddr.cs_config[0] = CFG_DDR_CONFIG;
198 im->ddr.cs_config[1] = CFG_DDR_CONFIG;
199
200 im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1;
201 im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2;
202 im->ddr.sdram_cfg = CFG_DDR_CONTROL;
203
204 im->ddr.sdram_mode = CFG_DDR_MODE;
205 im->ddr.sdram_interval = CFG_DDR_INTERVAL;
Xie Xiaobod61853c2007-02-14 18:27:17 +0800206#endif
Dave Liu5f820432006-11-03 19:33:44 -0600207 udelay(200);
208 im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
209
210 return msize;
211}
212#endif /*!CFG_SPD_EEPROM */
213
214int checkboard(void)
215{
216 puts("Board: Freescale MPC8360EMDS\n");
217 return 0;
218}
219
220/*
221 * if MPC8360EMDS is soldered with SDRAM
222 */
223#if defined(CFG_BR2_PRELIM) \
224 && defined(CFG_OR2_PRELIM) \
225 && defined(CFG_LBLAWBAR2_PRELIM) \
226 && defined(CFG_LBLAWAR2_PRELIM)
227/*
228 * Initialize SDRAM memory on the Local Bus.
229 */
230
231void sdram_init(void)
232{
Timur Tabid239d742006-11-03 12:00:28 -0600233 volatile immap_t *immap = (immap_t *) CFG_IMMR;
Dave Liu5f820432006-11-03 19:33:44 -0600234 volatile lbus83xx_t *lbc = &immap->lbus;
235 uint *sdram_addr = (uint *) CFG_LBC_SDRAM_BASE;
236
Dave Liu5f820432006-11-03 19:33:44 -0600237 /*
238 * Setup SDRAM Base and Option Registers, already done in cpu_init.c
239 */
240 /*setup mtrpt, lsrt and lbcr for LB bus */
241 lbc->lbcr = CFG_LBC_LBCR;
242 lbc->mrtpr = CFG_LBC_MRTPR;
243 lbc->lsrt = CFG_LBC_LSRT;
244 asm("sync");
245
246 /*
247 * Configure the SDRAM controller Machine Mode Register.
248 */
249 lbc->lsdmr = CFG_LBC_LSDMR_5; /* Normal Operation */
250 lbc->lsdmr = CFG_LBC_LSDMR_1; /* Precharge All Banks */
251 asm("sync");
252 *sdram_addr = 0xff;
253 udelay(100);
254
255 /*
256 * We need do 8 times auto refresh operation.
257 */
258 lbc->lsdmr = CFG_LBC_LSDMR_2;
259 asm("sync");
260 *sdram_addr = 0xff; /* 1 times */
261 udelay(100);
262 *sdram_addr = 0xff; /* 2 times */
263 udelay(100);
264 *sdram_addr = 0xff; /* 3 times */
265 udelay(100);
266 *sdram_addr = 0xff; /* 4 times */
267 udelay(100);
268 *sdram_addr = 0xff; /* 5 times */
269 udelay(100);
270 *sdram_addr = 0xff; /* 6 times */
271 udelay(100);
272 *sdram_addr = 0xff; /* 7 times */
273 udelay(100);
274 *sdram_addr = 0xff; /* 8 times */
275 udelay(100);
276
277 /* Mode register write operation */
278 lbc->lsdmr = CFG_LBC_LSDMR_4;
279 asm("sync");
280 *(sdram_addr + 0xcc) = 0xff;
281 udelay(100);
282
283 /* Normal operation */
284 lbc->lsdmr = CFG_LBC_LSDMR_5 | 0x40000000;
285 asm("sync");
286 *sdram_addr = 0xff;
287 udelay(100);
288}
289#else
290void sdram_init(void)
291{
Dave Liu5f820432006-11-03 19:33:44 -0600292}
293#endif
294
Kim Phillips3fde9e82007-08-15 22:30:33 -0500295#if defined(CONFIG_OF_BOARD_SETUP)
296void ft_board_setup(void *blob, bd_t *bd)
Kim Phillipsbf0b5422006-11-01 00:10:40 -0600297{
Kim Phillips6a16e0d2007-08-15 22:30:26 -0500298#if defined(CONFIG_OF_FLAT_TREE)
Kim Phillipsbf0b5422006-11-01 00:10:40 -0600299 u32 *p;
300 int len;
301
Kim Phillipsbf0b5422006-11-01 00:10:40 -0600302 p = ft_get_prop(blob, "/memory/reg", &len);
303 if (p != NULL) {
304 *p++ = cpu_to_be32(bd->bi_memstart);
305 *p = cpu_to_be32(bd->bi_memsize);
306 }
Gerald Van Baren213bf8c2007-03-31 12:23:51 -0400307#endif
Kim Phillips3fde9e82007-08-15 22:30:33 -0500308 ft_cpu_setup(blob, bd);
Gerald Van Baren213bf8c2007-03-31 12:23:51 -0400309#ifdef CONFIG_PCI
310 ft_pci_setup(blob, bd);
311#endif
Kim Phillipsbf0b5422006-11-01 00:10:40 -0600312}
Kim Phillips3fde9e82007-08-15 22:30:33 -0500313#endif