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Aubrey Li65458982007-03-20 18:16:24 +08001/*
2 * U-boot - start.S Startup file of u-boot for BF533/BF561
3 *
Aubrey Li155fd762007-04-05 18:31:18 +08004 * Copyright (c) 2005-2007 Analog Devices Inc.
Aubrey Li65458982007-03-20 18:16:24 +08005 *
6 * This file is based on head.S
7 * Copyright (c) 2003 Metrowerks/Motorola
8 * Copyright (C) 1998 D. Jeff Dionne <jeff@ryeham.ee.ryerson.ca>,
9 * Kenneth Albanowski <kjahds@kjahds.com>,
10 * The Silver Hammer Group, Ltd.
11 * (c) 1995, Dionne & Associates
12 * (c) 1995, DKG Display Tech.
13 *
14 * See file CREDITS for list of people who contributed to this
15 * project.
16 *
17 * This program is free software; you can redistribute it and/or
18 * modify it under the terms of the GNU General Public License as
19 * published by the Free Software Foundation; either version 2 of
20 * the License, or (at your option) any later version.
21 *
22 * This program is distributed in the hope that it will be useful,
23 * but WITHOUT ANY WARRANTY; without even the implied warranty of
24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
25 * GNU General Public License for more details.
26 *
27 * You should have received a copy of the GNU General Public License
28 * along with this program; if not, write to the Free Software
Aubrey Li155fd762007-04-05 18:31:18 +080029 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
30 * MA 02110-1301 USA
Aubrey Li65458982007-03-20 18:16:24 +080031 */
32
33/*
34 * Note: A change in this file subsequently requires a change in
35 * board/$(board_name)/config.mk for a valid u-boot.bin
36 */
37
38#define ASSEMBLY
39
40#include <linux/config.h>
41#include <config.h>
42#include <asm/blackfin.h>
43
44.global _stext;
45.global __bss_start;
46.global start;
47.global _start;
48.global _rambase;
49.global _ramstart;
50.global _ramend;
51.global edata;
52.global _initialize;
53.global _exit;
54.global flashdataend;
55.global init_sdram;
56
57.text
58_start:
59start:
60_stext:
61
62 R0 = 0x32;
63 SYSCFG = R0;
64 SSYNC;
65
66 /*
67 * As per HW reference manual DAG registers,
68 * DATA and Address resgister shall be zero'd
69 * in initialization, after a reset state
70 */
71 r1 = 0; /* Data registers zero'd */
72 r2 = 0;
73 r3 = 0;
74 r4 = 0;
75 r5 = 0;
76 r6 = 0;
77 r7 = 0;
78
79 p0 = 0; /* Address registers zero'd */
80 p1 = 0;
81 p2 = 0;
82 p3 = 0;
83 p4 = 0;
84 p5 = 0;
85
86 i0 = 0; /* DAG Registers zero'd */
87 i1 = 0;
88 i2 = 0;
89 i3 = 0;
90 m0 = 0;
91 m1 = 0;
92 m3 = 0;
93 m3 = 0;
94 l0 = 0;
95 l1 = 0;
96 l2 = 0;
97 l3 = 0;
98 b0 = 0;
99 b1 = 0;
100 b2 = 0;
101 b3 = 0;
102
103 /*
104 * Set loop counters to zero, to make sure that
105 * hw loops are disabled.
106 */
107 r0 = 0;
108 lc0 = r0;
109 lc1 = r0;
110
111 SSYNC;
112
113 /* Check soft reset status */
114 p0.h = SWRST >> 16;
115 p0.l = SWRST & 0xFFFF;
116 r0.l = w[p0];
117
118 cc = bittst(r0, 15);
119 if !cc jump no_soft_reset;
120
121 /* Clear Soft reset */
122 r0 = 0x0000;
123 w[p0] = r0;
124 ssync;
125
126no_soft_reset:
127 nop;
128
129 /* Clear EVT registers */
130 p0.h = (EVT_EMULATION_ADDR >> 16);
131 p0.l = (EVT_EMULATION_ADDR & 0xFFFF);
132 p0 += 8;
133 p1 = 14;
134 r1 = 0;
135 LSETUP(4,4) lc0 = p1;
136 [ p0 ++ ] = r1;
137
138 p0.h = hi(SIC_IWR);
139 p0.l = lo(SIC_IWR);
140 r0.l = 0x1;
141 w[p0] = r0.l;
142 SSYNC;
143
144 sp.l = (0xffb01000 & 0xFFFF);
145 sp.h = (0xffb01000 >> 16);
146
147 /*
148 * Check if the code is in SDRAM
149 * If the code is in SDRAM, skip SDRAM initializaiton
150 */
151 call get_pc;
152 r3.l = 0x0;
153 r3.h = 0x2000;
154 cc = r0 < r3 (iu);
155 if cc jump sdram_initialized;
156 call init_sdram;
157 /* relocate into to RAM */
158sdram_initialized:
159 call get_pc;
160offset:
161 r2.l = offset;
162 r2.h = offset;
163 r3.l = start;
164 r3.h = start;
165 r1 = r2 - r3;
166
167 r0 = r0 - r1;
168 p1 = r0;
169
170 p2.l = (CFG_MONITOR_BASE & 0xffff);
171 p2.h = (CFG_MONITOR_BASE >> 16);
172
173 p3 = 0x04;
174 p4.l = ((CFG_MONITOR_BASE + CFG_MONITOR_LEN) & 0xffff);
175 p4.h = ((CFG_MONITOR_BASE + CFG_MONITOR_LEN) >> 16);
176loop1:
177 r1 = [p1 ++ p3];
178 [p2 ++ p3] = r1;
179 cc=p2==p4;
180 if !cc jump loop1;
181 /*
182 * configure STACK
183 */
184 r0.h = (CONFIG_STACKBASE >> 16);
185 r0.l = (CONFIG_STACKBASE & 0xFFFF);
186 sp = r0;
187 fp = sp;
188
189 /*
190 * This next section keeps the processor in supervisor mode
191 * during kernel boot. Switches to user mode at end of boot.
192 * See page 3-9 of Hardware Reference manual for documentation.
193 */
194
195 /* To keep ourselves in the supervisor mode */
196 p0.l = (EVT_IVG15_ADDR & 0xFFFF);
197 p0.h = (EVT_IVG15_ADDR >> 16);
198
199 p1.l = _real_start;
200 p1.h = _real_start;
201 [p0] = p1;
202
203 p0.l = (IMASK & 0xFFFF);
204 p0.h = (IMASK >> 16);
205 r0.l = LO(IVG15_POS);
206 r0.h = HI(IVG15_POS);
207 [p0] = r0;
208 raise 15;
209 p0.l = WAIT_HERE;
210 p0.h = WAIT_HERE;
211 reti = p0;
212 rti;
213
214WAIT_HERE:
215 jump WAIT_HERE;
216
217.global _real_start;
218_real_start:
219 [ -- sp ] = reti;
220
221#ifdef CONFIG_EZKIT561
222 p0.l = (WDOG_CTL & 0xFFFF);
223 p0.h = (WDOG_CTL >> 16);
224 r0 = WATCHDOG_DISABLE(z);
225 w[p0] = r0;
226#endif
227
228 /* DMA reset code to Hi of L1 SRAM */
229copy:
230 P1.H = hi(SYSMMR_BASE); /* P1 Points to the beginning of SYSTEM MMR Space */
231 P1.L = lo(SYSMMR_BASE);
232
233 R0.H = reset_start; /* Source Address (high) */
234 R0.L = reset_start; /* Source Address (low) */
235 R1.H = reset_end;
236 R1.L = reset_end;
237 R2 = R1 - R0; /* Count */
238 R1.H = hi(L1_ISRAM); /* Destination Address (high) */
239 R1.L = lo(L1_ISRAM); /* Destination Address (low) */
240 R3.L = DMAEN; /* Source DMAConfig Value (8-bit words) */
241 R4.L = (DI_EN | WNR | DMAEN); /* Destination DMAConfig Value (8-bit words) */
242
243DMA:
244 R6 = 0x1 (Z);
245 W[P1+OFFSET_(MDMA_S0_X_MODIFY)] = R6; /* Source Modify = 1 */
246 W[P1+OFFSET_(MDMA_D0_X_MODIFY)] = R6; /* Destination Modify = 1 */
247
248 [P1+OFFSET_(MDMA_S0_START_ADDR)] = R0; /* Set Source Base Address */
249 W[P1+OFFSET_(MDMA_S0_X_COUNT)] = R2; /* Set Source Count */
250 /* Set Source DMAConfig = DMA Enable,
251 Memory Read, 8-Bit Transfers, 1-D DMA, Flow - Stop */
252 W[P1+OFFSET_(MDMA_S0_CONFIG)] = R3;
253
254 [P1+OFFSET_(MDMA_D0_START_ADDR)] = R1; /* Set Destination Base Address */
255 W[P1+OFFSET_(MDMA_D0_X_COUNT)] = R2; /* Set Destination Count */
256 /* Set Destination DMAConfig = DMA Enable,
257 Memory Write, 8-Bit Transfers, 1-D DMA, Flow - Stop, IOC */
258 W[P1+OFFSET_(MDMA_D0_CONFIG)] = R4;
259
260WAIT_DMA_DONE:
261 p0.h = hi(MDMA_D0_IRQ_STATUS);
262 p0.l = lo(MDMA_D0_IRQ_STATUS);
263 R0 = W[P0](Z);
264 CC = BITTST(R0, 0);
265 if ! CC jump WAIT_DMA_DONE
266
267 R0 = 0x1;
268 W[P1+OFFSET_(MDMA_D0_IRQ_STATUS)] = R0; /* Write 1 to clear DMA interrupt */
269
270 /* Initialize BSS Section with 0 s */
271 p1.l = __bss_start;
272 p1.h = __bss_start;
273 p2.l = _end;
274 p2.h = _end;
275 r1 = p1;
276 r2 = p2;
277 r3 = r2 - r1;
278 r3 = r3 >> 2;
279 p3 = r3;
280 lsetup (_clear_bss, _clear_bss_end ) lc1 = p3;
281 CC = p2<=p1;
282 if CC jump _clear_bss_skip;
283 r0 = 0;
284_clear_bss:
285_clear_bss_end:
286 [p1++] = r0;
287_clear_bss_skip:
288
289 p0.l = _start1;
290 p0.h = _start1;
291 jump (p0);
292
293reset_start:
294 p0.h = WDOG_CNT >> 16;
295 p0.l = WDOG_CNT & 0xffff;
296 r0 = 0x0010;
297 w[p0] = r0;
298 p0.h = WDOG_CTL >> 16;
299 p0.l = WDOG_CTL & 0xffff;
300 r0 = 0x0000;
301 w[p0] = r0;
302reset_wait:
303 jump reset_wait;
304
305reset_end: nop;
306
307_exit:
308 jump.s _exit;
309get_pc:
310 r0 = rets;
311 rts;